S1D13A05B00B200 [EPCOS]
LCD/USB Companion Chip; LCD / USB辅助芯片
| 型号： | S1D13A05B00B200 |
| 厂家： | 
EPCOS |
| 描述： | LCD/USB Companion Chip |
| 文件： | 总184页 (文件大小：1122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S1D13A05 LCD/USB Companion Chip
Hardware Functional Specification
Document Number: X40A-A-001-07
Status: Revision 7.7
Issue Date: 2012/02/27
© SEIKO EPSON CORPORATION 2002 - 2012. Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
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Epson Research and Development
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S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
Page 3
Vancouver Design Center
Table of Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Integrated Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Display Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 USB Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8 2D Acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Typical System Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 PFBGA 121-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.2 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.3 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.4 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.5 Power And Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 25
4.4 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 26
4.5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
6
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 RESET# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.1 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Revision 7.7
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6.3.2 Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.3 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.4 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.5 Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.6 Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.7 Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.8 Motorola Dragonball Interface Timing with DTACK . . . . . . . . . . . . . . . . 46
6.3.9 Motorola Dragonball Interface Timing w/o DTACK . . . . . . . . . . . . . . . . . 48
6.4 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4.1 Passive/TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4.2 Passive/TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.5 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.5.1 Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.5.2 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 54
6.5.3 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 56
6.5.4 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.5.5 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 60
6.5.6 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 62
6.5.7 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.5.8 Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.5.9 9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.5.10 Sharp HR-TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.5.11 Casio TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.5.12 TFT Type 2 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5.13 TFT Type 3 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.5.14 TFT Type 4 Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.6 USB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.1 Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.1.1 BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1.2 MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1.3 PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.1.4 PWMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.3 Clocks versus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
8.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
8.2 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.3 LCD Register Descriptions (Offset = 0h) . . . . . . . . . . . . . . . . . . . .93
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Revision 7.7
Epson Research and Development
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8.3.1 Read-Only Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.3.2 Clock Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.3.3 Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.3.4 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8.3.5 Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.3.6 Picture-in-Picture Plus (PIP+) Registers . . . . . . . . . . . . . . . . . . . . . . . 110
8.3.7 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.3.8 Extended Panel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.4 USB Registers (Offset = 4000h) . . . . . . . . . . . . . . . . . . . . . . . 135
8.5 2D Acceleration (BitBLT) Registers (Offset = 8000h) . . . . . . . . . . . . . . 153
8.6 2D Accelerator (BitBLT) Data Register Descriptions . . . . . . . . . . . . . . . 160
9
2D Accelerator (BitBLT) Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.2 BitBLT Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
10 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11 Display Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
13 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
13.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
13.2 90° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
13.2.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.3 180° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.3.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
13.4 270° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13.4.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14 Picture-in-Picture Plus (PIP+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.2 With SwivelView Enabled . . . . . . . . . . . . . . . . . . . . . . . . . 176
14.2.1 SwivelView 90° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
14.2.2 SwivelView 180° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
14.2.3 SwivelView 270° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
16 USB Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.1 USB Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 6
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19 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
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1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13A05 LCD/USB Companion
Chip. Included in this document are timing diagrams, AC and DC characteristics, register
descriptions, and power management descriptions. This document is intended for two
audiences: Video Subsystem Designers and Software Developers.
This document is updated as appropriate. Please check for the latest revision of this
document before beginning any development. The latest revision can be downloaded at
www.erd.epson.com.
We appreciate your comments on our documentation. Please contact us via email at
documentation@erd.epson.com.
1.2 Overview Description
The S1D13A05 is an LCD/USB solution designed for seamless connection to a wide
variety of microprocessors. The S1D13A05 integrates a USB slave controller and an LCD
graphics controller with an embedded 256K byte SRAM display buffer. The LCD
controller supports all standard panel types and multiple TFT types eliminating the need for
an external timing control IC. The S1D13A05 includes a Hardware Acceleration Engine to
greatly improve screen drawing functions and the built-in USB controller provides revision
1.1 compliance for applications requiring a USB client. This high level of integration
provides a low cost, low power, single chip solution to meet the demands of embedded
markets requiring USB client support, such as Mobile Communications devices and Palm-
size PCs.
The S1D13A05 utilizes a guaranteed low-latency CPU architecture that provides support
for microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data
path, write buffer and the Hardware Acceleration Engine provide high performance
bandwidth into display memory allowing for fast display updates.
TM
Additionally, products requiring a rotated display can take advantage of the SwivelView
feature which provides hardware rotation of the display memory transparent to the software
application. The S1D13A05 also provides support for “Picture-in-Picture Plus” (a variable
size Overlay window).
®
The S1D13A05, with its integrated USB client, provides impressive support for Palm OS
handhelds. However, its impartiality to CPU type or operating system makes it an ideal
display solution for a wide variety of applications.
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
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Revision 7.7
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2 Features
2.1 Integrated Frame Buffer
• Embedded 256K byte SRAM display buffer.
2.2 CPU Interface
• Direct support of the following interfaces:
Hitachi SH-4 / SH-3.
Motorola M68xxx (REDCAP2, DragonBall, ColdFire).
Motorola DragonBall SZ Support (66MHz).
Motorola “REDCAP2” - no WAIT# signal.
Generic MPU bus interface with programmable ready (WAIT#).
• “Fixed” low-latency CPU access times.
• Registers are memory-mapped - M/R# input selects between memory and register
address space.
• The complete 256K byte display buffer is directly and contiguously available through
the 18-bit address bus.
2.3 Display Support
• Single-panel, single drive passive displays.
• 4/8-bit monochrome LCD interface.
• 4/8/16-bit color LCD interface.
• Active Matrix TFT interface.
• 9/12/18-bit interface.
• Extended TFT interfaces (Type 2, 3, 4)
• ‘Direct’ support for 18-bit Sharp HR-TFT LCD (or compatible interfaces).
• ‘Direct’ support for the Casio TFT LCD (or compatible interfaces).
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2.4 Display Modes
• 1/2/4/8/16 bit-per-pixel (bpp) color depths.
• Up to 64 gray shades on monochrome passive LCD panels.
• Up to 64K colors on passive panels.
• Up to 64K colors on active matrix LCD panels.
• Example resolutions:
320x320 at a color depth of 16 bpp
160x160 at a color depth of 16 bpp (2 pages)
160x240 at a color depth of 16 bpp
2.5 Display Features
• SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
+
• Picture-in-Picture Plus (PIP ): displays a variable size window overlaid over back-
ground image.
• Pixel Doubling: independent control of both horizontal and vertical pixel doubling.
• example usage: 160x160 8 bpp can be expanded to 320x320 8 bpp without any addi-
tional memory.
• supports all color depths.
• Double Buffering/Multi-pages: provides smooth animation and instantaneous screen
updates.
2.6 Clock Source
• Three independent clock inputs: CLKI, CLKI2 and USBCLK.
• Flexible clock source selection:
• internal Bus Clock (BCLK) selected from CLKI, CLKI/2, or CLKI2
• internal Memory Clock (MCLK) selected from BCLK or BCLK divide ratio
(REG[04h)
• internal Pixel Clock (PCLK) selected from CLKI, CLKI2, MCLK, or BCLK. PCLK
can also be divided down from source
• Single clock input possible if USB support not required.
2.7 USB Device
• USB Client, revision 1.1 compliant.
• Dedicated clock input: USBCLK.
• 48MHz crystal oscillator for USBCLK.
Hardware Functional Specification
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Revision 7.7
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2.8 2D Acceleration
• 2D BitBLT engine including:
Write BitBLT
Transparent Write BitBLT
Move BitBLT
Solid Fill BitBLT
Transparent Move BitBLT
Read BitBLT
Pattern Fill BitBLT
Move BitBLT with Color Expansion
Color Expansion BitBLT
2.9 Miscellaneous
• Software initiated Video Invert.
• Software initiated Power Save mode.
• General Purpose Input/Output pins are available.
• IO Operates at 3.3 volts 10%.
• Core operates at 2.0 volts 10% or 2.5 volts 10%.
• 121-pin PFBGA package.
S1D13A05
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Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
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3 Typical System Implementation Diagrams
3.1 Typical System Diagrams.
Oscillator
Generic #1
BUS
IOVDD
VSS
BS#
AB0
16-bit
Single
LCD
FPDAT[15:0]
FPFRAME
D[15:0]
FPFRAME
M/R#
CS#
A[27:18]
CSn#
Decoder
Display
FPLINE
FPSHIFT
DRDY
FPLINE
FPSHIFT
MOD
A[17:1]
D[15:0]
AB[17:1]
DB[15:0]
WE0#
WE1#
S1D13A05
WE0#
WE1#
GPIO0
RD0#
RD1#
RD#
RD/WR#
WAIT#
WAIT#
BUSCLK
RESET#
CLKI
RESET#
Figure 3-1: Typical System Diagram (Generic #1 Bus)
.
Oscillator
Generic #2
BUS
IOVDD
BS#
9-bit
TFT
Display
RD/WR#
FPDAT[8:0]
D[8:0]
M/R#
A[27:18]
Decoder
FPFRAME
FPFRAME
CSn#
CS#
FPLINE
FPSHIFT
DRDY
FPLINE
FPSHIFT
DRDY
A[17:0]
D[15:0]
AB[17:0]
DB[15:0]
WE#
S1D13A05
WE0#
WE1#
BHE#
GPIO0
RD#
RD#
WAIT#
WAIT#
BUSCLK
RESET#
CLKI
RESET#
Figure 3-2: Typical System Diagram (Generic #2 Bus)
Hardware Functional Specification
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Revision 7.7
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.
Oscillator
SH-4
BUS
AB0
VSS
12-bit
TFT
Display
FPDAT15
D11
D10
A[25:18]
CSn#
M/R#
CS#
Decoder
FPDAT12
FPDAT[9:0]
D[9:0]
FPFRAME
FPLINE
FPFRAME
FPLINE
A[17:1]
D[15:0]
WE0#
AB[17:1]
DB[15:0]
WE0#
FPSHIFT
DRDY
FPSHIFT
DRDY
WE1#
BS#
WE1#
S1D13A05
BS#
RD/WR#
RD#
GPIO0
RD/WR#
RD#
RDY#
WAIT#
CKIO
CLKI
RESET#
RESET#
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)
.
Oscillator
SH-3
BUS
AB0
VSS
18-bit
TFT
Display
A[25:18]
CSn#
M/R#
CS#
FPDAT[17:0]
FPFRAME
Decoder
D[17:0]
FPFRAME
A[17:1]
D[15:0]
AB[17:1]
DB[15:0]
FPLINE
FPSHIFT
DRDY
FPLINE
FPSHIFT
DRDY
WE0#
WE1#
BS#
WE0#
WE1#
S1D13A05
BS#
RD/WR#
RD#
GPO0
RD/WR#
RD#
WAIT#
WAIT#
CKIO
CLKI
RESET#
RESET#
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)
S1D13A05
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Hardware Functional Specification
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.
Oscillator
MC68K #1
BUS
IOVDD
RD#
FPDAT[17:0]
FPFRAME
FPLINE
D[17:0]
SPS
18-bit
HR-TFT
Display
WE0#
A[23:18]
FC0, FC1
LP
M/R#
Decoder
FPSHIFT
CLK
GPIO0
GPIO1
GPIO2
GPIO3
PS
CS#
Decoder
CLS
REV
SPL
A[17:1]
D[15:0]
AB[17:1]
DB[15:0]
LDS#
AB0
S1D13A05
UDS#
AS#
WE1#
BS#
R/W#
RD/WR#
WAIT#
DTACK#
CLK
CLKI
RESET#
RESET#
Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)
.
Oscillator
MC68K #2
BUS
A[31:18]
FC0, FC1
M/R#
Decoder
FPDAT[17:0]
D[17:0]
SPS
18-bit
HR-TFT
Display
CS#
FPFRAME
FPLINE
Decoder
LP
A[17:0]
AB[17:0]
DB[15:0]
FPSHIFT
CLK
D[31:16]
GPIO0
GPIO1
GPIO2
GPIO3
PS
CLS
REV
SPL
DS#
AS#
WE1#
BS#
S1D13A05
R/W#
SIZ1
RD/WR#
RD#
SIZ0
WE0#
WAIT#
DSACK1#
CLK
CLKI
RESET#
RESET#
Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)
Hardware Functional Specification
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.
Oscillator
REDCAP2
BUS
IOVDD
BS#
4-bit
Single
LCD
Display
FPDAT[7:4]
FPSHIFT
D[3:0]
M/R#
CS#
A[21:18]
CSn
Decoder
FPSHIFT
FPFRAME
FPLINE
DRDY
FPFRAME
FPLINE
MOD
A[17:1]
D[15:0]
AB[17:1]
DB[15:0]
S1D13A05
R/W
OE
GPIO0
RD/WR#
RD#
EB1
WE0#
WE1#
EB0
CLK
CLKI
RESET_OUT
RESET#
AB0
VSS
*Note: CSn# can be any of CS0-CS4
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)
.
Oscillator
MC68EZ328/
MC68VZ328
IOVDD
BS#
DragonBall
BUS
8-bit
Single
LCD
Display
RD/WR#
M/R#
FPDAT[7:0]
FPSHIFT
D[7:0]
FPSHIFT
A[25:18]
Decoder
FPFRAME
FPLINE
DRDY
FPFRAME
FPLINE
MOD
CSX
CS#
A[17:1]
D[15:0]
AB[17:1]
DB[15:0]
S1D13A05
GPIO0
LWE
WE0#
WE1#
UWE
OE
RD#
DTACK
WAIT#
CLKO
CLKI
RESET
RESET#
AB0
VSS
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)
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3.2 USB Interface
USB Socket
S1D13A05
150kΩ
VBus
USBDETECT
(GPIO5)
300kΩ
USBPUP
(GPIO4)
Full Speed Device
IOVDD
1.5kΩ
20Ω
20Ω
USBDP
(GPIO7)
DP
USBDM
(GPIO6)
DM
300kΩ
NNCD5.6LG
Overvoltage
Protection
ESD
Protection
VSS
GND
Figure 3-9: USB Typical Implementation
Hardware Functional Specification
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4 Pins
4.1 Pinout Diagrams
4.1.1 PFBGA 121-pin
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11
BOTTOM VIEW
Figure 4-1: Pinout Diagram - PFBGA 121-pin
Table 4-1: PFBGA 121-pin Mapping
NC
GPO0
GPO1
DB12
WAIT#
RESET#
RD#
IOVDD
VSS
DB7
DB8
DB3
DB4
DB0
DB1
GPIO7
GPIO6
GPO3
IOVDD
GPIO5
GPO4
AB13
AB17
AB16
AB14
AB15
6
GPIO3
GPIO2
GPIO1
GPIO4
FPDAT5
FPDAT8
TESTEN
CNF3
GPIO0
IRQ
IOVDD
DRDY
COREVDD
VSS
NC
L
K
J
GPO6
DB9
DB6
DB5
DB2
USBCLK FPFRAME COREVDD
GPO7
DB11
DB15
VSS
DB10
DB14
RD/WR#
M/R#
AB2
DB13
IOVDD
WE1#
CS#
GPO2
VSS
CLKI
WE0#
AB12
AB9
GPO5
FPLINE
FPDAT2
VSS
FPSHIFT
FPDAT3
FPDAT7
FPDAT0
FPDAT4
IOVDD
H
G
F
FPDAT1
FPDAT6
FPDAT9
BS#
FPDAT12 FPDAT11 FPDAT10
E
D
C
B
A
AB0
AB1
AB8
FPDAT13 FPDAT16 FPDAT15 FPDAT14
USBOSCO COREVDD
AB3
AB6
CNF2
CNF5
CNF4
NC
CNF6
CLKI2
PWMOUT
9
FPDAT17
VSS
GPO8
GPO9
NC
USBOSCI
VSS
COREVDD
2
AB5
GPO10
AB7
AB10
AB11
5
CNF1
NC
AB4
CNF0
IOVDD
10
1
3
4
7
8
11
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4.2 Pin Descriptions
Key:
I
=
=
=
=
=
=
=
=
=
=
=
=
=
Input
O
Output
IO
Bi-Directional (Input/Output)
Power pin
P
CI
CMOS input
a
LI
LVTTL input
LB2A
LB3P
LO3
LB3M
T1
LVTTL IO buffer (6mA/-6mA@3.3V)
Low noise LVTTL IO buffer (6mA/-6mA@3.3V)
Low noise LVTTL Output buffer (3mA/-3mA@3.3V)
Low noise LVTTL IO buffer with input mask (3mA/-3mA@3.3V)
Test mode control input with pull-down resistor (typical value of 50KΩ at 3.3V)
High Impedance
Hi-Z
CUS
Custom Cell Type
a
LVTTL is Low Voltage TTL.
4.2.1 Host Interface
Table 4-2: Host Interface Pin Descriptions
I/O type
(see key
above)
PFBGA
Pin #
RESET#
State
Pin Name
Description
This input pin has multiple functions.
• For Generic #1, this pin is not used and should be connected to VSS.
• For Generic #2, this pin inputs system address bit 0 (A0).
• For SH-3/SH-4, this pin is not used and should be connected to VSS.
• For MC68K #1, this pin inputs the lower data strobe (LDS#).
• For MC68K #2, this pin inputs system address bit 0 (A0).
AB0
D1
LI
⎯
• For REDCAP2, this pin is not used and should be connected to VSS.
• For DragonBall, this pin is not used and should be connected to VSS.
D6,C6,A6,
B6,E6,D5,
A5,B5,C5,
D4,A4,C4,
B3,A3,C3,
D3,D2
AB[17:1]
CI
⎯
System address bus bits 17-1.
Input data from the system data bus.
• For Generic #1, these pins are connected to D[15:0].
• For Generic #2, these pins are connected to D[15:0].
• For SH-3/SH-4, these pins are connected to D[15:0].
• For MC68K #1, these pins are connected to D[15:0].
G2, G3,
H4, H1,
H2, H3,
DB[15:0] J2, K3, L3,
J3, J4, K4,
LB2A
Hi-Z
• For MC68K #2, these pins are connected to D[31:16] for a 32-bit device
(e.g. MC68030) or D[15:0] for a 16-bit device (e.g. MC68340).
L4, J5, K5,
L5
• For REDCAP2, these pins are connected to D[15:0].
• For DragonBall, these pins are connected to D[15:0].
Hardware Functional Specification
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Table 4-2: Host Interface Pin Descriptions
I/O type
(see key
above)
PFBGA
Pin #
RESET#
State
Pin Name
Description
This input pin has multiple functions.
• For Generic #1, this pin inputs the write enable signal for the lower data
byte (WE0#).
• For Generic #2, this pin inputs the write enable signal (WE#)
• For SH-3/SH-4, this pin inputs the write enable signal for data byte 0
(WE0#).
WE0#
E5
LI
⎯
• For MC68K #1, this pin must be tied to IO V
DD
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For REDCAP2, this pin inputs the byte enable signal for the D[7:0] data
byte (EB1).
• For DragonBall, this pin inputs the byte enable signal for the D[7:0] data
byte (LWE).
This input pin has multiple functions.
• For Generic #1, this pin inputs the write enable signal for the upper data
byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for the high data
byte (BHE#).
• For SH-3/SH-4, this pin inputs the write enable signal for data byte 1
(WE1#).
WE1#
F4
LI
⎯
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For REDCAP2, this pin inputs the byte enable signal for the D[15:8] data
byte (EB0).
• For DragonBall, this pin inputs the byte enable signal for the D[15:8]
data byte (UWE).
CS#
E4
E3
CI
LI
⎯
⎯
Chip select input.
This input pin is used to select between the display buffer and register
address spaces of the S1D13A05. M/R# is set high to access the display
buffer and low to access the registers.
M/R#
This input pin has multiple functions.
• For Generic #1, this pin must be tied to IO V
• For Generic #2, this pin must be tied to IO V
.
DD
.
DD
• For SH-3/SH-4, this pin inputs the bus start signal (BS#).
• For MC68K #1, this pin inputs the address strobe (AS#).
• For MC68K #2, this pin inputs the address strobe (AS#).
BS#
E2
LI
⎯
• For REDCAP2, this pin must be tied to IO V
.
DD
• For DragonBall, this pin must be tied to IO V
.
DD
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Table 4-2: Host Interface Pin Descriptions
I/O type
(see key
above)
PFBGA
Pin #
RESET#
State
Pin Name
Description
This input pin has multiple functions.
• For Generic #1, this pin inputs the read command for the upper data
byte (RD1#).
• For Generic #2, this pin must be tied to IO V
.
DD
• For SH-3/SH-4, this pin inputs the RD/WR# signal. The S1D13A05
needs this signal for early decode of the bus cycle.
RD/WR#
F3
LI
⎯
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For REDCAP2, this pin inputs the R/W signal.
• For DragonBall, this pin must be tied to IO V
This input pin has multiple functions.
.
DD
• For Generic #1, this pin inputs the read command for the lower data
byte (RD0#).
• For Generic #2, this pin inputs the read command (RD#).
• For SH-3/SH-4, this pin inputs the read signal (RD#).
RD#
E1
LI
⎯
• For MC68K #1, this pin must be tied to IO V
.
DD
• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
• For REDCAP2, this pin inputs the output enable (OE).
• For DragonBall, this pin inputs the output enable (OE).
During a data transfer, this output pin is driven active to force the system to
insert wait states. It is driven inactive to indicate the completion of a data
transfer. WAIT# is released to the high impedance state after the data
transfer is complete. Its active polarity is configurable.
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
• For SH-3 mode, this pin outputs the wait request signal (WAIT#).
• For SH-4 mode, this pin outputs the device ready signal (RDY#).
• For MC68K #1, this pin outputs the data transfer acknowledge signal
(DTACK#).
WAIT#
G1
LB2A
Hi-Z
• For MC68K #2, this pin outputs the data transfer and size acknowledge
bit 1 (DSACK1#).
• For REDCAP2, this pin is unused (Hi-Z).
• For DragonBall, this pin outputs the data transfer acknowledge signal
(DTACK).
Note: This pin should be tied to the inactive voltage level as selected by
CNF5, using a pull-up or pull-down resistor. If CNF5 = 1, the WAIT# pin
should be tied low using a pull-down resistor. If CNF5 = 0, the WAIT# pin
should be tied high using a pull-up resistor. If WAIT# is not used, this pin
should be tied either high or low using a pull-up or pull-down resistor.
Active low input to set all internal registers to the default state and to force all
signals to their inactive states.
RESET#
F1
LI
⎯
Hardware Functional Specification
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4.2.2 LCD Interface
Table 4-3: LCD Interface Pin Descriptions
I/O type
RESET#
Pin Name PFBGA Pin# (see key
above)
Description
State
C10,D9,D10,
D11,D8,E9,
E10,E11,
FPDAT[17:0] E8,F7,F10,
F8,G7,G11,
LB3P
LB3P
LB3P
LB3P
0
Panel Data bits 17-0.
G10,G9,G8,
H11
This output pin has multiple functions.
• Frame Pulse
• SPS for HR-TFT
FPFRAME
J9
H9
0
0
0
• GSRT for Casio
• STV for TFT Type 2
• STV for TFT Type 3
This output pin has multiple functions.
• Line Pulse
• LP for HR-TFT
FPLINE
• GPCK for Casio
• STB for TFT Type 2
• LP for TFT Type 3
This output pin has multiple functions.
• Shift Clock
• DCLK for HR-TFT
• CLK for Casio
FPSHIFT
H10
• CLK for TFT Type 2
• CPH for TFT Type 3
This output pin has multiple functions.
• LCD backplane bias signal (MOD) for all other LCD panels
• 2nd shift clock (FPSHIFT2) for passive LCD with Format 1 interface
• Display enable (DRDY) for TFT panels
• INV for TFT Type 2/3
DRDY
K9
LO3
0
• DRDY for TFT Type 4
• General Purpose Output
GPO0
GPO1
K1
J1
LO3
LO3
0
0
This is a general purpose output
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as VCOM
• General purpose output bit otherwise
This output pin has multiple functions.
GPO2
GPO3
H5
J6
LO3
LO3
0
0
• When in TFT Type 3 mode, operates as XOEV
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as CMD
• General purpose output bit otherwise
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Table 4-3: LCD Interface Pin Descriptions
I/O type
RESET#
Pin Name PFBGA Pin# (see key
above)
Description
State
This output pin has multiple functions.
GPO4
GPO5
GPO6
GPO7
GPO8
GPO9
GPO10
F6
H8
LO3
LO3
LO3
LO3
LO3
LO3
LO3
0
• When in TFT Type 3 mode, operates as PCLK1
• General purpose output bit otherwise
This output pin has multiple functions.
0
0
0
0
0
0
• When in TFT Type 3 mode, operates as PCLK2
• General purpose output bit otherwise
This output pin has multiple functions.
K11
J11
C11
B11
B4
• When in TFT Type 3 mode, operates as XRESH
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as XRESV
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as XOHV
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as XSTBY
• General purpose output bit otherwise
This output pin has multiple functions.
• When in TFT Type 3 mode, operates as PMDE
• General purpose output bit otherwise
This pin has multiple functions.
• PS for HR-TFT
• POL for Casio
• VCLK for TFT Type 2
• CPV for TFT Type 3
GPIO0
L8
LB3M
⎯
• General purpose IO pin 0 (GPIO0)
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
This pin has multiple functions.
• CLS for HR-TFT
• GRES for Casio
• AP for TFT Type 2
• OE for TFT Type 3
GPIO1
J7
LB3M
⎯
• General purpose IO pin 1 (GPIO1)
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
Hardware Functional Specification
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Table 4-3: LCD Interface Pin Descriptions
I/O type
RESET#
Pin Name PFBGA Pin# (see key
above)
Description
State
This pin has multiple functions.
• REV for HR-TFT
• FRP for Casio
• POL for TFT Type 2/3
• General purpose IO pin 2 (GPIO2)
GPIO2
K7
LB3M
⎯
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
This pin has multiple functions.
• SPL for HR-TFT
• STH for Casio
• STH for TFT Type 2
• EIO for TFT Type 3
GPIO3
L7
LB3M
⎯
• General purpose IO pin 3 (GPIO3)
When this pin is used for the above display modes, it must be configured
as an output using REG[64h] after every RESET. Otherwise, it defaults to
a Hi-Z state after every RESET and must either be configured as an
output or be pulled high or low externally to avoid unnecessary current
drain.
This pin has multiple functions.
• USBPUP
• General purpose IO pin 4 (GPIO4)
GPIO4
GPIO5
H7
G6
LB3M
LB3M
⎯
⎯
This pin is Hi-Z after every RESET and must either be configured as an
output using REG[64h] or be pulled high or low externally to avoid
unnecessary current drain.
This pin has multiple functions.
• USBDETECT
• General purpose IO pin 5 (GPIO5)
This pin always defaults as an input. When not used as a USBDETECT
pin, it must either be configured as an output using REG[64h] or be pulled
high or low externally to avoid unnecessary current drain.
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Table 4-3: LCD Interface Pin Descriptions
I/O type
RESET#
Pin Name PFBGA Pin# (see key
above)
Description
State
This pin has multiple functions.
• USBDM
• General purpose IO pin 6 (GPIO6)
GPIO6
GPIO7
K6
L6
CUS
CUS
⎯
When not used as a USB connection, this pin defaults to a Hi-Z state after
every RESET and must either be configured as an output using REG[64h]
or be pulled high or low externally to avoid unnecessary current drain.
This pin has multiple functions.
• USBDP
• General purpose IO pin 7
⎯
When not used as a USB connection, this pin defaults to a Hi-Z state after
every RESET and must either be configured as an output using REG[64h]
or be pulled high or low externally to avoid unnecessary current drain.
This output pin is the IRQ pin for USB. When IRQ is activated, an active
high pulse is generated and stays high until the IRQ is serviced by
software at REG[404Ah] or REG[404Ch].
IRQ
K8
A9
LO3
LO3
0
0
This pin has multiple functions.
• PWM Clock output
PWMOUT
• General purpose output
Hardware Functional Specification
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4.2.3 Clock Input
Table 4-4: Clock Input Pin Descriptions
I/O type
(see key
above)
PFBGA
Pin Name
RESET#
State
Description
Pin#
CLKI
F5
B9
CI
CI
—
—
Typically used as input clock source for bus clock and memory clock
Optionally used as input clock source for pixel clock
Used as input clock source for USB.
CLKI2
USBCLK
J8
CI
—
Note: If this pin is not connected to an input clock source, this pin
must be connected to VSS.
USB Crystal Oscillator feedback input from crystal.
For an example implementation circuit using a crystal oscillator, see
Section 16.1, “USB Oscillator Circuit” on page 179.
USBOSCI
B1
C1
I
—
—
Note: If this pin is not connected to a USB Crystal Oscillator, this pin
must be connected to VSS.
USB Crystal Oscillator output to crystal.
For an example implementation circuit using a crystal oscillator, see
Section 16.1, “USB Oscillator Circuit” on page 179.
USBOSCO
O
4.2.4 Miscellaneous
Table 4-5: Miscellaneous Pin Descriptions
PFBGA
Pin Name
I/O type (see RESET#
Description
Pin#
key above)
State
These inputs are used to configure the S1D13A05 - see Table 4-7:
“Summary of Power-On/Reset Options,” on page 25.
C9,C8,B8,
D7,C7,B7,
A7
CNF[6:0]
TESTEN
CI
—
Note: These pins are used for configuration of the S1D13A05 and
must be connected directly to IO V or V
.
DD
SS
Test Enable input used for production test only (has type 1 pull-down
resistor with a typical value of 50KΩ at 3.3V).
E7
T1
⎯
Note: This pin must be left un-connected.
4.2.5 Power And Ground
Table 4-6: Power And Ground Pin Descriptions
I/O type
(see key
above)
PFBGA
Pin#
RESET#
State
Pin Name
Description
L2,G4,H6,
L9,A10,F11
IOVDD
P
—
IO power supply.
A2,C2,L10,
J10
COREVDD
P
P
—
Core power supply.
B2,F2,K2,
G5,F9,B10,
K10
VSS
—
GND for IOVDD and COREVDD.
S1D13A05
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4.3 Summary of Configuration Options
These pins are used for configuration of the S1D13A05 and must be connected directly to
IOV or V . The state of CNF[6:0] are latched on the rising edge of RESET#. Changing
DD
SS
state at any other time has no effect.
Table 4-7: Summary of Power-On/Reset Options
S1D13A05
Configuration
Input
Power-On/Reset State
1 (connected to IO V
)
0 (connected to V
)
DD
SS
Select host bus interface as follows:
CNF4 CNF2 CNF1 CNF0
Host Bus
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
SH-4/SH-3 interface, Big Endian
SH-4/SH-3 interface, Little Endian
MC68K #1, Big Endian
Reserved
MC68K #2, Big Endian
Reserved
Generic #1, Big Endian
Generic #1, Little Endian
Reserved
Generic #2, Little Endian
REDCAP2, Big Endian
Reserved
CNF4,CNF[2:0]
DragonBall (MC68EZ328/VZ328/SZ328), Big Endian
Reserved
Reserved
CNF3
Reserved. Must be set to 1.
WAIT# is active high
CNF5
(see note)
WAIT# is active low
CNF6
CLKI to BCLK divide ratio 2:1
CLKI to BCLK divide ratio 1:1
Note
If CNF5 = 1, the WAIT# pin should be tied low using a pull-down resistor. If CNF5 = 0,
the WAIT# pin should be tied high using a pull-up resistor. If WAIT# is not used, this
pin should be tied either high or low using a pull-up or pull-down resistor.
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 26
Epson Research and Development
Vancouver Design Center
4.4 Host Bus Interface Pin Mapping
Table 4-8: Host Bus Interface Pin Mapping
Motorola
S1D13A05
Pin Name
Hitachi
SH-3 /SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
MC68EZ328/
MC68VZ328
DragonBall
Generic #1
Generic #2
AB[17:1]
AB0
A[17:1]
A[17:1]
A0
A[17:1]
A[17:1]
LDS#
A[17:1]
A0
A[17:1]
A[17:1]
1
1
1
1
A0
A0
A0
A0
2
DB[15:0]
CS#
D[15:0]
D[15:0]
D[15:0]
CSn#
D[15:0]
D[15:0]
D[15:0]
CSn
D[15:0]
CSX
External Decode
External Decode
M/R#
CLKI
External Decode
BUSCLK
BUSCLK
CKIO
BS#
CLK
AS#
CLK
AS#
CLK
CLKO
BS#
Connected to IOV
Connected to IOV
DD
DD
Connected to
IOV
Connected to
RD/WR#
RD#
RD1#
RD0#
RD/WR#
RD#
R/W#
R/W#
SIZ1
R/W
OE
IOV
DD
DD
Connected to
RD#
OE
IOV
DD
Connected to
IOV
WE0#
WE1#
WE0#
WE1#
WE#
BHE#
WE0#
WE1#
SIZ0
DS#
EB1
EB0
LWE
UWE
DD
UDS#
WAIT#/
RDY#
WAIT#
RESET#
WAIT#
RESET#
WAIT#
RESET#
DTACK#
RESET#
DSACK1#
RESET#
N/A
DTACK
RESET
RESET#
RESET_OUT
Note
1
A0 for these busses is not used internally by the S1D13A05 and should be connected
to V .
SS
2
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
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Vancouver Design Center
4.5 LCD Interface Pin Mapping
Table 4-9: LCD Interface Pin Mapping
Monochrome Passive
Panel
Color Passive Panel
Single
Color TFT Panel
1
1
Pin Name
Sharp
HR-TFT
Casio
TFT Type 2
TFT Type 3
TFT Type 4
USB
Single
Generic TFT (TFT Type 1)
1
1
TFT
Format 1
8-bit
Format 2
8-bit
4-bit
16-Bit
3
4-bit
8-bit
9-bit
12-bit
18-bit
18-bit
SPS
LP
18-bit
GSRT
GPCK
CLK
18-bit
STV
STB
CLK
18-bit
STV
LP
18-bit
FPFRAME
FPLINE
FPFRAME
FPLINE
FPFRAME
FPLINE
⎯
⎯
⎯
FPSHIFT
FPSHIFT
DCLK
CPH
FPSHIFT
FPSHIFT
2
DRDY
MOD
MOD
DRDY
driven 0
no connect
INV
INV
DRDY
⎯
2
2
2
2
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
FPDAT16
FPDAT17
GPIO0
driven 0
driven 0
driven 0
driven 0
D0
D0
driven 0
driven 0
driven 0
driven 0
D0 (B5)
D0 (G3)
D0 (R6)
R2
R3
R2
R5
R4
R5
R4
R5
R4
R5
R4
R5
R4
R5
R4
⎯
2
2
D1
D1 (R5)
D1 (R3)
D1 (G5)
R1
⎯
2
2
2
2
2
2
D2
D2 (G4)
D2 (B2)
D2 (B4)
D3 (R4)
D8 (B5)
D9 (R5)
R0
R1
R3
R3
R3
R3
R3
R3
⎯
2
2
D3
D3 (B3)
D3 (G2)
G2
G3
G5
G5
G5
G5
G5
G5
⎯
2
2
2
D4
D0 (R2)
D1 (B1)
D4 (R3)
D4 (R2)
G1
G2
G4
G4
G4
G4
G4
G4
⎯
2
2
2
2
D1
D5
D5 (G2)
D5 (B1)
G0
G1
G3
G3
G3
G3
G3
G3
⎯
2
2
2
D2
D6
D2 (G1)
D3 (R1)
D6 (B1)
D6 (G1)
D10 (G4)
B2
B3
B5
B5
B5
B5
B5
B5
⎯
2
2
2
2
D3
D7
D7 (R1)
D7 (R1)
D11 (B3)
B1
B2
B4
B4
B4
B4
B4
B4
⎯
2
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
D4 (G3)
B0
B1
B3
B3
B3
B3
B3
B3
⎯
2
D5 (B2)
D6 (R2)
D7 (G1)
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
R0
R2
R2
R2
R2
R2
R2
⎯
2
driven 0
driven 0
G0
R1
R1
R1
R1
R1
R1
⎯
2
R0
R0
R0
R0
R0
R0
⎯
2
2
D12 (R3)
G2
G2
G2
G2
G2
G2
⎯
D13 (G2)
driven 0
driven 0
B0
G1
G1
G1
G1
G1
G1
⎯
2
D14 (B1)
D15 (R1)
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
G0
G0
G0
G0
G0
G0
⎯
2
B2
B2
B2
B2
B2
B2
⎯
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
B1
B1
B1
B1
B1
B1
⎯
B0
B0
B0
B0
B0
B0
⎯
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
PS
POL
GRES
FRP
STH
GPIO4
GPIO5
GPIO6
GPIO7
VCLK
AP
CPV
OE
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
⎯
GPIO1
CLS
REV
SPL
GPIO4
GPIO5
GPIO6
GPIO7
⎯
GPIO2
POL
STH
GPIO4
GPIO5
GPIO6
GPIO7
POL
EIO
GPIO4
GPIO5
GPIO6
GPIO7
⎯
GPIO3
⎯
GPIO4
USBPUP
GPIO5
USBDETECT
GPIO6
USBDM
GPIO7
USBDP
⎯
GPO0
GPO0 (General Purpose Output)
GPO1
GPO1
VCOM
XOEV
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
GPO8
GPO9
GPO10
⎯
GPO2
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
GPO8
GPO9
⎯
GPO3
CMD
⎯
GPO4
PCLK1
PCLK2
XRESH
XRESV
XOHV
XSTBY
PMDE
⎯
GPO5
⎯
GPO6
⎯
GPO7
⎯
GPO8
⎯
GPO9
⎯
GPO10
PWMOUT
GPO10
⎯
PWMOUT
⎯
Note
1
GPIO pins which are used by the HR-TFT, Casio, TFT Type 2, and TFT Type
3 interfaces, must be configured as outputs using REG[64h] bits 23-16 after every
RESET or power-up.
2
These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
Section 6.5, “Display Interface” on page 52.
3
The S1D13A05 also supports the 9-bit and 12-bit variations of the Type 4 TFT panel.
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 28
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5 D.C. Characteristics
Note
When applying Supply Voltages to the S1D13A05, Core V must be applied to the
DD
chip before, or simultaneously with IO V , or damage to the chip may result.
DD
Table 5-1: Absolute Maximum Ratings
Symbol
Core V
Parameter
Supply Voltage
Rating
Units
V
V
V
V
V
- 0.3 to 3.0
- 0.3 to 4.0
DD
DD
SS
SS
SS
SS
IO V
Supply Voltage
V
V
V
T
Input Voltage
- 0.3 to IO V + 0.5
V
IN
OUT
DD
Output Voltage
- 0.3 to IO V + 0.5
V
DD
Storage Temperature
Solder Temperature/Time
-65 to 150
° C
° C
STG
SOL
T
260 for 10 sec. max at lead
Table 5-2: Recommended Operating Conditions
Symbol
Core V
Parameter
Supply Voltage
Condition
= 0 V
Min
Typ
Max
Units
V
V
V
1.8 (note 1) 2.0 (note 1) 2.2 (note 1)
V
V
V
V
SS
SS
SS
DD
DD
= 0 V
2.25
3.0
2.5
3.3
2.75
3.6
IO V
Supply Voltage
= 0 V
V
V
IO V
SS
SS
DD
V
Input Voltage
IN
CORE V
85
DD
T
Operating Temperature
-40
25
° C
OPR
1. When Core VDD is 2.0V 10%, the MCLK must be less than or equal to 30MHz (MCLK ≤ 30MHz)
Table 5-3: Electrical Characteristics for VDD = 3.3V typical
Symbol
Parameter
Quiescent Current
Condition
Quiescent Conditions
Min
Typ
Max
170
Units
I
I
I
μA
μA
μA
DDS
Input Leakage Current
Output Leakage Current
-1
-1
1
1
IZ
OZ
VDD = min
V
High Level Output Voltage
Low Level Output Voltage
I
=
-3mA (Type 1)
-6mA (Type 2)
V - 0.4
DD
V
OH
OL
OH
VDD = min
I
V
=
3mA (Type 1)
6mA (Type 2)
0.4
V
OL
V
V
High Level Input Voltage
Low Level Input Voltage
Pull Down Resistance
LVTTL Level, V = max 2.0
V
IH
DD
LVTTL Level, V = min
0.8
120
10
V
IL
DD
R
C
C
C
V
= V
DD
20
50
kΩ
pF
pF
pF
PD
IN
Input Pin Capacitance
I
Output Pin Capacitance
Bi-Directional Pin Capacitance
10
O
10
IO
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
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6 A.C. Characteristics
Conditions: IO V = 3.3V ± 10%
DD
T = -40° C to 85° C
A
T
and T for all inputs must be < 5 nsec (10% ~ 90%)
rise
fall
C = 50pF (Bus/MPU Interface)
L
C = 0pF (LCD Panel Interface)
L
6.1 Clock Timing
6.1.1 Input Clocks
Clock Input Waveform
t
t
PWH
PWL
90%
V
IH
V
IL
10%
t
t
r
f
T
OSC
Figure 6-1: Clock Input Requirements
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Symbol
Parameter
Min
Max
Units
f
Input Clock Frequency (CLKI)
Input Clock period (CLKI)
100
MHz
ns
OSC
T
1/f
OSC
OSC
t
Input Clock Pulse Width High (CLKI)
Input Clock Pulse Width Low (CLKI)
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
4.5
4.5
ns
PWH
t
ns
PWL
t
5
5
ns
f
t
ns
r
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
31 for internal clock requirements.
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 30
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Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1
Symbol
Parameter
Min
Max
Units
MHz
ns
f
Input Clock Frequency (CLKI)
Input Clock period (CLKI)
66
OSC
T
t
1/f
OSC
OSC
Input Clock Pulse Width High (CLKI)
Input Clock Pulse Width Low (CLKI)
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
3
3
ns
PWH
t
ns
PWL
t
5
5
ns
f
t
ns
r
Note
Maximum internal requirements for clocks derived from CLKI must be considered
when determining the frequency of CLKI. See Section 6.1.2, “Internal Clocks” on page
31 for internal clock requirements.
Table 6-3: Clock Input Requirements for CLKI2
Symbol
Parameter
Min
Max
Units
MHz
ns
f
Input Clock Frequency (CLKI2)
Input Clock period (CLKI2)
66
OSC
T
1/f
OSC
OSC
t
Input Clock Pulse Width High (CLKI2)
Input Clock Pulse Width Low (CLKI2)
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
3
3
ns
PWH
t
ns
PWL
t
5
5
ns
f
t
ns
r
Note
Maximum internal requirements for clocks derived from CLKI2 must be considered
when determining the frequency of CLKI2. See Section 6.1.2, “Internal Clocks” on page
31 for internal clock requirements.
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
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6.1.2 Internal Clocks
Table 6-4: Internal Clock Requirements
Symbol
Parameter
Min
Max
66
Units
MHz
MHz
MHz
MHz
MHz
f
Bus Clock frequency
BCLK
COREVDD = 2.0V
COREVDD = 2.5V
30
f
Memory Clock frequency (see note 1)
MCLK
50
f
Pixel Clock frequency
PWM Clock frequency
50
PCLK
f
66
PWMCLK
1. MCLK is derived from BCLK, therefore when BCLK is greater than 50MHz, MCLK must be divided using
REG[04h] bits 5-4.
Note
For further information on internal clocks, refer to Section 7, “Clocks” on page 85.
6.2 RESET# Timing
t1
RESET#
Figure 6-2 S1D13A05 RESET# Timing
Table 6-5 S1D13A05 RESET# Timing
Symbol
Parameter
Active Reset Pulse Width
Min
Max
Units
t1
1
—
CLKI
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
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6.3 CPU Interface Timing
6.3.1 Generic #1 Interface Timing
T
CLK
CLK
A[16:1], M/R#
t5
t1
t6
t2
CS#
t15
t7
t8
t3
WE0#, WE1#, RD0#, RD1#
WAIT#
t9
t10
t12
t14
t4
t11
valid
D[15:0] (write)
D[15:0] (read)
t13
valid
Figure 6-3: Generic #1 Interface Timing
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
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Table 6-6: Generic #1 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
50
MHz
ns
CLK
T
1/f
CLK
CLK
A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and
either RD0#, RD1# = 0 or WE0#, WE1# = 0
t1
0
ns
t2
t3
t4
CS# setup to CLK rising edge
0
0
3
ns
ns
ns
RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
RD0#, RD1# or WE0#, WE1# state change to WAIT# driven low
8
A[16:1], M/R# and CS# hold from RD0#, RD1#, WE0#, WE1# rising
edge
t5
0
ns
t6
t7
t8
t9
CS# deasserted to reasserted
0
0
1
5
ns
ns
WAIT# rising edge to RD0#, RD1#, WE0#, WE1# rising edge
WE0#, WE1#, RD0#, RD1# deasserted to reasserted
CLK rising edge to WAIT# rising edge
T
CLK
14
5
ns
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# high
impedance
t10
t11
ns
D[15:0] setup to 4th rising CLK edge after CS#=0 and WE0#,
WE1#=0
1
T
CLK
t12
t13
t14
t15
D[15:0] hold from WE0#, WE1# rising edge (write cycle)
D[15:0] valid to WAIT# rising edge (read cycle)
D[15:0] hold from RD0#, RD1# rising edge (read cycle)
Cycle Length
0
0.5
2
ns
T
CLK
ns
6
T
CLK
Table 6-7: Generic #1 Interface Truth Table for Little Endian
WE0#
WE1#
RD0#
RD1#
D[15:8]
valid
-
D[7:0]
valid
valid
-
Comments
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
16-bit write
1
8-bit write; data on low byte (even byte address )
1
valid
valid
-
8-bit write; data on high byte (odd byte address )
valid
valid
-
16-bit read
1
8-bit read; data on low byte (even byte address )
1
valid
8-bit read; data on high byte (odd byte address )
Table 6-8: Generic #1 Interface Truth Table for Big Endian
WE0#
WE1#
RD0#
RD1#
D[15:8]
valid
-
D[7:0]
valid
valid
-
Comments
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
16-bit write
8-bit write; data on low byte (odd byte address )
1
1
valid
valid
-
8-bit write; data on high byte (even byte address )
16-bit read
valid
valid
-
1
8-bit read; data on low byte (odd byte address )
1
valid
8-bit read; data on high byte (even byte address )
1. Because A0 is not used internally, all addresses are seen by the S1D13A05 as even addresses (16-bit word
address aligned on even byte addresses).
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
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6.3.2 Generic #2 Interface Timing
T
BUSCLK
BUSCLK
A[16:0], M/R#, BHE#
CS#
t5
t1
t6
t2
t15
t7
t8
t3
WE#, RD#
t9
t10
t12
t14
t4
WAIT#
t11
valid
D[15:0] (write)
D[15:0] (read)
t13
valid
Figure 6-4: Generic #2 Interface Timing
S1D13A05
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Table 6-9: Generic #2 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
50
MHz
ns
BUSCLK
T
1/f
BUSCLK
BUSCLK
A[16:0], M/R#, BHE# setup to first BUSCLK rising edge where CS# =
0 and either RD# = 0 or WE# = 0
t1
0
ns
t2
t3
CS# setup to BUSCLK rising edge
0
0
3
0
0
0
1
5
ns
ns
ns
ns
ns
ns
RD#, WE# setup to BUSCLK rising edge
t4
RD# or WE# state change to WAIT# driven low
A[16:0], M/R#, BHE# and CS# hold from RD#, WE# rising edge
CS# deasserted to reasserted
9
t5
t6
t7
WAIT# rising edge to RD#, WE# rising edge
WE#, RD# deasserted to reasserted
t8
T
BUSCLK
t9
WAIT# rising edge after BUSCLK rising edge
Rising edge of either RD# or WE# to WAIT# high impedance
D[15:0] setup to 4th rising BUSCLK edge after CS#=0 and WE#=0
D[15:0] hold from WE# rising edge (write cycle)
D[15:0] valid to WAIT# rising edge setup (read cycle)
D[15:0] hold from RD# rising edge (read cycle)
Cycle Length
14
7
ns
t10
t11
t12
t13
t14
t15
ns
1
0
T
T
T
BUSCLK
ns
0.5
2
BUSCLK
ns
6
BUSCLK
Table 6-10: Generic #2 Interface Truth Table for Little Endian
WE#
RD#
BHE#
A0
0
D[15:8]
valid
-
D[7:0]
valid
valid
-
Comments
0
0
0
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
16-bit write
0
8-bit write at even address
8-bit write at odd address
16-bit read
1
valid
valid
-
0
valid
valid
-
0
8-bit read at even address
8-bit read at odd address
1
valid
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6.3.3 Hitachi SH-3 Interface Timing
T
CKIO
CKIO
A[16:1], M/R#, RD/WR#
BS#
t1
t8
t17
t9
t2
t4
t3
CSn#
t10
t11
t5
WEn#, RD#
WAIT#
t13
t12
t15
t6
t14
t7
D[15:0] (write)
D[15:0] (read)
t16
Figure 6-5: Hitachi SH-3 Interface Timing
Note
A minimum of one software wait state is required.
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Table 6-11: Hitachi SH-3 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
66
MHz
ns
CKIO
T
1/f
CKIO
CKIO
t1
A[16:1], RD/WR# setup to CKIO
BS# setup
0
ns
t2
t3
t4
t5
t6
0
9
0
0
4
ns
BS# hold
ns
CSn# setup
ns
WEn#, RD# setup to next CKIO after BS# low
Falling edge CSn# to WAIT# driven low
ns
9
ns
D[15:0] setup to 3rd CKIO rising edge after BS# deasserted
(write cycle)
t7
1
0
ns
t8
t9
WE#, RD# deasserted to A[16:1], M/R#, RD/WR# deasserted
Rising edge of WAIT# to BS# falling
ns
ns
T
+ 16
CKIO
CKIO rising edge before WAIT# deasserted to WEn#, RD# asserted
for next cycle
t10
2
T
CKIO
t11
t12
t13
t14
t15
t16
t17
Rising edge of WAIT# to WE#, RD# deasserted
WAIT# rising edge after CKIO rising edge
Rising edge of CSn# to WAIT# high impedance
D[15:0] hold from WEn# deasserted (write cycle)
D[15:0] setup to WAIT# rising edge (read cycle)
Rising edge of RD# to D[15:0] high impedance (read cycle)
Cycle Length
0
5
ns
ns
ns
ns
14
6
0
0.5
3
T
T
CKIO
7
ns
5
CKIO
1. The S1D13A05 requires 2ns of write data hold time.
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6.3.4 Hitachi SH-4 Interface Timing
T
CKIO
CKIO
A[16:1], RD/WR#, M/R#
BS#
t1
t8
t18
t9
t2
t4
t3
CSn#
t10
t11
t5
WEn#, RD#
RDY
t14
t13
t12
t6
t7
t15
D[15:0] (write)
D[15:0] (read)
t16
t17
Figure 6-6: Hitachi SH-4 Interface Timing
Note
A minimum of one software wait state is required.
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Table 6-12: Hitachi SH-4 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
66
MHz
ns
CKIO
T
1/f
CKIO
CKIO
t1
A[16:1], M/R#, RD/WR# setup to CKIO
0
ns
t2
t3
t4
t5
t6
BS# setup
0
9
0
0
3
ns
BS# hold
ns
CSn# setup
ns
WEn#, RD# setup to 1st CKIO rising edge after BS# low
Falling edge CSn# to RDY driven high
ns
7
ns
D[15:0] setup to 3rd CKIO rising edge after BS# deasserted
(write cycle)
t7
1
0
ns
t8
t9
WE#,RD# deasserted to A[16:1],M/R#,RD/WR# deasserted
RDY falling edge to BS# falling
ns
ns
T
+ 11
CKIO
CKIO rising edge before RDY deasserted to WEn#, RD# asserted
for next cycle
t10
2
T
CKIO
t11
t12
t13
t14
t15
t16
t17
t18
RDY falling edge to WE#,RD# deasserted
RDY falling edge after CKIO rising edge
Rising edge CSn# to RDY rising edge
CKIO falling edge to RDY tristate
0
5
ns
ns
ns
ns
ns
14
10
12
4
4
D[15:0] hold from WEn# deasserted (write cycle)
D[15:0] valid setup to RDY falling edge (read cycle)
Rising edge of RD# to D[15:0] high impedance (read cycle)
Cycle Length
0
0.5
2
T
T
CKIO
7
ns
4
CKIO
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6.3.5 Motorola MC68K #1 Interface Timing
T
CLK
CLK
A[16:1], R/W#, M/R#
CS#
t3
t3
t1
t13
t1
t1
t1
t4
AS#
t5
UDS#, LDS#, (A0)
DTACK#
t8
t6
t2
t7
t9
t10
D[15:0] (write)
D[15:0] (read)
t11
t12
Figure 6-7: Motorola MC68K #1 Interface Timing
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Table 6-13: Motorola MC68K#1 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
50
MHz
ns
CLK
T
1/f
CLK
CLK
A[16:1], M/R#, R/W# and CS# and AS# and UDS#, LDS# setup to
first CLK rising edge
t1
1
ns
t2
t3
t4
t5
t6
t7
CS# and AS# asserted to DTACK# driven
A[16:1], M/R#, R/W# and CS# hold from AS# rising edge
AS# rising edge to CLK falling edge
2
0
1
0
5
3
7
ns
ns
ns
ns
ns
ns
DTACK# falling edge to UDS#, LDS# rising edge
CLK rising edge to DTACK# falling edge
AS# rising edge to DTACK# rising edge
14
9
1st CLK falling edge after AS# deasserted to DTACK# high
impedance
0.5 T
+
CLK
t8
t9
ns
12
D[15:0] valid to 4th CLK rising edge where CS# = 0, AS# = 0 and
either UDS# = 0 or LDS# = 0 (write cycle)
1
T
CLK
t10
t11
t12
t13
D[15:0] hold from DTACK# falling edge (write cycle)
D[15:0] valid setup time to DTACK# goes low (read cycle)
UDS#, LDS# rising edge to D[15:0] high impedance (read cycle)
Cycle Length
0
0.5
2
ns
T
CLK
ns
7
T
CLK
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6.3.6 Motorola MC68K #2 Interface Timing
T
CLK
CLK
t3
t4
t1
A[16:1], M/R#, R/W#, SIZ[1:0]
t15
t1
CS#
AS#
t5
t6
t1
t1
t7
DS#
t10
t9
t8
t2
DSACK1#
D[31:16] (write)
D[31:16] (read)
t11
t12
t13
t14
Figure 6-8: Motorola MC68K #2 Interface Timing
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Table 6-14: Motorola MC68K#2 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
50
MHz
ns
CLK
T
1/f
CLK
CLK
A[16:0], M/R#, R/W#, SIZ[1:0] and CS# and AS# and DS# setup to
first CLK rising edge
t1
0
ns
t2
t3
t4
t5
t6
t7
t8
t9
CS# and AS# asserted low to DSACK1# driven
A[16:1], M/R#, R/W#, SIZ[1:0] hold from AS# rising edge
CS# hold from AS# rising edge
2
0
0
0
1
0
5
3
7
ns
ns
ns
ns
ns
ns
ns
ns
DS# rising edge to AS# rising edge
AS# setup to CLK falling edge
DSACK1# falling edge to DS# rising edge
CLK rising edge to DSACK1# falling edge
AS# rising edge to DSACK1# rising edge
14
9
1st CLK falling edge after AS# deasserted to DSACK1# high
impedance
t10
t11
T
+ 3
ns
CLK
D[15:0] setup to 4th CLK rising edge after CS#=0, AS#=0, DS#=0,
and DSACK1#=0
1
T
CLK
t12
t13
t14
t15
D[15:0] hold from DSACK1# falling edge
D[15:0] valid setup to DSACK1# falling edge (read cycle)
DS# rising edge to D[15:0] high impedance (read cycle)
Cycle Length
0
0.5
2
ns
T
CLK
9
ns
7
T
CLK
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6.3.7 Motorola REDCAP2 Interface Timing
T
CKO
CKO
A[16:1], R/W#, CS#
EBO#, EB1# (write)
D[15:0] (write)
t8
t1
t12
t9
t2
t4
t3
valid
t10
t5
t7
EB0#, EB1#, OE# (read)
D[15:0] (read)
t6
t11
valid
Figure 6-9: Motorola Redcap2 Interface Timing
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Table 6-15: Motorola Redcap2 Interface Timing
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
17
MHz
ns
CKO
T
1/f
CKO
CKO
t1
A[16:1], R/W, CSn# setup to CKO rising edge
EB0,EB1 setup to CKO rising edge (write)
0
ns
t2
0
ns
D[15:0] input setup to 4th CKO rising edge after CSn# and EB0 or
EB1 asserted low (write cycle)
t3
1
T
CKO
D[15:0] input hold from 4th CKO rising edge after CSn# and EB0 or
EB1 asserted low (write cycle)
t4
t5
7
0
ns
ns
ns
EB0,EB1,OE setup to CKO rising edge (read cycle)
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
D[15:0] valid for MCLK = BCLK (read cycle)
t6a
t6b
t6c
t6d
6T
9T
+17
CKO
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
+17
ns
ns
ns
CKO
D[15:0] valid for MCLK = BCLK
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
D[15:0] valid for MCLK = BCLK 3 (read cycle)
1st CKO rising edge after CSn#, EB0 or EB1,OE asserted low to
D[15:0] valid for MCLK = BCLK 4 (read cycle)
÷
2 (read cycle)
12T
15T
+17
+17
CKO
÷
CKO
÷
t7
t8
EB0,EB1,OE falling edge to D[15:0] driven (read cycle)
A[16:1], R/W, CSn hold from CKO rising edge
EB0, EB1 setup to CKO rising edge (write cycle)
CKO falling edge to EB0, EB1, OE deasserted (read)
OE, EB0, EB1 deasserted to D[15:0] output high impedance (read)
Cycle Length (note 1)
2
0
1
0
2
9
ns
ns
ns
ns
ns
t9
t10
t11
t12
8
T
CKO
1. The cycle length for the REDCAP interface is fixed at 10 TCKO
.
2. The Read and Write 2D BitBLT functions are not available when using the REDCAP interface.
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6.3.8 Motorola Dragonball Interface Timing with DTACK
T
CLKO
CLKO
A[16:1]
t1
t3
t13
t1
t1
t1
t4
CSX#
t5
t4
UWE#, LWE# (write)
OE# (read)
t6
t7
D[15:0] (write)
D[15:0] (read)
DTACK#
Valid
t8
t9
Valid
t12
t2
t10
t11
Figure 6-10: Motorola Dragonball Interface Timing with DTACK
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Table 6-16: Motorola Dragonball Interface Timing with DTACK
Symbol
Parameter
Min
Max
Unit
f
66 (note 1)
MHz
ns
Clock frequency
Clock period
CLKO
T
1/f
CLKO
CLKO
t1
t2
t3
t4
t5
1
ns
A[16:1], CSX, UWE, LWE, OE setup to CLKO rising edge
CSX asserted low to DTACK driven
2
0
0
1
7
ns
ns
A[16:1] hold from CSX rising edge
ns
DTACK falling edge to UWE, LWE and CSX rising edge
UWE, LWE deasserted to reasserted
T
CLKO
D[15:0] valid to fourth CLKO rising edge where CSX = 0 and UWE
= 0 or LWE = 0 (write cycle)
t6
1
T
CLKO
t7
t8
0
0.5
2
ns
D[15:0] hold from DTACK falling edge (write cycle)
D[15:0] valid setup to DTACK falling edge (read cycle)
T
CLKO
ns
t9
6
14
9
CSX rising edge to D[15:0] high impedance (read cycle)
CLKO rising edge to DTACK# falling edge
t10
t11
5
ns
3
ns
CSX rising edge to DTACK rising edge
First CLKO falling edge after deassertion of CSX# to DTACK#
high impedance
t12
t13
0.5T
+ 4 0.5T
+ 8
CLKO
ns
CLKO
Cycle Length
8
T
CLKO
1. The MC68SZ328 with a maximum clock frequency of 66MHz is supported.
The MC68VZ328 with a maximum clock frequency of 33MHz is supported.
The MC68EZ328 with a maximum clock frequency of 16MHz is supported.
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6.3.9 Motorola Dragonball Interface Timing w/o DTACK
T
CLKO
CLKO
A[16:1]
t1
t1
t5
t7
CSX#
t1
t1
t5
t5
UWE#, LWE# (write)
OE#
t2
t5
D[15:0] (write)
D[15:0] (read)
t4
t6
t3
Figure 6-11: Motorola Dragonball Interface Timing w/o DTACK
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Table 6-17: Motorola Dragonball Interface Timing w/o DTACK
Symbol
Parameter
Min
Max
Unit
f
Bus clock frequency
Bus clock period
33 (note 1)
MHz
ns
CLKO
T
1/f
CLKO
CLKO
A[16:1] and CSX# and UWE#, LWE# and OE# setup to CLKO
rising edge
t1
1
ns
D[15:0] valid to 4th CLK rising edge where CSX# = 0 and UWE# =
0 or LWE# = 0 (write cycle)
t2
t3
1
2
T
CLKO
CSX# and OE# asserted low to D[15:0] driven (read cycle)
8
7
ns
1st CLKO rising edge after CSX# and OE# asserted to D[15:0]
valid for MCLK=BCLK (read cycle)
t4a
T
T
T
CLKO
CLKO
1st CLKO rising edge after CSX# and OE# asserted to D[15:0]
valid for MCLK=BCLK ÷ 2 (read cycle)
t4b
t4c
t5
10
13
1st CLKO rising edge after CSX# and OE# asserted to D[15:0]
valid for MCLK=BCLK ÷ 3 (read cycle) (see note 2)
CLKO
A[16:1] and UWE#, LWE# and OE# and D[15:0] (write) hold from
CSX# rising edge
0
2
ns
t6
t7
CSX# rising edge to D[15:0] high impedance
Cycle Length (see note 3)
8
ns
T
CLKO
1. The MC68VZ328 with a maximum clock frequency of 33MHz is supported.
The MC68EZ328 with a maximum clock frequency of 16MHz is supported.
2. The MC68EZ328 does not support the MCLK = BCLK
The MC68VZ328 does not support the MCLK = BCLK
÷
÷
3 and MCLK = BCLK
4 option.
÷ 4 options.
3. The cycle length for the Dragonball w/o DTACK interface is fixed at 10 TCLKO
.
4. The Read and Write 2D BitBLT functions are not available when using the Dragonball w/o DTACK interface.
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6.4 LCD Power Sequencing
6.4.1 Passive/TFT Power-On Sequence
GPIO0*
t1
Power Save Mode Enable**
(REG[14h] bit 4)
t2
LCD Signals***
*It is recommended to use the general purpose IO pin GPIO0 to control the LCD bias power.
**The LCD power-on sequence is activated by programming the Power Save Mode Enable bit (REG[14h] bit 4) to 0.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-12: Passive/TFT Power-On Sequence Timing
Table 6-18: Passive/TFT Power-On Sequence Timing
Symbol
Parameter
LCD signals active to LCD bias active
Min
Note 1
0
Max
Note 1
1
Units
t1
t2
BCLK
Power Save Mode disabled to LCD signals active
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
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6.4.2 Passive/TFT Power-Off Sequence
t1
GPIO0*
Power Save Mode Enable**
(REG[14h] bit 4)
t2
LCD Signals***
*It is recommended to use the general purpose IO pin GPIO0 to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[14h] bit 4) to 1.
***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-13: Passive/TFT Power-Off Sequence Timing
Table 6-19: Passive/TFT Power-Off Sequence Timing
Symbol
Parameter
Min
Note 1
0
Max
Note 1
1
Units
t1
t2
LCD bias deactivated to LCD signals inactive
Power Save Mode enabled to LCD signals low
BCLK
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.
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6.5 Display Interface
The timing parameters required to drive a flat panel display are shown below. Timing
details for each supported panel type are provided in the remainder of this section.
HT
HDPS
HPS
HPW
VPS
VDPS
VPW
HDP
VDP
VT
Figure 6-14: Panel Timing Parameters
Table 6-20: Panel Timing Parameter Definition and Register Summary
Symbol
Description
Derived From
((REG[20h] bits 6-0) + 1) x 8
Units
HT
Horizontal Total
1
1
HDP
Horizontal Display Period
((REG[24h] bits 6-0) + 1) x 8
For STN panels: ((REG[28h] bits 9-0) + 22)
For TFT panels: ((REG[28h] bits 9-0) + 5)
(REG[2Ch] bits 9-0) + 1
HDPS
Horizontal Display Period Start Position
Ts
HPS
HPW
VT
FPLINE Pulse Start Position
FPLINE Pulse Width
(REG[2Ch] bits 22-16) + 1
(REG[30h] bits 9-0) + 1
Vertical Total
VDP
VDPS
VPS
VPW
Vertical Display Period
(REG[34h] bits 9-0) + 1
Vertical Display Period Start Position
FPFRAME Pulse Start Position
FPFRAME Pulse Width
REG[38h] bits 9-0
Lines (HT)
REG[3Ch] bits 9-0
(REG[3Ch] bits 18-16) + 1
1. For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
2. The following formulas must be valid for all panel timings:
HDPS + HDP < HT
VDPS + VDP < VT
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6.5.1 Generic STN Panel Timing
VT (= 1 Frame)
VPW
FPFRAME
VDP
FPLINE
1
MOD (DRDY)
FPDAT[17:0]
HT (= 1 Line)
HPS
HPW
FPLINE
FPSHIFT
1 PCLK
2
MOD (DRDY)
HDPS
HDP
FPDAT[17:0]
Figure 6-15: Generic STN Panel Timing
VT
= Vertical Total
= [(REG[30h] bits 9-0) + 1] lines
VPS
VPW
VDPS
VDP
HT
HPS
HPW
HDPS
HDP
= FPFRAME Pulse Start Position
= FPFRAME Pulse Width
= Vertical Display Period Start Position = 0 lines, because REG[38h] bits 9-0 = 0
= Vertical Display Period
= Horizontal Total
= FPLINE Pulse Start Position
= FPLINE Pulse Width
= 0 lines, because REG[3Ch] bits 9-0 = 0
= [(REG[3Ch] bits 18-16) + 1] lines
= [(REG[34h] bits 9-0) + 1] lines
= [((REG[20h] bits 6-0) + 1) x 8] pixels
= [(REG[2Ch] bits 9-0) + 1] pixels
= [(REG[2Ch] bits 22-16) + 1] pixels
= Horizontal Display Period Start Position= 22 pixels, because REG[28h] bits 9-0 = 0
= Horizontal Display Period = [((REG[24h] bits 6-0) + 1) x 8] pixels
*For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
*HPS should comply with the following formula:
HPS > HDP + 22
HPS + HPW < HT
*Panel Type Bits (REG[0Ch] bits 1-0) = 00b (STN)
*FPFRAME Pulse Polarity Bit (REG[3Ch] bit 23) = 1 (active high)
*FPLINE Polarity Bit (REG[2Ch] bit 23) = 1 (active high)
*MOD1 is the MOD signal when REG[0Ch] bits 21-16 = 0 (MOD toggles every FPFRAME)
*MOD2 is the MOD signal when REG[0Ch] bits 21-16 = n (MOD toggles every n FPLINE)
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 54
Epson Research and Development
Vancouver Design Center
6.5.2 Single Monochrome 4-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
Invalid
FPDAT[7:4]
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
Invalid
1-317
1-318
1-319
1-320
1-1
1-2
1-3
1-4
1-5
Invalid
Invalid
Invalid
Invalid
Invalid
1-6
FPDAT6
FPDAT5
1-7
1-8
Invalid
Invalid
FPDAT4
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
Figure 6-16: Single Monochrome 4-Bit Panel Timing
= Vertical Display Period
VDP
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
VNDP
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
HDP
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
HNDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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Hardware Functional Specification
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t9
t14
t11 t10
t7
FPSHIFT
t12 t13
1
2
FPDAT[7:4]
Figure 6-17: Single Monochrome 4-Bit Panel A.C. Timing
Table 6-21: Single Monochrome 4-Bit Panel A.C. Timing
Symbol
t1
Parameter
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 2
4
Typ
Max
Units
Ts (note 1)
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
2
2
1
2
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
note 8
1. Ts
= pixel clock period
2. t1min = HPS + t4min
3. t2min = t3min - (HPS + t4min
4. t3min = HT
)
5. t4min = HPW
6. t5min = HPS - 1
7. t6min = HPS - (HDP + HDPS) + 2, if negative add t3min
8. t14min = HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
Page 56
Epson Research and Development
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6.5.3 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
Invalid
Invalid
FPDAT[7:0]
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
Invalid
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
1-1
1-2
1-3
1-4
1-5
1-9
Invalid
Invalid
Invalid
Invalid
Invalid
1-10
1-11
1-12
1-13
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1-6
1-7
1-8
1-14
1-15
1-16
Invalid
Invalid
Invalid
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 6-18: Single Monochrome 8-Bit Panel Timing
VDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
VNDP
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
HDP
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
HNDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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Hardware Functional Specification
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t9
t14
t11 t10
t7
FPSHIFT
t12
t13
1
2
FPDAT[7:0]
Figure 6-19: Single Monochrome 8-Bit Panel A.C. Timing
Table 6-22: Single Monochrome 8-Bit Panel A.C. Timing
Symbol
t1
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 4
8
Typ
Max
Units
Ts (note 1)
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
4
4
4
4
note 8
1. Ts
= pixel clock period
2. t1min = HPS + t4min
3. t2min = t3min - (HPS + t4min
4. t3min = HT
)
5. t4min = HPW
6. t5min = HPS - 1
7. t6min = HPS - (HDP + HDPS) + 4, if negative add t3min
8. t14min = HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
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6.5.4 Single Color 4-Bit Panel Timing
VNDP
VDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
Invalid
Invalid
FPDAT[7:4]
FPLINE
DRDY (MOD)
HDP
HNDP
.5Ts .5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts .5Ts
.5Ts
.5Ts
FPSHIFT
.5Ts
.5Ts
.5Ts
.5Ts
.5Ts
2.5Ts
Invalid
Invalid
1-R1 1-G2 1-B3
Invalid
Invalid
1-B319
FPDAT7
FPDAT6
FPDAT5
FPDAT4
1-R320
1-G320
1-B320
1-G1 1-B2
1-R4
1-G4
Invalid
Invalid
1-B1
1-R2
1-R3
Invalid
Invalid
1-G3 1-B4
Notes:
- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-20: Single Color 4-Bit Panel Timing
= Vertical Display Period
VDP
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
VNDP
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
HDP
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
HNDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
S1D13A05
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Hardware Functional Specification
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t9
t14
t7
t11 t10
FPSHIFT
t12 t13
1
2
FPDAT[7:4]
Figure 6-21: Single Color 4-Bit Panel A.C. Timing
Table 6-23: Single Color 4-Bit Panel A.C. Timing
Symbol
t1
Parameter
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 0.5
1
Typ
Max
Units
Ts (note 1)
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
0.5
0.5
0.5
0.5
FPDAT[7:4] setup to FPSHIFT falling edge
FPDAT[7:4] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
note 8
1. Ts
= pixel clock period
2. t1min = HPS + t4min
3. t2min = t3min - (HPS + t4min
4. t3min = HT
)
5. t4min = HPW
6. t5min = HPS - 1
7. t6min = HPS - (HDP + HDPS) + 1.5), if negative add t3min
8. t14min = HDPS - (HPS + t4min) + 1, if negative add t3min
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
X40A-A-001-07
Revision 7.7
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6.5.5 Single Color 8-Bit Panel Timing (Format 1)
VNDP
VDP
FPFRAME
FPLINE
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
Invalid
LINE1
LINE2
FPDAT[7:0]
Invalid
FPLINE
HDP
2Ts
HNDP
2Ts 2Ts
2Ts
4Ts
4Ts
2Ts
2Ts 2Ts
2Ts
2Ts
2Ts
FPSHIFT
2Ts
2Ts
4Ts
4Ts
2Ts
2Ts
2Ts
2Ts
4Ts
4Ts
2Ts
2Ts
4Ts
4Ts
2Ts
2Ts
1-
R316
2Ts
2Ts
FPSHIFT2
2Ts
2Ts
2Ts
2Ts
2Ts
1-
R316
1-R1 1-G1
1-B1 1-R2
1-G2 1-B2
1-G6
1-B6
1-B11 1-R12
Invalid
FPDAT7
FPDAT6
Invalid
1-
B316
1-R7
1-B7
1-G7 1-G12 1-B12
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1-
G317
1-R8
1-B8
1-R13 1-G13
1-B13 1-R14
FPDAT5
FPDAT4
FPDAT3
1-
R318
1-R3 1-G3
1-B3 1-R4
1-G8
1-R9
Invalid
Invalid
Invalid
Invalid
Invalid
1-
B318
1-G9 1-G14 1-B14
1-R10 1-R15 1-G15
1-B10 1-B15 1-R16
1-G11 1-G16 1-B16
1-
G319
1-G4 1-B4
1-R5 1-G5
1-B5 1-R6
1-B9
1-G10
1-R11
FPDAT2
1-
R320
FPDAT1
FPDAT0
1-
B320
Notes:
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIFT/FPSHIFT2 rising edges
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-22: Single Color 8-Bit Panel Timing (Format 1)
= Vertical Display Period
VDP
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
VNDP
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
HDP
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
HNDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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Hardware Functional Specification
Issue Date: 2012/02/27
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
FPLINE
Data Timing
t6a
t6b
t8
t9
t14
t7a
t11 t10
FPSHIFT
t7b
FPSHIFT2
t12 t13 t12
t13
2
1
FPDAT[7:0]
Figure 6-23: Single Color 8-Bit Panel A.C. Timing (Format 1)
Table 6-24: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6a + t4
t6b + t4
t14 + 2
4
Typ
Max
Units
Ts (note 1)
t1
t2
t3
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
t4
FPLINE pulse width
t6a
t6b
t7a
t7b
t8
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT2 falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPSHIFT2 falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT rising, FPSHIFT2 falling edge
FPSHIFT2, FPSHIFT period
t9
6
t10
t11
t12
t13
t14
FPSHIFT2, FPSHIFT pulse width low
2
2
1
1
FPSHIFT2, FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT2, FPSHIFT falling edge
FPDAT[7:0] hold from FPSHIFT2, FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
note 8
1. Ts
= pixel clock period
2. t1min = HPS + t4min
3. t2min = t3min - (HPS + t4min
4. t3min = HT
)
5. t4min = HPW
6. t6amin = HPS - (HDP + HDPS), if negative add t3min
7. t6bmin = HPS - (HDP + HDPS) + 2, if negative add t3min
8. t14min = HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2012/02/27
S1D13A05
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Revision 7.7
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6.5.6 Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
Invalid
FPLINE
DRDY (MOD)
HDP
HNDP
2Ts
Ts
2Ts
2Ts
Ts
Ts
2Ts
2Ts
Ts
2Ts
FPSHIFT
Ts
1-R1
Ts
Ts
Ts
Ts
Ts
Invalid
Invalid
Invalid
Invalid
Invalid
1-B3
1-G6
1-G318
Invalid
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
1-B318
1-R319
1-G1
1-B1
1-R2
1-G2
1-B2
1-R4
1-G4
1-B4
1-R5
1-G5
1-B6
1-R7
1-G7
1-B7
1-R8
1-G8
1-B8
Invalid
Invalid
1-G319
1-B319
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1-R320
1-G320
1-B320
FPDAT2
FPDAT1
FPDAT0
1-R3 1-B5
1-G3 1-R6
Invalid
Notes:
- The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Figure 6-24: Single Color 8-Bit Panel Timing (Format 2)
= Vertical Display Period
VDP
= (REG[34h] bits 9:0) + 1 Lines
= Vertical Non-Display Period
VNDP
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
HDP
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
HNDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
S1D13A05
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Hardware Functional Specification
Issue Date: 2012/02/27
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t1
t2
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t9
t7
t14
t11 t10
FPSHIFT
t12 t13
1
2
FPDAT[7:0]
Figure 6-25: Single Color 8-Bit Panel A.C. Timing (Format 2)
Table 6-25: Single Color 8-Bit Panel A.C. Timing (Format 2)
Symbol
t1
Parameter
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 2
2
Typ
Max
Units
Ts (note 1)
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
FPDAT[7:0] setup to FPSHIFT falling edge
FPDAT[7:0] hold to FPSHIFT falling edge
FPLINE falling edge to FPSHIFT rising edge
1
1
1
1
note 8
1. Ts
= pixel clock period
2. t1min = HPS + t4min
3. t2min = t3min - (HPS + t4min
4. t3min = HT
)
5. t4min = HPW
6. t5min = HPS - 1
7. t6min = HPS - (HDP + HDPS) + 1, if negative add t3min
8. t14min = HDPS - (HPS + t4min), if negative add t3min
Hardware Functional Specification
Issue Date: 2012/02/27
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Revision 7.7
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6.5.7 Single Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[15:0]
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
Invalid
Invalid
LINE1
LINE2
FPLINE
DRDY (MOD)
HDP
3Ts
HNDP
3Ts
3Ts
2Ts
2Ts
3Ts
3Ts
3Ts
2Ts
3Ts
3Ts
2Ts
3Ts
FPSHIFT
3Ts
3Ts
3Ts
3Ts
2Ts
3Ts
2Ts
Invalid
1-G6
1-R7
1-B7
1-G635
1-B11
1 R1
-
Invalid
Invalid
Invalid
FPDAT15
FPDAT14
FPDAT13
FPDAT12
FPDAT7
FPDAT6
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1-G12
1-G636
1-B1
1-R13
1-R637
1-B637
1-G638
1-R639
1-G2
1-R3
1-B3
1-G4
1-G8 1-B13
1-R9 1-G14
Invalid
Invalid
Invalid
1-B9
1-R15
1-G10 1-B15
1-R5
1-B5
1-G1
1-B639
1-G640
Invalid
Invalid
Invalid
Invalid
FPDAT5
FPDAT4
1-G16
1-R11
1-B6
1-G7
1-R8
1-B8
1-R12
1-B12
1-R636
1-B636
1-G637
1-R638
1-B638
1-G639
1-R640
1-B640
FPDAT11
FPDAT10
FPDAT9
FPDAT8
FPDAT3
FPDAT2
1-R2
1-B2
1-G3
1-G13
1-R14
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1-R4
1-B4
1-G5
1-R6
1-G9
1-B14
Invalid
Invalid
Invalid
Invalid
1-R10 1-G15
1-B10
1-R16
FPDAT1
1-G11 1-B16
FPDAT0
Notes:
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 3 FPSHIFT rising clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 640x480 panel
Figure 6-26: Single Color 16-Bit Panel Timing
VDP
= Vertical Display Period
= (REG[34h] bits 9:0) + 1 Lines
VNDP
= Vertical Non-Display Period
= VT - VDP
= (REG[30h] bits 9:0) - (REG[34h] bits 9:0) Lines
= Horizontal Display Period
HDP
= ((REG[24h] bits 6:0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
HNDP
= (((REG[20h] bits 6:0) + 1) x 8Ts) - (((REG[24h] bits 6:0) + 1) x 8Ts)
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t2
t1
Sync Timing
FPFRAME
t4
t3
FPLINE
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t8
t9
t7
t14
t11 t10
FPSHIFT
t12 t13
1
2
FPDAT[15:0]
Figure 6-27: Single Color 16-Bit Panel A.C. Timing
Table 6-26: Single Color 16-Bit Panel A.C. Timing
Symbol
Parameter
Min
note 2
note 3
note 4
note 5
note 6
note 7
t6 + t4
t14 + 3
5
Typ
Max
Units
Ts (note 1)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
FPFRAME setup to FPLINE falling edge
FPFRAME hold from FPLINE falling edge
FPLINE period
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE pulse width
MOD transition to FPLINE rising edge
FPSHIFT falling edge to FPLINE rising edge
FPSHIFT falling edge to FPLINE falling edge
FPLINE falling edge to FPSHIFT falling edge
FPSHIFT period
FPSHIFT pulse width low
FPSHIFT pulse width high
2
2
2
2
FPDAT[15:0] setup to FPSHIFT rising edge
FPDAT[15:0] hold to FPSHIFT rising edge
FPLINE falling edge to FPSHIFT rising edge
note 8
1. Ts
= pixel clock period
2. t1min = HPS + t4min
3. t2min = t3min - (HPS + t4min
4. t3min = HT
)
5. t4min = HPW
6. t5min = HPS - 1
7. t6min = HPS - (HDP + HDPS) + 2, if negative add t3min
8. t14min = HDPS - (HPS + t4min), if negative add t3min
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6.5.8 Generic TFT Panel Timing
VT (= 1 Frame)
VPS
VPW
FPFRAME
VDP
VDPS
FPLINE
DRDY
FPDAT[17:0]
HT (= 1 Line)
HPS
HPW
FPLINE
FPSHIFT
DRDY
FPDAT[17:0]
HDPS
invalid
HDP
invalid
Figure 6-28: Generic TFT Panel Timing
VT
= Vertical Total
= FPFRAME Pulse Start Position
= FPFRAME Pulse Width
= Vertical Display Period Start Position= (REG[38h] bits 9-0) lines
= Vertical Display Period
= Horizontal Total
= FPLINE Pulse Start Position
= FPLINE Pulse Width
= Horizontal Display Period Start Position= [(REG[28h] bits 9-0) + 5] pixels
= Horizontal Display Period = [((REG[24h] bits 6-0) + 1) x 8] pixels
= [(REG[30h] bits 9-0) + 1] lines
= (REG[3Ch] bits 9-0) lines
= [(REG[3Ch] bits 18-16) + 1] lines
VPS
VPW
VDPS
VDP
HT
HPS
HPW
HDPS
HDP
= [(REG[34h] bits 9-0) + 1] lines
= [((REG[20h] bits 6-0) + 1) x 8] pixels
= [(REG[2Ch] bits 9-0) + 1] pixels
= [(REG[2Ch] bits 22-16) + 1] pixels
*For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
*Panel Type Bits (REG[0Ch] bits 1-0) = 01 (TFT)
*FPLINE Pulse Polarity Bit (REG[2Ch] bit 23) = 0 (active low)
*FPFRAME Polarity Bit (REG[3Ch] bit 23) = 0 (active low)
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6.5.9 9/12/18-Bit TFT Panel Timing
VNDP2
VDP
VNDP1
FPFRAME
FPLINE
LINE240
LINE1
LINE480
FPDAT[17:0]
DRDY
FPLINE
HDP
HNDP1
HNDP2
FPSHIFT
DRDY
1-1
1-2
1-320
invalid
invalid
FPDAT[17:0]
Note: DRDY is used to indicate the first pixel
Example Timing for 18-bit 320x240 panel
Figure 6-29: 18-Bit TFT Panel Timing
VDP
= Vertical Display Period
= VDP Lines
VNDP
= Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
VNDP1 = Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
VNDP2 = Vertical Non-Display Period 2
= VDPS - VPS Lines
if negative add VT
HDP
= Horizontal Display Period
= HDP Ts
HNDP
= Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
HNDP1 = Horizontal Non-Display Period 1
= HDPS - HPS Ts
HNDP2 = Horizontal Non-Display Period 2
= HPS - (HDP + HDPS) Ts
if negative add HT
if negative add HT
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t1
t2
FPFRAME
t3
FPLINE
t4
FPLINE
DRDY
t5
t8
t7
t6
t9
t12
t13
t14
t11
t10
FPSHIFT
t15 t16
1
invalid
2
319
320
invalid
FPDAT[17:0]
Note: DRDY is used to indicate the first pixel
Figure 6-30: TFT A.C. Timing
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Table 6-27: TFT A.C. Timing
Symbol
Parameter
Min
VT
VPW
HPS
HT
HPW
note 2
HDP
note 3
1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Typ
Max
Units
Lines
Lines
FPFRAME cycle time
FPFRAME pulse width low
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
FPFRAME falling edge to FPLINE falling edge phase difference
FPLINE cycle time
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE pulse width low
FPLINE Falling edge to DRDY active
DRDY pulse width
DRDY falling edge to FPLINE falling edge
FPSHIFT period
250
FPSHIFT pulse width high
FPSHIFT pulse width low
FPLINE setup to FPSHIFT falling edge
DRDY to FPSHIFT falling edge setup time
DRDY hold from FPSHIFT falling edge
Data setup to FPSHIFT falling edge
Data hold from FPSHIFT falling edge
1. Ts
= pixel clock period
2. t6min = HDPS - HPS
3. t8min = HPS - (HDP + HDPS)
if negative add HT
if negative add HT
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6.5.10 Sharp HR-TFT Panel Timing
t1
t2
FPSHIFT
(DCLK)
Ts
t3
FPDAT[17:0]
(OB[5:0],
OG[5:0],
1
2
3
last
OR[5:0])
t4
GPIO3
(SPL)
t5
t6
FPLINE
(LP)
t7
GPIO1
(CLS)
t8
PS1
t10
t9
t9
t9
t9
t9
GPIO0
(PS)
PS2
PS3
t11
t12
t12
GPIO2
(REV)
Figure 6-31: Sharp HR-TFT Panel Horizontal Timing
Table 6-28: Sharp HR-TFT Panel Horizontal Timing
Symbol
Parameter
Min
8
9
Typ
note 2
note 3
note 4
1
note 5
note 6
note 7
note 8
note 9
note 10
note 11
note 12
Max
1024
1025
1024
Units
Ts (note 1)
Horizontal total period
FPSHIFT (DCLK) active
Horizontal display period
GPIO3 (SPL) pulse width
FPLINE (LP) pulse width
t1
t2
t3
t4
t5
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
8
1
2
0
0
0
0
0
0
256
-
511
63
127
255
127
31
t6
FPLINE (LP) falling edge to GPIO3 (SPL) rising edge
GPIO1 (CLS) pulse width
GPIO1 (CLS) falling edge to GPIO0 (PS1) rising edge
GPIO0 (PS2) toggle width
GPIO0 (PS2) first falling edge to GPIO0 (PS2) first rising edge
GPIO0 (PS3) pulse width
GPIO2 (REV) toggle position to FPLINE (LP) rising edge
t7
t8
t9
t10
t11
t12
1. Ts
= pixel clock period
2. t1typ
3. t2typ
4. t3typ
= [(REG[20h] bits 6-0) + 1] * 8
= [((REG[24h] bits 6-0) + 1) * 8] + 1
= [(REG[24h] bits 6-0) + 1] * 8
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5. t5typ
6. t6typ
7. t7typ
8. t8typ
9. t9typ
= (REG[2Ch] bits 22-16) + 1
= (REG[28h] bits 9-0) - (REG[2Ch] bits 22-16) + 2
= (REG[A0h] bits 8-0)
= (REG[A4h] bits 5-0)
= (REG[ACh] bits 6-0)
10. t10typ = (REG[A8h] bits 7-0)
11. t11typ = (REG[B0h] bits 6-0)
12. t12typ = (REG[B4h] bits 4-0)
t1
t2
FPFRAME
(SPS)
t3
t4
t3
t4
t5
t3
FPLINE
(LP)
t6
Vertical Display Period
t7
FPDAT[17:0]
(OB[5:0],
Line 1
Last
OG[5:0],
OR[5:0])
Driving period for PS3
Driving period for PS3
Driving period for PS1 or PS2
Figure 6-32: Sharp HR-TFT Panel Vertical Timing
Table 6-29: Sharp HR-TFT Panel Vertical Timing
Symbol
Parameter
FPFRAME (SPS) pulse width
Min
1
Typ
Max
8
Units
Lines
(note 1)
Lines
note 3
t1
t2
Vertical total period
1
note 4
1
1024
FPFRAME (SPS) rising/falling edge to FPLINE (LP) rising edge
Ts (note 2)
t3
t4
(note 5)
note 5
note 6
note 7
note 8
FPLINE (LP) rising edge to FPFRAME (SPS) rising/falling edge
Vertical display start position
Vertical display period
0
0
1
0
1023
1023
1024
7
Ts
Lines
Lines
Lines
t5
t6
t7
Extra driving period for GPIO0 (PS1/2)
1. Lines
= 1 Horizontal Line
2. Ts
= pixel clock period
3. t1typ
4. t2typ
5. t3typ
= (REG[3Ch] bits 18-16) + 1
= (REG[30h] bits 9-0) + 1
The FPFRAME (SPS) rising/falling edge can occur before or after FPLINE (LP) rising edge depending
on the value stored in the FPLINE Pulse Start Position bits (REG[2Ch] bits 9-0). To obtain the case
indicated by t3, set the FPLINE Pulse Start Position bits to 0 and the FPFRAME (SPS) rising/falling
edge will occur 1 Ts before the FPLINE (LP) rising edge. To obtain the case indicated by t4, set the
FPLINE Pulse Start Position bits to a value between 1 and the Horizontal Total - 1. Then t4 = (Horizontal
Total Period - 1) - (REG[2Ch] bits 9-0)
6. t5typ
7. t6typ
8. t7typ
= (REG[38h] bits 9-0)
= (REG[34h] bits 9-0) + 1
= (REG[B8h] bits 2-0)
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6.5.11 Casio TFT Panel Timing
Vertical Timing
FPFRAME
(GSRT)
t1
FPLINE
(GPCK)
t2
Horizontal Timing
t3
FPLINE
(GPCK)
t4
t6
FPSHIFT
(CLK)
t5
FPDAT[17:0]
t7
t8
GPIO3
(STH)
GPIO0
(POL)
t10
t9
GPIO1
(GRES)
t11
GPIO2
(FRP)
Figure 6-33: Casio TFT Horizontal Timing
Table 6-30: Casio TFT Horizontal Timing
Symbol
Parameter
Horizontal pulse start position
Min
Typ
note 2
note 3
note 4
note 5
note 6
note 7
note 8
1
Max
1024
1024
128
Units
Ts (note 1)
1
8
1
t1
t2
t3
t4
t5
Horizontal total
Horizontal pulse width
Pixel clock period
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Horizontal display period start position
Horizontal display period
FPLINE (GPCK) rising edge to GPIO3 (STH) rising edge
GPIO3 (STH) pulse width
FPLINE (GPCK) rising edge to GPIO1 (GRES) falling edge
GPIO1 (GRES) falling edge to FPLINE (GPCK) rising edge
FPLINE (GPCK) rising edge to GPIO2 (FRP) toggle point
4
8
0
1027
1024
63
t6
t7
t8
t9
t10
t11
0
1
0
note 9
note 10
note 11
63
64
127
1. Ts
= pixel clock period
2. t1typ = [(REG[2Ch] bits 9-0) + 1)
3. t2typ = [(REG[20h] bits 6-0) + 1) * 8
4. t3typ = [(REG[2Ch] bits 22-16) + 1
5. t4typ = depends on the pixel clock (PCLK)
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6. t5typ = (REG[28h] bits 9-0) + 4
7. t6typ = [(REG[24h] bits 6-0) + 1] * 8
8. t7typ = (REG[C0h] bits 29-24)
9. t9typ = (REG[C0h] bits 5-0)
10. t10typ = (REG[C0h] bits 13-8) + 1
11. t11typ = (REG[C0h] bits 22-16)
t3
FPFRAME
(GSRT)
t2
t1
FPLINE
(GPCK)
GPIO1
(GRES)
GPIO2
(FRP)
GPIO0
(POL)
t4
t5
FPDAT[17:0]
Figure 6-34: Casio TFT Vertical Timing
Table 6-31: Casio TFT Vertical Timing
Symbol
Parameter
Min
Typ
Max
1024
1023
8
1024
1024
Units
lines (note 1)
lines
Vertical total
Vertical pulse start
Vertical pulse width
1
0
1
1
1
note 2
note 3
note 4
note 5
note 6
t1
t2
t3
t4
t5
lines
lines
lines
Vertical display period start position
Vertical display period
1. Lines = 1 Horizontal Line
2. t1typ = (REG[30h] bits 9-0) + 1
3. t2typ = (REG[3Ch] bits 9-0)
4. t3typ = (REG[3Ch] bits 18-16) + 1
5. t4typ = (REG[38h] bits 9-0) + 1
6. t5typ = (REG[34h] bits 9-0) + 1
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6.5.12 TFT Type 2 Panel Timing
t1
t2
FPLINE
(STB)
t3
t4
GPIO0
(VCLK)
t5
t6
GPIO3
(STH)
FPSHIFT
(CLK)
t7
t8
D[17:0]
1
2
Last
DRDY
(INV)
t9
t11
t10
GPIO1
(AP)
t12
GPIO2
(POL)
Figure 6-35: TFT Type 2 Horizontal Timing
Table 6-32: TFT Type 2 Horizontal Timing
Symbol
Parameter
Min
1
Typ
note 2
5
note 3
note 4
note 5
1
Max
1024
Units
Ts (note 1)
Horizontal total period
FPLINE (STB) pulse width
t1
t2
t3
t4
t5
t6
t7
t8
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
GPIO0 (VCLK) rising edge to FPLINE (STB) rising edge
FPLINE (STB) rising edge to GPIO0 (VCLK) falling edge
FPLINE (STB) rising edge to GPIO3 (STH) rising edge
GPIO3 (STH) pulse width
7
7
16
16
Data setup time
Data hold time
Horizontal display period
0.5
0.5
8
40
20
note 6
note 7
note 8
10
1024
90
270
t9
t10
t11
t12
FPLINE (STB) rising edge to GPIO1 (AP) rising edge
GPIO1 (AP) pulse width
FPLINE (STB) rising edge to GPIO2 (POL) toggle position
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1. Ts
= pixel clock period
2. t1typ = [(REG[20h] bits 6-0) + 1] * 8
3. t3typ = (REG[BCh] bits 1-0)
Selected from 7, 9, 12 or 16 Ts
4. t4typ = (REG[BCh] bits 4-3)
Selected from 7, 9, 12 or 16 Ts
5. t5typ = (REG[28h] bits 9-0) + 3 Ts
6. t9typ = [(REG[24h] bits 6-0) + 1] * 8
7. t10typ = (REG[BCh] bits 9-8)
Selected from 40, 52, 68 or 90 Ts
8. t11typ = (REG[BCh] bits 13-11)
Selected from 20, 40, 80, 120, 150, 190, 240 or 270 Ts
t1
t2
FPFRAME
(STV)
t3
GPIO3
(STH)
t4
t5
D[17:0]
Line1
Line2
Last
GPIO2
(POL)
(Odd Frame)
GPIO2
(POL)
(Even Frame)
GPIO2
(POL)
(Alternate Timing)
Figure 6-36: TFT Type 2 Vertical Timing
Table 6-33: TFT Type 2 Vertical Timing
Symbol
Parameter
Min
Typ
Max
Units
Vertical total period
FPFRAME (STV) pulse width
GPIO3 (STH) rising edge to FPFRAME (STV) rising edge
Vertical display start position
Vertical display period
8
1024
Lines
Lines
Ts (note 1)
Lines (note 2)
Ts
t1
t2
t3
t4
t5
1
0
0
1
note 3
note 4
1024
1024
1. Ts
= pixel clock period
2. Lines = 1 Horizontal Line
3. t4typ = (REG[38h] bits 9-0)
4. t5typ = (REG[34h] bits 9-0)
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6.5.13 TFT Type 3 Panel Timing
t1
t2
FPLINE
(LP)
t3
t4
GPIO3
(EIO)
FPSHIFT
(CPH)
t7
t6
t5
t8
D[17:0]
DRDY
(INV)
1
2
t9
t10
GPIO1
(OE)
t11
GPIO2
(POL)
t12
GPO1
(VCOM)
t13
t14
GPIO0
(CPV)
Figure 6-37: TFT Type 3 Horizontal Timing
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Table 6-34: TFT Type 3 Horizontal Timing
Symbol
Parameter
Min
8
1
Typ
Max
1024
256
Units
Ts (note 1)
Horizontal total period
FPLINE (LP) pulse width
t1
t2
t3
t4
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE (LP) rising edge to GPIO3 (EIO) rising edge
GPIO3 (EIO) pulse width
GPIO3 (EIO) rising edge to 1st data
Data setup time
1
1
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
0.5
0.5
8
0
0
Data hold time
Horizontal display period
1024
512
512
512
512
FPLINE (LP) rising edge to GPIO1 (OE) rising edge
GPIO1 (OE) pulse width
FPLINE (LP) rising edge to GPIO2 (POL) toggle position
FPLINE (LP) rising edge to GPO1 (VCOM) toggle position
FPLINE (LP) rising edge to GPIO0 (CPV) rising edge
GPIO0 (CPV) pulse width
0
0
0
0
512
1. Ts
= pixel clock period
2. t1typ = [(REG[20h] bits 6-0) + 1] * 8
3. t2typ = (REG[2Ch] bits 22-16) + 1
3. t3typ = (REG[28h] bits 9-0) + 4 Ts
4. t4typ = Selected from 0, 1, 2 Ts
6. t8typ = [(REG[24h] bits 6-0) + 1] * 8
7. t9typ = (REG[D8h] bits 15-8) * 2
8. t10typ = (REG[D8h] bits 23-16) * 2
9. t11typ = (REG[D8h] bits 31-24) * 2
10. t12typ = (REG[DCh] bits 7-0) * 2
7. t14typ = (REG[DCh] bits 15-8) * 2
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t1
t2
FPFRAME
(STV)
t3
t3
GPIO0
(CPV)
FPLINE
(LP)
t4
t5
Line1
Line2
Last
D[17:0]
t5
GPIO1
(OE)
t6 t7
GPO2
(XOEV)
GPIO2
(POL)
(Odd Frame)
GPO1
(VCOM)
(Odd Frame)
GPIO2
(POL)
(Even Frame)
GPO1
(VCOM)
(Even Frame)
Figure 6-38: TFT Type 3 Vertical Timing
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Table 6-35: TFT Type 3 Vertical Timing
Symbol
Parameter
Min
Typ
Max
Units
Vertical total period
FPFRAME (STV) pulse width
GPIO0 (CPV) rising edge to FPFRAME (STV) rising (falling) edge
Vertical display start position
Vertical display period
1
1024
Lines
Lines
Lines
Lines
Lines
Ts
t1
t2
t3
t4
1
0.5
1
1
0
0
1024
512
512
t5
t6
t7
GPO2 (XOEV) rising edge to GPIO0 (CPV) rising edge
GPIO0 (CPV) rising edge to GPO2 (XOEV) falling edge
Ts
1. Ts
= pixel clock period
2. t4typ = (REG[38h] bits 9-0)
2. t5typ = (REG[34h] bits 9-0) + 1
3. t6typ = (REG[DCh] bits 23-16) * 2
4. t7typ = (REG[DCh] bits 31-24) * 2
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6.5.14 TFT Type 4 Panel Timing
VNDP2
VDP
VNDP1
FPFRAME
FPLINE
LINE480
LINE1
LINE480
FPDAT[17:0]
DRDY
FPLINE
HDP
HNDP1
HNDP2
FPSHIFT
DRDY
1-1
1-2
1-640
invalid
invalid
FPDAT[17:0]
Note: DRDY is used to indicate the first pixel
Example Timing for 12-bit 640x480 panel
Figure 6-39: TFT Type 4 Panel Timing
VDP
= Vertical Display Period
= VDP Lines
VNDP
= Vertical Non-Display Period
= VNDP1 + VNDP2
= VT - VDP Lines
VNDP1 = Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
VNDP2 = Vertical Non-Display Period 2
= VDPS - VPS Lines
if negative add VT
HDP
= Horizontal Display Period
= HDP Ts
HNDP
= Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
HNDP1 = Horizontal Non-Display Period 1
= HDPS - (HPS + 1) + 5 Ts
HNDP2 = Horizontal Non-Display Period 2
= (HPS + 1) - (HDP + HDPS + 5) Ts
if negative add HT
if negative add HT
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t1
t2
FPFRAME
FPLINE
t3
t4
FPLINE
t5
t6
t9
t7
t8
DRDY
t10
t12
t13
t15
t14
t11
FPSHIFT
t16 t17
1
invalid
2
639
640
invalid
FPDAT[17:0]
Note: DRDY is used to indicate the first pixel
Figure 6-40: TFT Type 4 A.C. Timing
Hardware Functional Specification
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Table 6-36: TFT Type 4 A.C. Timing
Symbol
Parameter
Min
VT
VPW
Typ
Max
Units
Lines
Lines
FPFRAME cycle time
FPFRAME pulse width low
t1
t2
t3
t4
t5
FPFRAME falling edge to FPLINE falling edge phase difference HPS + 1
Ts (note 1)
FPLINE cycle time
FPLINE pulse width low
HT
HPW
note 2
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
FPLINE Falling edge to DRDY active
DRDY active to data setup
250
t6
t7
8
DRDY pulse width
HDP
note 3
1
0.5
0.5
0.5
0.5
0.5
0.5
t8
t9
DRDY falling edge to FPLINE falling edge
FPSHIFT period
t10
t11
t12
t13
t14
t15
t16
t17
FPSHIFT pulse width high
FPSHIFT pulse width low
FPLINE setup to FPSHIFT falling edge
DRDY to FPSHIFT falling edge setup time
DRDY hold from FPSHIFT falling edge
Data setup to FPSHIFT falling edge
Data hold from FPSHIFT falling edge
0.5
1. Ts
= pixel clock period
2. t6min = HDPS - (HPS + 1) + 5
3. t8min = (HPS + 1) - (HDP + HDPS + 5)
if negative add HT
if negative add HT
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6.6 USB Timing
Data Signal Rise and Fall Time
Figure 6-41 Data Signal Rise and Fall Time
Figure 6-42 Differential Data Jitter
Figure 6-43 Differential to EOP Transition Skew and EOP Width
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Figure 6-44 Receiver Jitter Tolerance
Table 6-37 USB Interface Timing
Symbol
Parameter
Conditions
Waveform
Min
Typ
Max
Unit
USB
USB Clock Frequency
48
MHz
FREQ
1
T
USB Clock Period
Rise & Fall Times
Figure 6-41
-------------------------
USBFREQ
PERIOD
T
T
T
4
4
20
20
ns
C = 50 pF
Notes 1,2
R
F
L
Figure 6-41
Figure 6-41
Rise/Fall time matching
Output Signal Crossover Voltage
Driver Output Resistance
Data Rate
(T / T )
90
110
2.0
%
V
RFM
R
F
V
Z
1.3
Note 5
CRS
Steady State Drive
28
44
Ω
DRV
T
11.97
12
0
12.03
Mbs
DRATE
Source Differential Driver Jitter to
Next Transition
T
Notes 3,4.
Notes 3,4
Figure 6-42
Figure 6-42
-3.5
3.5
4.0
ns
ns
DDJ1
DDJ2
Source Differential Driver Jitter for
Paired Transitions
T
-4.0
0
Differential to EOP Transition
Skew
T
T
T
Note 4
Note 4
Note 4
Figure 6-43
Figure 6-43
Figure 6-44
-2
0
167
0
5
ns
ns
ns
DEOP
EOPT
JR1
Source EOP Width
160
175
18.5
Receiver Data Jitter Tolerance to
Next Transition
-18.5
Receiver Data Jitter Tolerance for
Paired Transitions
T
T
T
Note 4
Note 4
Note 4
Figure 6-44
Figure 6-43
Figure 6-43
-9
40
80
0
9
ns
ns
ns
JR2
EOP Width at Receiver;
Must reject as EOP
EOPR1
EOPR2
EOP Width at Receiver;
Must accept as EOP
1
Measured from 10% to 90% of the data signal.
2
3
4
5
The rising and falling edges should be smoothly transitioning (monotonic).
Timing difference between the differential data signals.
Measured at crossover point of differential data signals.
20 Ω is placed in series to meet this USB specification. The actual driver output impedance is 15 Ω.
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7 Clocks
7.1 Clock Descriptions
7.1.1 BCLK
BCLK is an internal clock derived from CLKI or CLKI2 (see REG[04h] bit 0). If CLKI is
selected as the source, BCLK can be a divided version (÷1, ÷2) of CLKI. CLKI is typically
derived from the host CPU bus clock.
The source clock options for BCLK may be selected as in the following table.
Table 7-1: BCLK Clock Selection
Source Clock Options
BCLK Selection
CNF6 = 0
CLKI
CLKI
÷
2
CNF6 = 1
Note
For synchronous bus interfaces, it is recommended that BCLK be set the same as the
CPU bus clock (not a divided version of CLKI) e.g. SH-3, SH-4.
7.1.2 MCLK
MCLK provides the internal clock required to access the embedded SRAM. The
S1D13A05 is designed with efficient power saving control for clocks (clocks are turned off
when not used); reducing the frequency of MCLK does not necessarily save more power.
Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the
CPU cycle latency and so reduces screen update performance. For a balance of power
saving and performance, the MCLK should be configured to have a high enough frequency
setting to provide sufficient screen refresh as well as acceptable CPU cycle latency.
Note
The maximum frequency of MCLK is 50MHz (30MHz if running CORE V at 2.0V ±
DD
10%). As MCLK is derived from BCLK, when BCLK is greater than 50MHz, MCLK
must be divided using REG[04h] bits 5-4.
The source clock options for MCLK may be selected as in the following table.
Table 7-2: MCLK Clock Selection
Source Clock Options
MCLK Selection
BCLK
REG[04h] bits 5-4 = 00
REG[04h] bits 5-4 = 01
REG[04h] bits 5-4 = 10
REG[04h] bits 5-4 = 11
BCLK
BCLK
BCLK
÷
÷
÷
2
3
4
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7.1.3 PCLK
PCLK is the internal clock used to control the panel. It should be chosen to match the
optimum frame rate of the panel. See Section 10, “Frame Rate Calculation” on page 162
for details on the relationship between PCLK and frame rate.
Some flexibility is possible in the selection of PCLK. Firstly, panels typically have a range
of permissible frame rates. Secondly, it may be possible to choose a higher PCLK
frequency and tailor the horizontal non-display period to bring down the frame-rate to its
optimal value.
The source clock options for PCLK may be selected as in the following table.
Table 7-3: PCLK Clock Selection
Source Clock Options
PCLK Selection
MCLK
REG[08h] bits 7-0 = 00h
REG[08h] bits 7-0 = 10h
REG[08h] bits 7-0 = 20h
REG[08h] bits 7-0 = 30h
REG[08h] bits 7-0 = 40h
REG[08h] bits 7-0 = 01h
REG[08h] bits 7-0 = 11h
REG[08h] bits 7-0 = 21h
REG[08h] bits 7-0 = 31h
REG[08h] bits 7-0 = 41h
REG[08h] bits 7-0 = 02h
REG[08h] bits 7-0 = 12h
REG[08h] bits 7-0 = 22h
REG[08h] bits 7-0 = 32h
REG[08h] bits 7-0 = 42h
REG[08h] bits 7-0 = 03h
REG[08h] bits 7-0 = 13h
REG[08h] bits 7-0 = 23h
RREG[08h] bits 7-0 = 33h
REG[08h] bits 7-0 = 43h
MCLK
MCLK
MCLK
MCLK
÷
÷
÷
÷
2
3
4
8
BCLK
BCLK
BCLK
BCLK
BCLK
÷
÷
÷
÷
2
3
4
8
CLKI
CLKI
CLKI
CLKI
CLKI
÷
2
÷3
÷4
÷8
CLKI2
CLKI2
÷
÷
÷
÷
2
3
4
8
CLKI2
CLKI2
CLKI2
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There is a relationship between the frequency of MCLK and PCLK that must be
maintained.
Table 7-4: Relationship between MCLK and PCLK
SwivelView Orientation
Color Depth (bpp)
MCLK to PCLK Relationship
16
f
≥ f
MCLK PCLK
8
f
f
f
≥ f
÷
÷
÷
2
4
8
MCLK
MCLK
MCLK
PCLK
PCLK
PCLK
SwivelView 0° and 180°
4
≥ f
≥ f
≥ f
2
1
f
÷
16
MCLK
PCLK
SwivelView 90° and 270°
16/8/4/2/1
f
≥ 1.25f
MCLK
PCLK
7.1.4 PWMCLK
PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel.
The source clock options for PWMCLK may be selected as in the following table.
Table 7-5: PWMCLK Clock Selection
Source Clock Options
PWMCLK Selection
REG[70h] bits 2-1 = 00
REG[70h] bits 2-1 = 01
REG[70h] bits 2-1 = 10
REG[70h] bits 2-1 = 11
CLKI
CLKI2
MCLK
PCLK
For further information on controlling PWMCLK, see “PWM Clock Configuration
Register” on page 121..
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7.2 Clock Selection
The following diagram provides a logical representation of the S1D13A05 internal clocks
used for the LCD controller.
CLKI
0
0
1
BCLK
÷
2
1
1
CNF6
REG[04h] bit 0
REG[04h] bits 5-4
00
01
÷2
÷3
÷4
MCLK
10
11
00
01
000
001
10
11
÷2
÷3
÷4
÷8
CLKI2
010
011
1xx
PCLK
REG[08h] bits 1,0
00
01
REG[08h] bits 6-4
PWMCLK
10
11
REG[70h] bits 2-1
Figure 7-1: Clock Selection
Note
1
CNF6 must be set at RESET#.
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7.3 Clocks versus Functions
Table 7-6: “S1D13A05 Internal Clock Requirements”, lists the internal clocks required for
the following S1D13A05 functions.
Table 7-6: S1D13A05 Internal Clock Requirements
Bus Clock
(BCLK)
Memory Clock
(MCLK)
Pixel Clock
(PCLK)
PWM Clock
(PWMCLK)
USB Clock
(USBCLK)
Function
1
1
Register Read/Write
Memory Read/Write
Required
Required
Not Required
Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Look-Up Table Register
Read/Write
1
Required
Required
Not Required
Not Required
Not Required
1
Software Power Save
LCD Output
Required
Required
Required
Not Required
Required
Not Required
Required
Not Required
Not Required
Not Required
Not Required
Required
1
USB Register Read/Write
Not Required
Not Required
Not Required
Note
1
PWMCLK is an optional clock (see Section 7.1.4, “PWMCLK” on page 87).
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8 Registers
This section discusses how and where to access the S1D13A05 registers. It also provides
detailed information about the layout and usage of each register.
8.1 Register Mapping
The S1D13A05 registers are memory-mapped. When the system decodes the input pins as
CS# = 0 and M/R# = 0, the registers may be accessed. The register space is decoded by
AB[17:0] and is mapped as follows.
Table 8-1: S1D13A05 Register Mapping
M/R#
Address
Size
256K bytes
Function
1
0
0
0
0
00000h to 40000h
0000h to 00E3h
4000h to 4054h
8000h to 8019h
10000h to 1FFFEh
SRAM memory
227 bytes
Configuration registers
USB registers
84 bytes
25 bytes
2D Acceleration Registers
2D Accelerator Data Port
65536 bytes (64K bytes)
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8.2 Register Set
The S1D13A05 register set is as follows.
Table 8-2: S1D13A05 Register Set
Register
Pg
Register
Pg
LCD Register Descriptions (Offset = 0h)
Read-Only Configuration Registers
93
REG[00h] Product Information Register
Clock Configuration Registers
REG[04h] Memory Clock Configuration Register
94
REG[08h] Pixel Clock Configuration Register
95
97
Panel Configuration Registers
REG[0Ch] Panel Type & MOD Rate Register
REG[14h] Power Save Configuration Register
96
REG[10h] Display Settings Register
100
Look-Up Table Registers
REG[18h] Look-Up Table Write Register
101
REG[1Ch] Look-Up Table Read Register
102
Display Mode Registers
REG[20h] Horizontal Total Register
103
104
105
106
108
108
REG[24h] Horizontal Display Period Register
103
104
106
107
108
REG[28h] Horizontal Display Period Start Position Register
REG[30h] Vertical Total Register
REG[2Ch] FPLINE Register
REG[34h] Vertical Display Period Register
REG[3Ch] FPFRAME Register
REG[38h] Vertical Display Period Start Position Register
REG[40h] Main Window Display Start Address Register
REG[48h] Extended Panel Type Register
REG[44h] Main Window Line Address Offset Register
+
Picture-in-Picture Plus (PIP ) Registers
+
+
REG[50h] PIP Window Display Start Address Register
110
111
REG[54h] PIP Window Line Address Offset Register
110
113
+
+
REG[58h] PIP Window X Positions Register
REG[5Ch] PIP Window Y Positions Register
Miscellaneous Registers
REG[60h] Reserved
115
119
122
123
REG[64h] GPIO Status and Control Register
115
121
123
123
REG[68h] GPO Status and Control Register
REG[74h] PWMOUT Duty Cycle Register
REG[84h] Scratch Pad B Register
REG[70h] PWM Clock Configuration Register
REG[80h] Scratch Pad A Register
REG[88h] Scratch Pad C Register
Extended Panel Registers
REG[A0h] HR-TFT CLS Width Register
REG[A8h] HR-TFT PS2 Rising Edge Register
REG[B0h] HR-TFT PS3 Signal Width Register
REG[B8h] HR-TFT PS1/2 End Register
REG[C0h] Casio TFT Timing Register
124
124
125
126
129
129
REG[A4h] HR-TFT PS1 Rising Edge Register
124
125
125
126
128
130
132
133
134
REG[ACh] HR-TFT PS2 Toggle Width Register
REG[B4h] HR-TFT REV Toggle Point Register
REG[BCh] Type 2 TFT Configuration Register
REG[D8h] Type 3 TFT Configuration 0 Register
REG[E0h] Type 3 TFT PCLK Divide Register
REG[E8h] Type 3 TFT Partial Area 0 Positions Register
REG[F0h] Type 3 TFT Partial Area 2 Positions Register
REG[F8h] Type 3 TFT Miscellaneous Register
REG[DCh] Type 3 TFT Configuration 1 Register
REG[E4h] Type 3 TFT Partial Mode Display Control Register 131
REG[ECh] Type 3 TFT Partial Area 1 Positions Register
REG[F4h] Type 3 TFT Command Store Register
132
133
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Table 8-2: S1D13A05 Register Set
Register
Pg
Register
Pg
USB Register Descriptions (Offset = 4000h)
REG[4000h] Control Register
135
137
138
139
140
140
141
141
142
142
144
144
145
145
145
REG[4002h] Interrupt Enable Register 0
136
138
139
139
140
140
141
142
142
143
144
144
145
145
145
REG[4004h] Interrupt Status Register 0
REG[4006h] Interrupt Enable Register 1
REG[4008h] Interrupt Status Register 1
REG[4010h] Endpoint 1 Index Register
REG[4012h] Endpoint 1 Receive Mailbox Data Register
REG[401Ah] Endpoint 2 Transmit Mailbox Data Register
REG[4020h] Endpoint 3 Receive FIFO Data Register
REG[4024h] Endpoint 3 Receive FIFO Status Register
REG[4028h] Endpoint 4 Transmit FIFO Data Register
REG[402Ch] Endpoint 4 Transmit FIFO Status Register
REG[4030h] Endpoint 4 Maximum Packet Size Register
REG[4034h] Frame Counter MSB Register
REG[4038h] Extended Register Index
REG[4018h] Endpoint 2 Index Register
REG[401Ch] Endpoint 2 Interrupt Polling Interval Register
REG[4022h] Endpoint 3 Receive FIFO Count Register
REG[4026h] Endpoint 3 Maximum Packet Size Register
REG[402Ah] Endpoint 4 Transmit FIFO Count Register
REG[402Eh] Endpoint 4 Maximum Packet Size Register
REG[4032h] USB Status Register
REG[4036h] Frame Counter LSB Register
REG[403Ah] Extended Register Data
REG[403Ah], Index[00h] Vendor ID MSB
REG[403Ah], Index[01h] Vendor ID LSB
REG[403Ah], Index[02h] Product ID MSB
REG[403Ah], Index[03h] Product ID LSB
REG[403Ah], Index[04h] Release Number MSB
REG[403Ah], Index[05h] Release Number LSB
REG[403Ah], Index[06h] Receive FIFO Almost Full Threshold 146
REG[403Ah], Index[07h] Transmit FIFO Almost Empty Threshold 146
REG[403Ah], Index[08h] USB Control
146
147
148
149
149
150
152
152
REG[403Ah], Index[09h] Maximum Power Consumption
REG[403Ah], Index[0Bh] Reserved
146
148
148
149
150
151
152
152
REG[403Ah], Index[0Ah] Packet Control
REG[403Ah], Index[0Ch] FIFO Control
REG[4040h] USBFC Input Control Register
REG[4042h] Reserved
REG[4044h] Pin Input Status / Pin Output Data Register
REG[4048h] Interrupt Control Enable Register 1
REG[404Ch] Interrupt Control Status/Clear Register 1
REG[4050h] Interrupt Control Masked Status Register 1
REG[4054h] USB Wait State Register
REG[4046h] Interrupt Control Enable Register 0
REG[404Ah] Interrupt Control Status/Clear Register 0
REG[404Eh] Interrupt Control Masked Status Register 0
REG[4052h] USB Software Reset Register
2D Acceleration (BitBLT) Register Descriptions (Offset = 8000h)
REG[8000h] BitBLT Control Register
153
155
157
158
159
REG[8004h] BitBLT Status Register
154
157
158
158
159
REG[8008h] BitBLT Command Register
REG[8010h] BitBLT Destination Start Address Register
REG[8018h] BitBLT Width Register
REG[800Ch] BitBLT Source Start Address Register
REG[8014h] BitBLT Memory Address Offset Register
REG[801Ch] BitBLT Height Register
REG[8020h] BitBLT Background Color Register
REG[8024h] BitBLT Foreground Color Register
2D Acceleration (BitBLT) Data Register Descriptions (Offset = 10000h)
AB16-AB0 = 10000h-1FFFEh, 2D Accelerator (BitBLT) Data Memory Mapped Region Register
160
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8.3 LCD Register Descriptions (Offset = 0h)
Unless specified otherwise, all register bits are set to 0 during power-on.
8.3.1 Read-Only Configuration Registers
Product Information Register
REG[00h]
Default = 2Dxx402Dh
Read Only
Revision Code
bits 1-0
Product Code bits 5-0
n/a
23
CNF[6:0] Status
19
31
30
29
28
27
26
10
25
24
22
6
21
20
18
2
17
16
Revision Code
bits 1-0
Display Buffer Size bits 7-0
Product Code bits 5-0
15
14
13
12
11
9
8
7
5
4
3
1
0
bits 31-26
bits 25-24
bits 22-16
Product Code
These read-only bits indicate the product code. The product code is 001011 (0Bh).
Revision Code
These are read-only bits that indicates the revision code. The revision code is 01.
CNF[6:0] Status
These read-only status bits return the status of the configuration pins CNF[6:0]. CNF[6:0]
are latched at the rising edge of RESET#.
Note
For a functional description of each configuration bit (CNF[6:0]), see Section 4.3,
“Summary of Configuration Options” on page 25.
bits 15-8
Display Buffer Size Bits [7:0]
This is a read-only register that indicates the size of the SRAM display buffer measured in
4K byte increments. The S1D13A05 display buffer is 256K bytes and therefore this regis-
ter returns a value of 64 (40h).
Value of this register = display buffer size ÷ 4K bytes
= 256K bytes ÷ 4K bytes
= 64 (40h)
bits 7-2
bits 1-0
Product Code
These read-only bits indicate the product code. The product code is 001011 (0Bh).
Revision Code
These are read-only bits that indicates the revision code. The revision code is 01.
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8.3.2 Clock Configuration Registers
Memory Clock Configuration Register
REG[04h]
Default = 00000000h
Read/Write
n/a
31
30
29
13
28
27
26
25
9
24
8
23
7
22
6
21
20
19
3
18
17
16
BCLK
Source
Select
MCLK Divide
Select bits 1-0
n/a
n/a
15
14
12
11
10
5
4
2
1
0
bits 5-4
MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the
Bus Clock (BCLK).
Table 8-3: MCLK Divide Selection
MCLK Divide Select Bits
BCLK to MCLK Frequency Ratio
00
01
10
11
1:1
2:1
3:1
4:1
bit 0
BCLK Source Select
When this bit = 0, the source of the Bus Clock (BCLK) is input pin CLKI or a divided
down version of CLKI. CLKI may be divided down using the CLKI to BCLK divide
select configuration pin CNF6.
When this bit = 1, the source of the Bus Clock (BCLK) is input pin CLKI2.
Note
Changing this bit allows the BCLK source to be switched in a glitch-free manner.
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Pixel Clock Configuration Register
REG[08h]
Default = 00000000h
Read/Write
n/a
31
30
29
13
28
12
27
26
10
25
9
24
8
23
7
22
21
20
19
3
18
2
17
16
PCLK Source
Select bits 1-0
n/a
PCLK Divide Select bits 2-0
n/a
15
14
11
6
5
4
1
0
bits 6-4
PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel
Clock Source.
Table 8-4: PCLK Divide Selection
PCLK Divide Select Bits
PCLK Source to PCLK Frequency Ratio
000
001
010
011
1XX
1:1
2:1
3:1
4:1
8:1
bits 1-0
PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).
Table 8-5: PCLK Source Selection
PCLK Source Select Bits
PCLK Source
00
01
10
11
MCLK
BCLK
CLKI
CLKI2
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8.3.3 Panel Configuration Registers
Panel Type & MOD Rate Register
REG[0Ch]
Default = 00000000h
Read/Write
FPSHIFT
Invert
n/a
n/a
MOD Rate bits 5-0
31
30
29
13
28
27
26
25
9
24
23
22
21
20
19
18
17
16
Panel
Data
Format
Select
Color/
Mono
Panel
Select
HR-TFT
PS
Mode
Panel Data Width Reserv
Panel Type
bits 1-0
n/a
n/a
bits 1-0
ed
3
15
14
12
11
10
8
7
6
5
4
2
1
0
bit 24
FPSHIFT Invert
This bit inverts the FPSHIFT signal used by active panels. For passive panels, this bit has
no effect.
When this bit is 0, FPSHIFT is unchanged.
When this bit is 1, FPSHIFT is inverted.
bits 21-16
bit 8
MOD Rate Bits [5:0]
These bits are for passive LCD panels only.
When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME.
For a non-zero value n, the MOD output signal (DRDY) toggles every n FPLINE.
HR-TFT PS Mode
This bit is for HR-TFT panels only.
This bit selects the timing used for the PS signal. The alternate PS timings (PS1, PS2,
PS3) result in additional power savings on the HR-TFT Panel.
When this bit = 0, the PS signal uses PS1 timing.
When this bit = 1, the PS signal uses PS2 timing.
bit 7
Panel Data Format Select
When this bit = 0, 8-bit single color passive LCD panel data format 1 is selected. For AC
timing see Section 6.5.5, “Single Color 8-Bit Panel Timing (Format 1)” on page 60.
When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. For AC
timing see Section 6.5.6, “Single Color 8-Bit Panel Timing (Format 2)” on page 62.
bit 6
Color/Mono Panel Select
When this bit = 0, a monochrome LCD panel is selected.
When this bit = 1, a color LCD panel is selected.
bits 5-4
Panel Data Width Bits [1:0]
These bits select the data width size of the LCD panel.
Table 8-6: Panel Data Width Selection
Passive Panel Data Width
Panel Data Width Bits [1:0]
Active Panel Data Width Size
Size
00
01
10
11
4-bit
9-bit
12-bit
8-bit
16-bit
18-bit
Reserved
Reserved
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bit 3
Reserved.
This bit must be set to 0.
bits 1-0
Panel Type Bits[1:0]
These bits select the panel type.
Table 8-7: LCD Panel Type Selection
Panel Type Bits [1:0]
Panel Type
STN
00
01
10
11
TFT
Reserved
HR-TFT
Display Settings Register
REG[10h]
Default = 00000000h
Read/Write
Display
Blank
Polarity
SW
Video Window
PIP+
Pixel
Pixel
Display Dithering
SwivelView Mode
Select
n/a
n/a
18
Doubling Doubling
Blank
Disable
Invert
Enable
Vertical
25
Horiz.
24
31
30
29
13
28
12
27
11
26
10
23
22
21
5
20
19
17
16
0
Bits-per-pixel Select
(actual value: 1, 2, 4, 8 or 16 bpp)
n/a
15
14
9
8
7
6
4
3
2
1
bit 25
Pixel Doubling Vertical Enable
This bit controls the pixel doubling feature for the vertical dimension or height of the
panel (i.e. 160 pixel high data doubled to 320 pixel high panel).
When this bit = 1, pixel doubling in the vertical dimension (height) is enabled.
When this bit = 0, there is no hardware effect.
Note
Pixel Doubling is not supported in SwivelView 90° or SwivelView 270° modes.
bit 24
Pixel Doubling Horizontal Enable
This bit controls the pixel doubling feature for the horizontal dimension or width of the
panel (i.e. 160 pixel wide data doubled to 320 pixel wide panel)
When this bit = 1, pixel doubling in the horizontal dimension (width) is enabled.
When this bit = 0, there is no hardware effect.
Note
Pixel Doubling is not supported in SwivelView 90° or SwivelView 270° modes.
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bit 23
Display Blank
When this bit = 0, the LCD display pipeline is enabled.
When this bit = 1, all applicable LCD data outputs (see Table 4-9: “LCD Interface Pin
Mapping,” on page 27) are forced to zero or one. The following table summarizes the
changes to the signals on FPDAT[17:0] for each combination of bits.
Table 8-8: Display Control Summary
Display Blank
(REG[10h] bit 23)
Display Blank Polarity
(REG[10h] bit 21)
Software Video Invert
(REG[10h] bit 20)
Output Data Lines
(FPDAT[17:0])
0
1
0
1
0
1
Normal
Inverted
All 0
0
1
X
0
1
All 1
All 1
All 0
bit 22
Dithering Disable
When this bit = 0, dithering on the passive LCD panel is enabled, allowing a maximum of
18
64K colors (2 ) or 64 gray shades in 1/2/4/8 bpp mode. In 16bpp mode, only 64K colors
16
(2 ) can also be achieved.
When this bit = 1, dithering on the passive LCD panel is disabled, allowing a maximum of
12
4096 colors (2 ) or 16 gray shades.
The dithering algorithm provides more shades of each primary color.
Note
For a summary of the results of dithering for each color depth, see Table 8-10: “LCD
Bit-per-pixel Selection,” on page 99.
bit 21
Display Blank Polarity
When this bit = 0, the display blank function operates normally.
When this bit = 1, the display blank function switches polarity.
This bit works in conjunction with bit 23 and bit 20. Table 8-8: “Display Control Sum-
mary” summarizes the changes to the signals on FPDAT[17:0] for each combination of
bits.
bit 20
Software Video Invert
When this bit = 0, video data is normal.
When this bit = 1, video data is inverted.
This bit works in conjunction with bit 23 and bit 21. Table 8-8: “Display Control Sum-
mary” summarizes the changes to the signals on FPDAT[17:0] for each combination of
bits.
Note
Video data is inverted after the Look-Up Table
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bit 19
PIP+ Window Enable
This bit enables a PIP+ window within the main window. The location of the PIP+ win-
dow within the landscape window is determined by the PIP+ X Position register
(REG[58h]) and PIP+ Y Position register (REG[5Ch]). The PIP+ window has its own Dis-
play Start Address register (REG[50h]) and Memory Address Offset register (REG[54h]).
The PIP+ window shares the same color depth and SwivelViewTM orientation as the main
window.
bit 17-16
SwivelView Mode Select Bits [1:0]
These bits select different SwivelViewTM orientations:
Table 8-9: SwivelViewTM Mode Select Options
SwivelView Mode Select Bits
SwivelView Orientation
00
01
10
11
0° (Normal)
90°
180°
270°
bits 4-0
Bit-per-pixel Select bits [4:0]
These bits select the color depth (bit-per-pixel) for the displayed data for both the main
+
window and the PIP window (if active).
1, 2, 4 and 8 bpp modes use the 18-bit LUT. 16 bpp mode bypasses the LUT. For further
details on the LUT, refer to Section 12, “Look-Up Table Architecture” on page 164.
Table 8-10: LCD Bit-per-pixel Selection
Max. No. Of Simultaneously
Displayed Colors/Shades
Bit-per-pixel Select Bits [4:0]
Color Depth (bpp)
00000
00001
Reserved
1 bpp
2 bpp
2/2
4/4
00010
00011
Reserved
Reserved
00100
4 bpp
16/16
00101 - 00111
01000
8 bpp
256/64
64K/64
10000
16 bpp
10001 - 11111
Reserved
Hardware Functional Specification
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Power Save Configuration Register
REG[14h]
Default = 00000010h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Memory
Power
Save
VNDP
Status
(RO)
Power
Save
Enable
Reserv
ed
n/a
n/a
n/a
Status
(RO)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
bit 7
Vertical Non-Display Period Status (Read-only)
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Display Period.
When this bit = 1, the LCD panel output is in a Vertical Non-Display Period.
bit 6
bit 4
bit 0
Memory Controller Power Save Status (Read-only)
This read-only status bit indicates the power save state of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down and the MCLK source can be
turned off.
Note
Memory reads/writes are possible during power save mode because the S1D13A05 dy-
namically enables the memory controller for display buffer accesses.
Power Save Mode Enable
When this bit = 1, the software initiated power save mode is enabled.
When this bit = 0, the software initiated power save mode is disabled.
At reset, this bit is set to 1. For a summary of Power Save Mode, see Section 15, “Power
Save Mode” on page 178.
Note
Memory reads/writes are possible during power save mode because the S1D13A05 dy-
namically enables the memory controller for display buffer accesses.
Reserved
This bit must be set to 0.
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8.3.4 Look-Up Table Registers
Look-Up Table Write Register
REG[18h]
Default = 00000000h
Write Only
LUT Write Address
LUT Red Write Data
21 20
LUT Blue Write Data
n/a
31
15
30
14
29
28
27
11
26
10
25
9
24
8
23
7
22
6
19
3
18
2
17
1
16
0
LUT Green Write Data
n/a
n/a
13
12
5
4
Note
The S1D13A05 has three 256-position, 6-bit wide LUTs, one for each of red, green, and
blue (see Section 12, “Look-Up Table Architecture” on page 164).
Note
This is a write-only register and returns 00h if read.
bits 31-24
LUT Write Address Bits [7:0]
These bits form a pointer into the Look-Up Table (LUT) which is used to write the LUT
Red, Green, and Blue data. When the S1D13A05 is set to a host bus interface using lit-
tle endian (CNF4 = 0), the RGB data is updated to the LUT with the completion of a
write to these bits.
Note
When a value is written to the LUT Write Address Bits, the same value is automatically
placed in the LUT Read Address Bits (REG[1Ch] bits 31-24).
bits 23-18
bits 15-10
bits 7-2
LUT Red Write Data Bits [5:0]
These bits contains the data to be written to the red component of the Look-Up Table. The
LUT position is controlled by the LUT Write Address bits (bits 31-24).
LUT Green Write Data Bits [5:0]
These bits contains the data to be written to the green component of the Look-Up Table.
The LUT position is controlled by the LUT Write Address bits (bits 31-24).
LUT Blue Write Data Bits [5:0]
These bits contains the data to be written to the blue component of the Look-Up Table.
The LUT position is controlled by the LUT Write Address bits (bits 31-24). When the
S1D13A05 is set to a host bus interface using big endian (CNF4 = 1), the RGB data is
updated to the LUT with the completion of a write to these bits.
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Look-Up Table Read Register
REG[1Ch]
Default = 00000000h
Write Only (bits 31-24)/Read Only
LUT Read Address (write only)
LUT Red Read Data
21 20
LUT Blue Read Data
n/a
31
15
30
29
28
27
11
26
10
25
9
24
8
23
7
22
6
19
3
18
2
17
1
16
0
LUT Green Read Data
n/a
n/a
14
13
12
5
4
Note
The S1D13A05 has three 256-position, 6-bit wide LUTs, one for each of red, green, and
blue (see Section 12, “Look-Up Table Architecture” on page 164).
bits 31-24
LUT Read Address Bits [7:0] (Write Only)
This register forms a pointer into the Look-Up Table (LUT) which is used to read LUT
data. Red data is read from bits 23-18, green data from bits 15-10, and blue data from bits
7-2.
Note
If a write to the LUT Write Address Bits (REG[18h] bits 31-24) is made, the LUT Read
Address bits are automatically updated with the same value.
bits 23-18
bits 15-10
LUT Red Read Data Bits [5:0] (Read Only)
These bits point to the data from the red component of the Look-Up Table. The LUT posi-
tion is controlled by the LUT Read Address bits (bits 31-24). This is a read-only register.
LUT Green Read Data Bits [5:0] (Read Only)
These bits point to the data from the green component of the Look-Up Table. The LUT
position is controlled by the LUT Read Address bits (bits 31-24). This is a read-only regis-
ter.
bits 7-2
LUT Blue Read Data Bits [5:0] (Read Only)
These bits point to the data from the blue component of the Look-Up Table. The LUT
position is controlled by the LUT Read Address bits (bits 31-24). This is a read-only regis-
ter.
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8.3.5 Display Mode Registers
Horizontal Total Register
REG[20h]
Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
26
10
25
9
24
8
23
7
22
6
21
5
20
19
18
17
1
16
0
n/a
Horizontal Total bits 6-0
15
11
4
3
2
bits 6-0
Horizontal Total Bits [6:0]
These bits specify the LCD panel Horizontal Total period, in 8 pixel resolution. The Hori-
zontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display
period. Since the maximum Horizontal Total is 1024 pixels, the maximum panel resolu-
tion supported is 800x600.
REG[20h] bits 6:0 = (Horizontal Total in number of pixels ÷ 8) - 1
Note
1
For all panels this register must be programmed such that:
HDPS + HDP < HT
HT - HDP ≥ 8MCLK
For passive panels, this register must be programmed such that:
2
HPS + HPW < HT
See Section 6.5, “Display Interface” on page 52.
3
Horizontal Display Period Register
REG[24h] Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
26
10
25
9
24
8
23
7
22
6
21
5
20
19
18
17
1
16
0
n/a
Horizontal Display Period bits 6-0
15
11
4
3
2
bits 6-0
Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display period, in 8 pixel resolution. The
Horizontal Display period should be less than the Horizontal Total to allow for a sufficient
Horizontal Non-Display period.
REG[24h] bits 6:0 = (Horizontal Display Period in number of pixels ÷ 8) - 1
Note
For passive panels, HDP must be a minimum of 32 pixels and must be increased by mul-
tiples of 16.
For TFT panels, HDP must be a minimum of 8 pixels and must be increased by multi-
ples of 8.
Note
See Section 6.5, “Display Interface” on page 52.
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Horizontal Display Period Start Position Register
REG[28h]
Default = 00000000h
Read/Write
n/a
31
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
21
20
19
18
2
17
1
16
0
n/a
Horizontal Display Period Start Position bits 9-0
15
14
6
5
4
3
bits 9-0
Horizontal Display Period Start Position Bits [9:0]
These bits specify a value used in the calculation of the Horizontal Display Period Start
Position (in 1 pixel resolution) for TFT and HR-TFT panels.
For passive LCD panels these bits must be set to 00h which will result in HDPS = 22.
HDPS = (REG[28h] bits 9-0) + 22
For TFT panels, HDPS is calculated using the following formula.
HDPS = (REG[28h] bits 9-0) + 5
Note
This register must be programmed such that the following formula is valid.
HDPS + HDP < HT
FPLINE Register
REG[2Ch]
Default = 00000000h
Read/Write
FPLINE
Polarity
n/a
FPLINE Pulse Width bits 6-0
31
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
22
21
20
19
18
2
17
1
16
0
n/a
FPLINE Pulse Start Position bits 9-0
15
7
6
5
4
3
bit 23
FPLINE Pulse Polarity
This bit selects the polarity of the horizontal sync signal. For passive panels, this bit must
be set to 1. For active panels, this bit is set according to the horizontal sync signal of the
panel (typically FPLINE or LP). This bit has no effect for TFT Type 2 and TFT Type 3
panels.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
bits 22-16
FPLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The
horizontal sync signal is typically FPLINE or LP, depending on the panel type.
REG[2Ch] bits 22:16 = FPLINE Pulse Width in number of pixels - 1
Note
For passive panels, these bits must be programmed such that the following formula is
valid.
HPW + HPS < HT
Note
See Section 6.5, “Display Interface” on page 52.
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bits 9-0
FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPLINE Pulse Start Position in pixels = (REG[2Ch] bits 9-0) + 1
Note
For passive panels, these bits must be programmed such that the following formula is
valid.
HPW + HPS < HT
Note
See Section 6.5, “Display Interface” on page 52.
Vertical Total Register
REG[30h]
Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
20
19
3
18
2
17
1
16
0
n/a
Vertical Total bits 9-0
15
5
4
bits 9-0
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
REG[30h] bits 9:0 = Vertical Total in number of lines - 1
Note
1
This register must be programmed such that the following formula is valid.
VT > VDPS + VDP
If an HR-TFT panel is selected, the following formula must also apply.
2
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
See Section 6.5, “Display Interface” on page 52.
3
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Vertical Display Period Register
REG[34h]
Default = 00000000h
Read/Write
n/a
31
15
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
21
20
19
18
2
17
1
16
0
n/a
Vertical Display Period bits 9-0
14
6
5
4
3
bits 9-0
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The
Vertical Display period should be less than the Vertical Total to allow for a sufficient
Vertical Non-Display period.
REG[34h] bits 9:0 = Vertical Display Period in number of lines - 1
Note
1
This register must be programmed such that the following formula is valid.
VT > VDPS + VDP
If an HR-TFT panel is selected, the following formula must also apply.
2
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
See Section 6.5, “Display Interface” on page 52.
3
Vertical Display Period Start Position Register
REG[38h] Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
21
20
19
18
2
17
1
16
0
n/a
Vertical Display Period Start Position bits 9-0
15
6
5
4
3
bits 9-0
Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position for TFT and HR-TFT panels
in 1 line resolution. For passive LCD panels these bits must be set to 00h.
For passive LCD panels these bits must be set to 00h.
For TFT panels, VDPS is calculated using the following formula.
VDPS = REG[38h] bits 9-0
Note
1
This register must be programmed such that the following formula is valid.
VT > VDPS + VDP
If an HR-TFT panel is selected, the following formula must also apply.
2
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
See Section 6.5, “Display Interface” on page 52.
3
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FPFRAME Register
REG[3Ch]
Default = 00000000h
Read/Write
FPFRAME
Polarity
FPFRAME Pulse Width
bits 2-0
n/a
n/a
31
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
22
21
20
19
18
17
16
n/a
FPFRAME Pulse Start Position bits 9-0
15
7
6
5
4
3
2
1
0
bit 23
FPFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. For passive panels, this bit must be
set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the panel
(typically FPFRAME, SPS). This bit has no effect for TFT Type 2 panels.
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
bits 18-16
FPFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The ver-
tical sync signal is typically FPFRAME, or SPS, depending on the panel type.
REG[3Ch] bits 2:0 = FPFRAME Pulse Width in number of lines - 1
Note
See Section 6.5, “Display Interface” on page 52.
bits 9-0
FPFRAME Pulse Start Position Bits [9:0]
These bits specify the start position of the vertical sync signal, in 1 line resolution.
For passive panels, these bits must be set to 00h.
For TFT panels, VDPS is calculated using the following formula.
VPS = REG[3Ch] bits 9-0
Note
See Section 6.5, “Display Interface” on page 52.
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Main Window Display Start Address Register
REG[40h]
Default = 00000000h
Read/Write
n/a
24
bit 16
31
30
29
13
28
12
27
11
26
10
25
23
22
21
5
20
4
19
3
18
2
17
1
16
0
Main Window Display Start Address bits 15-0
15
14
9
8
7
6
bits 16-0
Main Window Display Start Address Bits [16:0]
This register specifies the starting address, in DWORDS, for the LCD image in the display
buffer for the main window.
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the sec-
ond double-word of the display memory, and so on. Calculate the Display Start Address as
follows:
REG[40h] bits 16:0 = image address ÷ 4 (valid only for SwivelView 0°)
Note
For information on setting this register for other SwivelView orientations, see Section
13, “SwivelView™” on page 170.
Main Window Line Address Offset Register
REG[44h] Default = 00000000h
Read/Write
n/a
31
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
21
20
19
18
2
17
1
16
0
n/a
Main Window Line Address Offset bits 9-0
15
14
6
5
4
3
bits 9-0
Main Window Line Address Offset Bits [9:0]
This register specifies the offset, in DWORDS, from the beginning of one display line to
the beginning of the next display line in the main window. Note that this is a 32-bit
address increment. Calculate the Line Address Offset as follows:
REG[44h] bits 9:0 = display width in pixels ÷ (32 ÷ bpp)
Note
A virtual display can be created by programming this register with a value greater than
the formula requires. When a virtual display is created the image width is larger than the
display width and the displayed image becomes a window into the larger virtual image.
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Extended Panel Type Register
REG[48h]
Default = 00000000h
Read/Write
n/a
31
30
29
13
28
27
26
25
9
24
23
7
22
6
21
5
20
4
19
18
17
16
Data
Compare
Invert
Enable
n/a
n/a
Extended Panel Type bits 3-0
15
14
12
11
10
8
3
2
1
0
bit 8
Data Compare Invert Enable
This bit can be used to lower power consumption for TFT Type 2 and TFT Type 3 Inter-
faces. The Data Compare and Invert function reduces the amount of data toggled by
counting the number of bits that are changed (1 to 0 or 0 to 1) from the previous pixel
data. If more than half of the bits are changed the data is inverted and the lesser amount of
bits are toggled. For all other panel interfaces it has no effect.
When this bit = 0, the Data Compare and Invert functions are disabled.
When this bit = 1, the Data Compare and Invert functions are enabled.
bits 3-0
Extended Panel Type Bits [3:0]
These bits override the setting in REG[0Ch] bits 1-0 and allow selection of the alternate
TFT panel types.
Table 8-11: Extended Panel Type Selection
REG[48h] Bits [3:0]
Panel Type
no effect from REG[0Ch] bits 1-0
TFT Type 2
0000
0001
0010
TFT Type 3
0011
TFT Type 4
0100
Casio TFT
0101 - 1111
Reserved
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8.3.6 Picture-in-Picture Plus (PIP+) Registers
PIP+ Display Start Address Register
REG[50h]
Default = 00000000h
Read/Write
n/a
24
bit 16
31
30
14
29
13
28
12
27
11
26
10
25
23
22
21
5
20
4
19
3
18
2
17
1
16
0
PIP+ Display Start Address bits 15-0
15
9
8
7
6
+
bits 16-0
PIP Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the
PIP+ window.
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the sec-
ond double-word of the display memory, and so on.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[10h] bit
19).
PIP+ Line Address Offset Register
REG[54h] Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
21
20
19
18
2
17
1
16
0
n/a
PIP+ Line Address Offset bits 9-0
15
6
5
4
3
+
bits 9-0
PIP Window Line Address Offset Bits [9:0]
These bits are the LCD display’s 10-bit address offset from the starting double-word of
+
line “n” to the starting double-word of line “n + 1” for the PIP window. Note that this is a
32-bit address increment.
Note
+
These bits have no effect unless the PIP Window Enable bit is set to 1 (REG[10h] bit
19).
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PIP+ X Positions Register
REG[58h]
Default = 00000000h
n/a
Read/Write
PIP+ X End Position bits 9-0
22 21 20 19
PIP+ X Start Position bits 9-0
31
15
30
29
13
28
27
11
26
10
25
9
24
8
23
7
18
2
17
1
16
0
n/a
14
12
6
5
4
3
Note
The effect of REG[58h] through REG[5Ch] takes place only after REG[5Ch] is written
and at the next vertical non-display period.
+
bits 25-16
PIP Window X End Position Bits [9:0]
+
These bits determine the X end position of the PIP window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the X end position may not be a
horizontal position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the X End Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the X end position is incremented by x pixels where x is relative to
the current color depth.
Table 8-12: 32-bit Address Increments for Color Depth
Color Depth
1 bpp
Pixel Increment (x)
32
16
8
2 bpp
4 bpp
8 bpp
4
16 bpp
2
For 90° and 270° SwivelView the X end position is incremented in 1 line increments.
Depending on the color depth, some of the higher bits in this register are unused because
the maximum horizontal display width is 1024 pixels.
Note
+
These bits have no effect unless the PIP Window Enable bit is set to 1 (REG[10h] bit
19).
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+
bits 9-0
PIP Window X Start Position Bits [9:0]
+
These bits determine the X start position of the PIP window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the X start position may not be a
horizontal position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the X Start Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the X start position is incremented by x pixels where x is relative to
the current color depth.
Table 8-13: 32-bit Address Increments for Color Depth
Color Depth
1 bpp
Pixel Increment (x)
32
16
8
2 bpp
4 bpp
8 bpp
4
16 bpp
2
For 90° and 270° SwivelView the X start position is incremented in 1 line increments.
Depending on the color depth, some of the higher bits in this register are unused because
the maximum horizontal display width is 1024 pixels.
Note
+
These bits have no effect unless the PIP Window Enable bit is set to 1 (REG[10h] bit
19).
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PIP+ Y Positions Register
REG[5Ch]
Default = 00000000h
n/a
Read/Write
PIP+ Y End Position bits 9-0
22 21 20 19
PIP+ Y Start Position bits 9-0
31
15
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
18
2
17
1
16
0
n/a
14
6
5
4
3
Note
1
The effect of REG[58h] through REG[5Ch] takes place only after REG[5Ch] is
written and at the next vertical non-display period.
2
For host bus interfaces using little endian (CNF4 = 0), a write to bits 31-24 causes the
+
PIP Window Y End Position to take effect.
+
For host bus interfaces using big endian (CNF4 = 1), a write to bits 7-0 causes the PIP
Window Y End Position to take effect.
+
bits 25-16
PIP Window Y End Position Bits [9:0]
+
These bits determine the Y end position of the PIP window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the Y end position may not be a
vertical position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the Y End Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the Y end position is incremented in 1 line increments. For 90° and
270° SwivelView the Y end position is incremented by y pixels where y is relative to the
current color depth.
Table 8-14: 32-bit Address Increments for Color Depth
Color Depth
1 bpp
Pixel Increment (y)
32
16
8
2 bpp
4 bpp
8 bpp
4
16 bpp
2
Depending on the color depth, some of the higher bits in this register are unused because
the maximum vertical display height is 1024 pixels.
Note
+
These bits have no effect unless the PIP Window Enable bit is set to 1 (REG[10h] bit
19).
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+
bits 9-0
PIP Window Y Start Position Bits [9:0]
+
These bits determine the Y start position of the PIP window in relation to the origin of the
panel. Due to the S1D13A05 SwivelView feature, the Y start position may not be a
vertical position value (only true in 0° and 180° SwivelView). For further information
on defining the value of the Y Start Position register, see
Section 14, “Picture-in-Picture Plus (PIP+)” on page 175.
The register is also incremented differently based on the SwivelView orientation. For 0°
and 180° SwivelView the Y start position is incremented in 1 line increments. For 90° and
270° SwivelView the Y start position is incremented by y pixels where y is relative to the
current color depth.
Table 8-15: 32-bit Address Increments for Color Depth
Color Depth
1 bpp
Pixel Increment (y)
32
16
8
2 bpp
4 bpp
8 bpp
4
16 bpp
2
Depending on the color depth, some of the higher bits in this register are unused because
the maximum vertical display height is 1024 pixels.
Note
+
These bits have no effect unless the PIP Window Enable bit is set to 1 (REG[10h] bit
19).
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8.3.7 Miscellaneous Registers
Reserved
REG[60h]
Default = 00000000h
Read/Write
n/a
Reserved
20 19
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
22
6
21
5
18
17
1
16
0
Reserved
n/a
Reserved
n/a
n/a
7
4
3
2
GPIO Status and Control Register
REG[64h] Default = 20000000h
Read/Write
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Input Input Input Input Input Input Input Input
Enable Enable Enable Enable Enable Enable Enable Enable
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Config
Config
Config
Config
Config
Config
Config
Config
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Control/ Control/ Control/ Control/ Control/ Control/ Control/ Control/
n/a
Status
Status
Status
Status
Status
Status
Status
Status
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
The S1D13A05 GPIO pins default to inputs, however they can be individually configured
to outputs or inputs using the GPIO[7:0] Config bits (bits 23-16). If a GPIO pin is
configured as an input, the input functionality must be enabled using the corresponding
GPIO[7:0] Input Enable pin (see bits 31-24). Once the GPIO pin has been configured, it can
be controlled/read using the GPIO[7:0] Control/Status bits (bits 7-0). See the individual bit
descriptions for further details.
Some GPIOs must be configured as outputs after every RESET for use with some extended
panel types (i.e. Sharp HR-TFT, Casio TFT, etc.). See Table 4-9: “LCD Interface Pin
Mapping,” on page 27 and the individual bit descriptions for bits 7-0 for specific infor-
mation on each GPIO pin.
bits 31-24
GPIO[7:0] Input Enable bits
These bits individually enable the input function for each GPIO pin (GPIO[7:0]). After
power-on/reset, each bit must be set to a 1 to enable the input function of each GPIO pin
(default is 0 except for GPIO5 which is 1). If the GPIO pin is configured as an output the
GPIO[7:0] Input Enable bit has no effect.
Note
At power-on/reset, the GPIO5 Input Enable bit (bit 29) defaults to 1.
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bits 23-16
GPIO[7:0] IO Configuration
At power-on/reset, the GPIO[7:0] pins default to inputs. These bits individually configure
each GPIO pin as either an output or input.
When these bits = 0, the associated GPIO pin is configured as an input.
When these bits = 1, the associated GPIO pin is configured as an output.
This may be required for some extended panel types (i.e. Sharp HR-TFT, Casio TFT, etc.)
or USB. See Table 4-9: “LCD Interface Pin Mapping,” on page 27 and the individual bit
descriptions for bits 7-0 for specific information on each GPIO pin.
Note
If a GPIO pin is configured as an input, the input function of the GPIO pin must be en-
abled using the corresponding GPIOx Input Enable bit (bits 31-24) before the input con-
figuration takes effect.
bit 7
GPIO7 IO Control/Status
The following table shows the multiple uses of GPIO7.
Table 8-16: GPIO7 Usage
Function
Pin Usage
Output
Input
Read
Write 0
Write 1
GPIO7
USB
GPIO7 driven low
GPIO7 driven high
GPIO7 status returned
not available (used by USBDP) not available (used by USBDP) not available (used by USBDP)
bit 6
GPIO6 IO Control/Status
The following table shows the multiple uses of GPIO6.
Table 8-17: GPIO6 Usage
Function
Pin Usage
Output
Input
Read
Write 0
Write 1
GPIO6
USB
GPIO6 driven low
GPIO6 driven high
GPIO6 status returned
not available (used by USBDM) not available (used by USBDM) not available (used by USBDM)
bit 5
GPIO5 IO Control/Status
The following table shows the multiple uses of GPIO5.
Table 8-18: GPIO5 Usage
Function
Pin Usage
Output
Input
Read
Write 0
Write 1
GPIO5
USB
GPIO5 driven low
GPIO5 driven high
GPIO5 status returned
not available (used by
USBDETECT)
not available (used by
USBDETECT)
not available (used by
USBDETECT)
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bit 4
GPIO4 IO Control/Status
The following table shows the multiple uses of GPIO4.
Table 8-19: GPIO4 Usage
Function
Output
Pin Usage
Input
Read
Write 0
Write 1
GPIO4
USB
GPIO4 driven low
GPIO4 driven high
GPIO4 status returned
not available (used by
USBPUP)
not available (used by
USBPUP)
not available (used by
USBPUP)
bit 3
GPIO3 IO Control/Status
The following table shows the multiple uses of GPIO3.
Table 8-20: GPIO3 Usage
Function
Output
Pin Usage
Input
Write 0
Write 1
Read
GPIO3
GPIO3 driven low
GPIO3 driven high
GPIO3 status returned
not available (used by SPL)
not available (used by STH)
not available (used by STH)
not available (used by EIO)
Sharp HR-TFT
Casio TFT
not available (used by SPL)
not available (used by STH)
not available (used by STH)
not available (used by EIO)
not available (used by SPL)
not available (used by STH)
not available (used by STH)
not available (used by EIO)
TFT Type 2
TFT Type 3
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bit 2
GPIO2 IO Control/Status
The following table shows the multiple uses of GPIO2.
Table 8-21: GPIO2 Usage
Function
Output
Pin Usage
GPIO2
Input
Write 0
Write 1
Read
GPIO2 driven low
GPIO2 driven high
GPIO2 status returned
not available (used by REV)
not available (used by FRP)
not available (used by POL)
not available (used by POL)
Sharp HR-TFT
Casio TFT
not available (used by REV)
not available (used by FRP)
not available (used by POL)
not available (used by POL)
not available (used by REV)
not available (used by FRP)
not available (used by POL)
not available (used by POL)
TFT Type 2
TFT Type 3
bit 1
GPIO1 IO Control/Status
The following table shows the multiple uses of GPIO1.
Table 8-22: GPIO1 Usage
Function
Output
Pin Usage
Input
Write 0
Write 1
Read
GPIO1
Sharp HR-TFT
Casio TFT
GPIO1 driven low
GPIO1 driven high
not available (used by CLS)
GRES enabled
GPIO1 status returned
not available (used by CLS)
GRES status returned
not available (used by AP)
OE status returned
not available (used by CLS)
GRES forced low
TFT Type 2
TFT Type 3
not available (used by AP)
OE forced low
not available (used by AP)
OE enabled
bit 0
GPIO0 IO Control/Status
The following table shows the multiple uses of GPIO0.
Table 8-23: GPIO0 Usage
Function
Output
Pin Usage
Input
Write 0
Write 1
Read
GPIO0
Sharp HR-TFT
Casio TFT
GPIO0 driven low
GPIO0 driven high
GPIO0 status returned
not available (used by PS)
not available (used by POL)
not available (used by VCLK)
not available (used by CPV)
not available (used by PS)
not available (used by POL)
not available (used by VCLK)
not available (used by CPV)
not available (used by PS)
not available (used by POL)
not available (used by VCLK)
not available (used by CPV)
TFT Type 2
TFT Type 3
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GPO Control Register
REG[68h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
12
27
11
26
25
24
23
22
21
20
19
18
17
16
GPO10 GPO9
GPO8
GPO7
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1
GPO0
n/a
Control Control Control Control Control Control Control Control Control Control Control
15
14
13
10
9
8
7
6
5
4
3
2
1
0
bit 10
GPO10 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO10 high and writing a 0 to this bit drives GPO10 low. A read from this
bit returns the status of GPO10.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets PDME = 1 and writing a 0 sets PDME = 0.
bit 9
bit 8
bit 7
bit 6
GPO9 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO9 high and writing a 0 to this bit drives GPO9 low. A read from this bit
returns the status of GPO9.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XSTBY = 1 and writing a 0 sets XSTBY = 0.
GPO8 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO8 high and writing a 0 to this bit drives GPO8 low. A read from this bit
returns the status of GPO8.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XOHV = 1 and writing a 0 sets XOHV = 0.
GPO7 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO7 high and writing a 0 to this bit drives GPO7 low. A read from this bit
returns the status of GPO7.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XRESV = 1 and writing a 0 sets XRESV = 0.
GPO6 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO6 high and writing a 0 to this bit drives GPO6 low. A read from this bit
returns the status of GPO6.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit sets XRESH = 1 and writing a 0 sets XRESH = 0.
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bit 5
GPO5 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO5 high and writing a 0 to this bit drives GPO5 low. A read from this bit
returns the status of GPO5.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables PCLK2 and writing a 0 forces PCLK2 low.
bit 4
bit 3
bit 2
bit 1
bit 0
GPO4 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO4 high and writing a 0 to this bit drives GPO4 low. A read from this bit
returns the status of GPO4.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables PCLK1 and writing a 0 forces PCLK1 low.
GPO3 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO3 high and writing a 0 to this bit drives GPO3 low. A read from this bit
returns the status of GPO3.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), GPO3 is not
available.
GPO2 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO2 low and writing a 0 to this bit drives GPO2 high. A read from
this bit returns the status of GPO2.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables XOEV and writing a 0 sets XOEV = 0.
GPO1 Control
When the Type 3 TFT LCD interface is not selected (REG[48h] bits 3:0), writing a 1 to
this bit drives GPO1 high and writing a 0 to this bit drives GPO1 low. A read from this bit
returns the status of GPO1.
When the Type 3 TFT LCD interface is selected (REG[48h] bits 3:0 = 0010), writing a 1
to this bit enables VCOM and writing a 0 sets VCOM = 0.
GPO0 Control
Writing a 1 to this bit drives GPO0 high and writing a 0 to this bit drives GPO0 low. A
read from this bit returns the status of GPO0.
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PWM Clock Configuration Register
REG[70h]
Default = 00000000h
Read/Write
n/a
31
30
29
13
28
27
26
25
9
24
8
23
7
22
21
20
4
19
18
17
16
PWM
Clock
Force
High
PWM
Clock
Enable
PWM Clock Divide Select
bits 3-0
PWMCLK Source
Select bits 1-0
n/a
15
14
12
11
10
6
5
3
2
1
0
PWM Clock Enable
Divided
Clock
PWM Duty Cycle
Modulation
PWM Clock
Divider
to PWMOUT
PWMCLK
m
Duty = n / 256
Clock Source / 2
frequency =
m
Clock Source / (2 X 256)
n = PWM Clock Duty Cycle
m = PWM Clock Divide Select value
PWM Clock Force High
Figure 8-1: PWM Clock Block Diagram
Note
For further information on PWMCLK, see Section 7.1.4, “PWMCLK” on page 87.
bits 7-4
PWM Clock Divide Select Bits [3:0]
The value of these bits represents the power of 2 by which the selected PWM clock source
is divided.
Table 8-24: PWM Clock Divide Select Options
PWM Clock Divide Select Bits [3:0]
PWM Clock Divide Amount
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
Note
This divided clock is further divided by 256 before it is output at PWMOUT.
Hardware Functional Specification
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bit 3
PWM Clock Force High
When this bit = 0, the PWMOUT pin function is controlled by the PWM Clock enable bit.
When this bit = 1, the PWMOUT pin is forced to high.
bits 2-1
PWMCLK Source Select Bits [1:0]
These bits determine the source of PWMCLK.
Table 8-25: PWMCLK Source Selection
REG[70h] bits 2-1
PWMCLK Source
CLKI
00
01
10
11
CLKI2
BCLK
PCLK
Note
For further information on the PWMCLK source select, see Section 7.2, “Clock Selec-
tion” on page 88.
bit 0
PWM Clock Enable
When this bit = 0, PWMOUT output acts as a general purpose output pin controllable by
bit 3 of REG[70h].
When this bit = 1, the PWM Clock circuitry is enabled.
Note
The PWM Clock circuitry is disabled when Power Save Mode is enabled.
PWMOUT Duty Cycle Register
REG[74h] Default = 00000000h
Read/Write
n/a
31
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
20
19
18
17
1
16
0
n/a
PWMOUT Duty Cycle bits 7-0
15
14
5
4
3
2
bits 7-0
PWMOUT Duty Cycle Bits [7:0]
This register determines the duty cycle of the PWMOUT output.
Table 8-26: PWMOUT Duty Cycle Select Options
PWMOUT Duty Cycle [7:0]
PWMOUT Duty Cycle
Always Low
00h
01h
02h
...
High for 1 out of 256 clock periods
High for 2 out of 256 clock periods
...
FFh
High for 255 out of 256 clock periods
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Hardware Functional Specification
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Scratch Pad A Register
REG[80h]
Default = not applicable
Read/Write
Scratch Pad A bits 31-24
24 23
Scratch Pad A bits 15-0
31
30
29
13
28
12
27
11
26
10
25
9
22
6
21
5
20
4
19
3
18
2
17
1
16
0
15
14
8
7
bits 31-0
Scratch Pad A Bits [31:0]
This register contains general purpose read/write bits. These bits have no effect on hard-
ware.
Note
The contents of the Scratch Pad A register defaults to an un-defined state after initial
power-up. Any data written to this register remains intact when the S1D13A05 is reset,
as long as the chip is not powered off.
Scratch Pad B Register
REG[84h] Default = not applicable
Read/Write
Scratch Pad B bits 31-24
24 23
Scratch Pad B bits 15-0
31
30
14
29
13
28
12
27
11
26
10
25
9
22
6
21
5
20
4
19
3
18
2
17
1
16
0
15
8
7
bits 31-0
Scratch Pad B Bits [31:0]
This register contains general purpose read/write bits. These bits have no effect on hard-
ware.
Note
The contents of the Scratch Pad B register defaults to an un-defined state after initial
power-up. Any data written to this register remains intact when the S1D13A05 is reset,
as long as the chip is not powered off.
Scratch Pad C Register
REG[88h] Default = not applicable
Read/Write
Scratch Pad C bits 31-24
24 23
Scratch Pad C bits 15-0
31
30
14
29
13
28
12
27
11
26
10
25
9
22
6
21
5
20
4
19
3
18
2
17
1
16
0
15
8
7
bits 31-0
Scratch Pad C Bits [31:0]
This register contains general purpose read/write bits. These bits have no effect on hard-
ware.
Note
The contents of the Scratch Pad C register defaults to an un-defined state after initial
power-up. Any data written to this register remains intact when the S1D13A04 is reset,
as long as the chip is not powered off.
Hardware Functional Specification
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8.3.8 Extended Panel Registers
HR-TFT CLS Width Register
REG[A0h]
Default = 0000012Ch
Read/Write
n/a
31
30
14
29
13
28
27
11
26
10
25
9
24
8
23
7
22
6
21
20
19
18
2
17
1
16
0
n/a
CLS Pulse Width bits 8-0
15
12
5
4
3
bits 8-0
CLS Pulse Width Bits [8:0]
This register determines the width of the CLS signal in PCLKs.
Note
This register must be programmed such that the following formula is valid.
(REG[A0h] bits 8-0) > 0
HR-TFT PS1 Rising Edge Register
REG[A4h] Default = 00000032h
Read/Write
n/a
31
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
18
17
1
16
0
n/a
PS1 Rising Edge bits 5-0
15
14
3
2
bits 5-0
PS1 Rising Edge Bits [5:0]
This register determines the number of PCLKs between the CLS falling edge and the PS1
rising edge.
HR-TFT PS2 Rising Edge Register
REG[A8h] Default = 00000064h
Read/Write
n/a
31
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
19
18
2
17
1
16
0
n/a
PS2 Rising Edge bits 7-0
15
14
4
3
bits 7-0
PS2 Rising Edge Bits [7:0]
This register determines the number of PCLKs between the LP falling edge and the first
PS2 rising edge.
Note
This register must be programmed such that the following formula is valid.
(REG[A8h] bits 7-0) > 0
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HR-TFT PS2 Toggle Width Register
REG[ACh]
Default = 0000000Ah
Read/Write
n/a
31
30
14
29
13
28
12
27
26
10
25
9
24
8
23
7
22
6
21
5
20
19
18
17
1
16
0
n/a
PS2 Toggle Width bits 6-0
15
11
4
3
2
bits 6-0
PS2 Toggle Width Bits [6:0]
This register determines the width of the PS2 signal before toggling (in number of
PCLKs).
Note
This register must be programmed such that the following formula is valid.
(REG[ACh] bits 6-0) > 0
HR-TFT PS3 Signal Width Register
REG[B0h] Default = 00000064h
Read/Write
n/a
31
30
29
13
28
12
27
26
10
25
9
24
8
23
7
22
6
21
5
20
19
18
17
1
16
0
n/a
PS3 Signal Width bits 6-0
15
14
11
4
3
2
bits 6-0
PS3 Signal Width Bits [6:0]
This register determines the width of the PS3 signal in PCLKs.
Note
This register must be programmed such that the following formula is valid.
(REG[B0h] bits 6-0) > 0
HR-TFT REV Toggle Point Register
REG[B4h] Default = 0000000Ah
Read/Write
n/a
31
30
29
13
28
12
27
11
26
25
9
24
8
23
7
22
6
21
5
20
4
19
18
17
16
0
n/a
REV Toggle bits 4-0
15
14
10
3
2
1
bits 4-0
REV Toggle Bits [4:0]
This register determines the width in PCLKs to toggle the REV signal prior to LP rising
edge.
Hardware Functional Specification
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HR-TFT PS1/2 End Register
REG[B8h]
Default = 00000007h
Read/Write
n/a
31
30
29
13
28
12
27
11
26
10
25
24
8
23
7
22
6
21
5
20
4
19
3
18
17
16
n/a
PS1/2 End bits 2-0
1
15
14
9
2
0
bits 2-0
PS1/2 End Bits [2:0]
This register allows the PS signal to continue into the vertical non-display period (in
lines).
Note
This register must be programmed such that the following formula is valid.
VT > (REG[B8h] bits 2-0) + VDP + VPS + 1
Type 2 TFT Configuration Register
REG[BCh] Default = 00000000h
Read/Write
n/a
31
30
29
13
28
27
11
26
25
24
23
7
22
21
5
20
VCLK Hold
bits 1-0
19
18
17
16
POL
Type
AP Pulse Width
bits 2-0
APRising Position
bits 1-0
VCLK Setup
bits 1-0
n/a
n/a
n/a
n/a
15
14
12
10
9
8
6
4
3
2
1
0
bit 15
POL Type
This bit selects how often the POL signal is toggled. The S1D13A05 GPIO2 pin controls
the POL signal used for the TFT Type 2 Interface. For all other panel interfaces this bit has
no effect.
When this bit = 0, the POL signal is toggled every line.
When this bit = 1, the POL signal is toggled every frame.
bits 13-11
AP Pulse Width Bits [2:0]
These bits specify the AP Pulse Width used for the TFT Type 2 Interface. The S1D13A05
GPIO1 pin controls the AP signal for the TFT Type 2 Interface. For all other panel inter-
faces it has no effect.
Table 8-27: AP Pulse Width
REG[4Ch] bits 13-11
AP Pulse Width (in PCLKs)
000
001
010
011
100
101
110
111
20
40
80
120
150
190
240
270
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bits 9-8
bits 4-3
bits 1-0
AP Rising Position Bits [1:0]
These bits specify the TFT Type 2 AC timing parameter from the rising edge of FPLINE
(STB) to the rising edge of GPIO1 (AP). The parameter is selected as follows. For all
other panel interfaces it has no effect.
Table 8-28: AP Rising Position
REG[4Ch] bits 9-8
AP Rising Position (in PCLKs)
00
01
10
11
40
52
68
90
VCLK Hold Bits [1:0]
These bits specify the TFT Type 2 AC timing parameter from the rising edge of FPLINE
(STB) to the falling edge of GPIO0 (VCLK). The parameter is selected as follows. For all
other panel interfaces it has no effect.
Table 8-29: VCLK Hold
REG[4Ch] bits 4-3
VCLK Hold (in PCLKs)
00
01
10
11
7
9
12
16
VCLK Setup Bits [1:0]
These bits specify the TFT Type 2 AC timing parameter from the rising edge of GPIO0
(VCLK) to the rising edge of FPLINE (STB). The parameter is selected as follows. For all
other panel interfaces it has no effect.
Table 8-30: VCLK Setup
REG[4Ch] bits 1-0
VCLK Setup (in PCLKs)
00
01
10
11
7
9
12
16
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Casio TFT Timing Register
REG[C0h]
Default = 09180E09h
Read/Write
n/a
GPCK Rising Edge to STH Pulse bits 5-0
28 27 26 25
GRES Falling Edge to GPCK Rising Edge bits 4-0
13 12 11 10
GRES Falling Edge to FRP Toggle Point bits 6-0
21 20 19 18 17
GPCK Rising Edge to GRES Rising Edge bits 5-0
n/a
23
31
15
30
14
29
24
22
6
16
n/a
n/a
9
8
7
5
4
3
2
1
0
bits 29-24
bits 22-16
bits 13-8
bits 5-0
GPCK Rising Edge to STH Pulse Bits[5:0]
These bits determine the number of PCLKs from GPCK rising edge to STH pulse.
GRES Falling Edge to FRP Toggle Point Bits[6:0]
These bits determine the number of PCLKs from GRES falling edge to FRP Toggle point.
GRES Falling Edge to GPCK Rising Edge Bits[5:0]
These bits determine the number of PCLKs from GRES falling edge to GPCK rising edge.
GPCK Rising Edge to GRES Rising Edge Bits[5:0]
These bits determine the number of PCLKs from GPCK rising edge to GRES rising edge.
Type 3 TFT Configuration Register 0
REG[D8h]
Default = 00000000h
Read/Write
POL Toggle Position bits 7-0
OE Pulse Width bits 7-0
31
15
30
29
OE Rising Edge Position bits 7-0
13 12 11 10
28
27
26
25
9
24
8
23
7
22
6
21
5
20
19
18
2
17
1
16
0
n/a
14
4
3
bits 31-24
bits 23-16
bits 15-8
POL Toggle Position Bits [7:0]
These bits specify the toggle position of the POL signal in 2 pixel resolution. The
S1D13A05 GPIO2 pin controls the POL signal used for the TFT Type 3 Interface. This
register has no effect for all other panel interfaces.
POL Toggle Position in pixels = (REG[D8h] bits 31-24) × 2
OE Pulse Width Bits [7:0]
These bits specify the pulse width of the OE signal in 2 pixel resolution. The S1D13A05
GPIO1 pin controls the OE signal used for the TFT Type 3 Interface. This register has no
effect for all other panel interfaces.
OE Pulse Width in pixels = (REG[D8h] bits 23-16) × 2
OE Rising Edge Position Bits [7:0]
These bits specify the rising edge position of the OE signal in 2 pixel resolution. The
S1D13A05 GPIO1 pin controls the OE signal used for the TFT Type 3 Interface. This reg-
ister has no effect for all other panel interfaces.
OE Rising Edge Position in pixels = (REG[D8h] bits 15-8) × 2
S1D13A05
X40A-A-001-07
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Type 3 TFT Configuration Register 1
REG[DCh]
Default = 00000000h
Read/Write
XOEV End Position bits 7-0
XOEV Start Position bits 7-0
21 20 19 18
VCOM Toggle Position bits 7-0
31
15
30
14
29
13
28
CPV Pulse Width bits 6-0
12 11
27
26
10
25
9
24
8
23
7
22
6
17
1
16
0
5
4
3
2
bits 31-24
XOEV End Position Bits [7:0]
These bits specify the falling/rising edge position of the XOEV signal in 2 pixel resolution
(depending on the FPFRAME Pulse Polarity bit in REG[3Ch] bit 23). The S1D13A05
GPO2 pin controls the XOEV signal used for the TFT Type 3 Interface. This register has
no effect for all other panel interfaces.
XOEV Falling Edge Position in pixels = (REG[DCh] bits 31-24) × 2
Note
If this register is set to 0, no pulse is generated.
bits 23-16
XOEV Start Position Bits [7:0]
These bits specify the rising/falling edge position of the XOEV signal in 2 pixel resolution
(depending on the FPFRAME Pulse Polarity bit in REG[3Ch] bit 23). The S1D13A05
GPO2 pin controls the XOEV signal used for the TFT Type 3 Interface. This register has
no effect for all other panel interfaces.
XOEV Rising Edge Position in pixels = (REG[DCh] bits 23-16) × 2
Note
If this register is set to 0, no pulse is generated.
bits 15-8
bits 7-0
CPV Pulse Width Bits [7:0]
These bits specify the pulse width of the CPV signal in 2 pixel resolution. The S1D13A05
GPIO0 pin controls the CPV signal used for the TFT Type 3 Interface. This register has no
effect for all other panel interfaces.
CPV Pulse Width in pixels = (REG[DCh] bits 15-8) × 2
VCOM Toggle Position Bits [7:0]
These bits specify the toggle position of the VCOM signal in 2 pixel resolution. The
S1D13A05 GPO1 pin controls the VCOM signal used for the TFT Type 3 Interface. This
register has no effect for all other panel interfaces.
VCOM Toggle Position in pixels = (REG[DCh] bits 7-0) × 2
Hardware Functional Specification
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Type 3 TFT PCLK Divide Register
REG[E0h]
Default = 00000000h
Read/Write
n/a
31
30
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
20
19
3
18
17
16
0
PCLK2 Divide
Rate bits 1-0
n/a
PCLK1 Divide Rate bits 3-0
15
14
5
4
2
1
bit 5-4
PCLK2 Divide Rate Bits [1:0]
These bits specify the divide rate for PCLK2. This register is used for the TFT Type 3
Interface and has no effect for all other panel interfaces.
Table 8-31: PCLK2 Divide Rate
REG[C8h] bits 5-4
PCLK2 Divide Rate
00
01
10
11
64
128
256
512
bits 3-0
PCLK1 Divide Rate Bits [3:0]
These bits specify the divide rate for PCLK1. This register is used for the TFT Type 3
Interface and has no effect for all other panel interfaces.
Table 8-32: PCLK1 Divide Rate
REG[C8h] bits 3-0
0000
PCLK1 Divide Rate
2
4
0001
0010
8
0011
16
0100
32
0101
64
0110
128
256
512
1024
2048
4096
8192
16384
32768
65536
0111
1000
1001
1010
1011
1100
1101
1110
1111
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X40A-A-001-07
Hardware Functional Specification
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Type 3 TFT Partial Mode Display Area Control Register
REG[E4h]
Default = 00000000h
Read/Write
n/a
31
30
29
28
27
26
25
24
23
7
22
21
5
20
19
18
17
16
Partial
Mode
Partial
Mode
Display
Enable
Area 2
Area 1
Area 0
n/a
Partial Mode Display Refresh Cycle bits 5-0
n/a
Display Display Display Display
Type
Select
Enable Enable Enable
15
14
13
12
11
10
9
8
6
4
3
2
1
0
bits 13-8
bit 4
Partial Mode Display Refresh Cycle Bits [5:0]
These bits specify the refresh cycle for the Partial Mode Display. The refresh cycle can be
a value from 0 to 63. This register is used for the TFT Type 3 Interface and has no effect
for all other panel interfaces.
Partial Mode Display Enable
This bit enables/disables the Partial Mode Display for the TFT Type 3 and has no effect
for all other panel interfaces.
When this bit = 1, Partial Mode Display is enabled.
When this bit = 0, Partial Mode Display is disabled.
bit 3
Partial Mode Display Type Select
This bit selects the type of partial mode display.
When this bit =0, the Stripe type of partial mode display is selected. If Stripe is enabled
only the Y Position registers are used in calculating the partial display.
When this bit = 1, type Block type of partial mode display is selected. If Block is enabled
both the X and Y Position registers are used in calculating the partial display.
bit 2
bit 1
bit 0
Area 2 Display Enable
This bit enables/disables the Area 2 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 2 is enabled.
When this bit = 0, Area 2 is disabled.
Area 1 Display Enable
This bit enables/disables the Area 1 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 1 is enabled.
When this bit = 0, Area 1 is disabled.
Area 0 Display Enable
This bit enables/disables the Area 0 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 0 is enabled.
When this bit = 0, Area 0 is disabled.
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Type 3 TFT Partial Area 0 Positions Register
REG[E8h]
Default = 00000000h
Read/Write
n/a
Partial Area 0 Y End Position bits 5-0
Partial Area 0 X End Position bits 5-0
n/a
n/a
31
15
30
14
29
13
28
Partial Area 0 Y Start Position bits 5-0
12 11 10
27
26
25
24
8
23
7
22
6
21
5
20
19
18
17
16
0
n/a
Partial Area 0 X Start Position bits 5-0
9
4
3
2
1
bits 29-24
bits 21-16
bits 13-8
bits 5-0
Partial Area 0 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 0 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 0 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 0 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 0 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 0 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 0 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 0 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Type 3 TFT Partial Area 1 Positions Register
REG[ECh]
Default = 00000000h
Read/Write
n/a
Partial Area 1 Y End Position bits 5-0
Partial Area 1 X End Position bits 5-0
20 19 18 17
Partial Area 1 X Start Position bits 5-0
n/a
n/a
31
15
30
14
29
13
28
Partial Area 1 Y Start Position bits 5-0
12 11 10
27
26
25
24
8
23
7
22
6
21
5
16
0
n/a
9
4
3
2
1
bits 29-24
bits 21-16
bits 13-8
bits 5-0
Partial Area 1 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 1 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 1 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 1 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 1 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 1 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 1 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 1 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
S1D13A05
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Type 3 TFT Partial Area 2 Positions Register
REG[F0h]
Default = 00000000h
Read/Write
n/a
Partial Area 2 Y End Position bits 5-0
Partial Area 2 X End Position bits 5-0
20 19 18 17
Partial Area 2 X Start Position bits 5-0
n/a
n/a
31
15
30
14
29
13
28
Partial Area 2 Y Start Position bits 5-0
12 11 10
27
26
25
24
8
23
7
22
6
21
5
16
0
n/a
9
4
3
2
1
bits 29-24
bits 21-16
bits 13-8
bits 5-0
Partial Area 2 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 2 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 2 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Partial Area 2 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
Type 3 TFT Command Store Register
REG[F4h] Default = 00000000h
Read/Write
n/a
Command 1 Store bits 11-0
22 21
Command 0 Store bits 11-0
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
20
4
19
3
18
2
17
1
16
0
n/a
6
5
bits 27-16
Command 1 Store Bits [11:0]
These bits store command 1 for the TFT Type 3 Interface. This register has no effect for
all other panel interfaces.
bits 11-0
Command 0 Store Bits [11:0]
These bits store command 0 for the TFT Type 3 Interface. This register has no effect for
all other panel interfaces.
Hardware Functional Specification
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Type 3 TFT Miscellaneous Register
REG[F8h]
Default = 00000000h
Read/Write
n/a
31
30
29
13
28
27
26
25
24
23
7
22
6
21
5
20
19
3
18
2
17
16
Command
Send
Request
Source Driver IC
Number bits 1-0
n/a
n/a
15
14
12
11
10
9
8
4
1
0
bits 9-8
Source Driver IC Number Bits [1:0]
These bits contain the number of Source Driver ICs.
Table 8-33: Number of Source Driver ICs
REG[E0h] bits 1-0
Source Driver ICs
00
01
10
11
1
2
3
4
bit 0
Command Send Request
After the CPU sets this bit, the S1D13A05 sends the command in the next non-display
period and clears this bit automatically. This register has no effect for all other panel inter-
faces.
S1D13A05
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8.4 USB Registers (Offset = 4000h)
The S1D13A05 USB device occupies a 48 byte local register space which can be accessed
by the CPU on the local host interface.
To access the USB registers:
1. A valid USBCLK must be provided.
2. The USBClk Enable bit (REG[4000h] bit 7) must be set to 1 and the USB Setup bit
(REG[4000h] bit 2) must be set to 1. Both bits should be set together.
If any of the above conditions are not true, the USB registers must not be accessed.
Control Register
REG[4000h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
USBClk Enable
Software EOT
USB Enable
Endpoint 4 Stall
Endpoint 3 Stall
USB Setup
Reserved
Reserved
7
6
5
4
3
2
1
0
bit 7
USBClk Enable.
This bit allows the USBClk to be enabled/disabled allowing the S1D13A05 to save power
when the USBClk is not required. The USBClk Enable bit operates independently of the
Power Save Mode Enable bit (REG[14h] bit 4). For example, enabling power save mode
does not disable the USB section of the S1D13A05. It must be disabled using the USBClk
enable bit.
This bit should initially be set with the USB Setup bit. However, it can be disabled/re-
enabled individually.
When this bit = 1, the USBClk is enabled.
When this bit = 0, the USBClk is disabled.
Note
The USB Registers must not be accessed when this bit is 0.
bit 6
Software EOT
This bit determines the response to an IN request to Endpoint 4 when the transmit FIFO is
empty. If this bit is asserted, the S1D13A05 responds to an IN request to Endpoint 4 with
an ACK and a zero length packet if the FIFO is empty. If this bit is not asserted, the
S1D13A05 responds to an IN request from Endpoint 4 with an NAK if the FIFO is empty,
indicating that it expects to transmit more data. This bit is automatically cleared when the
S1D13A05 responds to the host with a zero length packet when the FIFO is empty.
Hardware Functional Specification
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bit 5
USB Enable
Any device or configuration descriptor reads from the host will be acknowledged with a
NAK until this bit is set. This allows time for the local CPU to set up the interrupt polling
register, maximum packet size registers, and other configuration registers (e.g. Product ID
and Vendor ID) before the host reads the descriptors.
Note
As the device and configuration descriptors cannot be read by the host until the USB
Enable bit is set, the device enumeration process will not complete and the device will
not be recognized on the USB.
bit 4
bit 3
bit 2
Endpoint 4 Stall.
If this bit is set, host bulk reads from the transmit FIFO will result in a STALL acknowl-
edge by the S1D13A05. No data will be returned to the USB host.
Endpoint 3 Stall.
If this bit is set, host bulk writes to the receive FIFO will result in a STALL acknowledge
by the S1D13A05. Receive data will be discarded.
USB Setup
This bit is used by software to select between GPIO and USB functions for multifunction
GPIO pins (GPIO[7:4]). This bit should be set at the same time as the USBClk Enable bit.
When this bit = 1, the USB function is selected.
When this bit = 0, the GPIO function is selected.
Note
The USB Registers must not be accessed when this bit is 0.
bit 1
bit 0
Reserved.
This bit must be set to 0.
Reserved.
This bit must be set to 0.
Interrupt Enable Register 0
REG[4002h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
Suspend Request
Interrupt Enable
SOF Interrupt
Enable
Endpoint 4
Interrupt Enable
Endpoint 3
Interrupt Enable
Endpoint 2
Interrupt Enable
Endpoint 1
Interrupt Enable
Reserved
n/a
7
6
5
4
3
2
1
0
bit 7
Suspend Request Interrupt Enable.
When set, this bit enables an interrupt to occur when the USB host is requesting the
S1D13A05 USB device to enter suspend mode.
bit 6
bit 5
SOF Interrupt Enable.
When set, this bit enables an interrupt to occur when a start-of-frame packet is received by
the S1D13A05.
Reserved.
This bit must be set to 0.
S1D13A05
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bit 4
bit 3
bit 2
bit 1
Endpoint 4 Interrupt Enable.
When set, this bit enables an interrupt to occur when a USB Endpoint 4 Data Packet has
been sent by the S1D13A05.
Endpoint 3 Interrupt Enable.
When set, this bit enables an interrupt to occur when a USB Endpoint 3 Data Packet has
been received by the S1D13A05.
Endpoint 2 Interrupt Enable.
When set, this bit enables an interrupt to occur when the USB Endpoint 2 Transmit Mail-
box registers have been read by the USB host.
Endpoint 1 Interrupt Enable.
When set, this bit enables an interrupt to occur when the USB Endpoint 1 Receive Mail-
box registers have been written to by the USB host.
Interrupt Status Register 0
REG[4004h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
Upper Interrupt
Active
(read only)
Suspend Request
Interrupt Status
SOF Interrupt
Status
Endpoint 4
Interrupt Status
Endpoint 3
Interrupt Status
Endpoint 2
Interrupt Status
Endpoint 1
Interrupt Status
Reserved
7
6
5
4
3
2
1
0
bit 7
Suspend Request Interrupt Status.
This bit indicates when a suspend-request has been received by the S1D13A05. Writing a
1 clears this bit.
bit 6
SOF Interrupt Status.
This bit indicates when a start-of-frame packet has been received by the S1D13A05. Writ-
ing a 1 clears this bit.
bit 5
bit 4
Reserved.
This bit must be set to 0.
Endpoint 4 Interrupt Status.
This bit indicates when a USB Endpoint 4 Data packet has been sent by the S1D13A05.
Writing a 1 clears this bit.
bit 3
Endpoint 3 Interrupt Status (Receive FIFO Valid).
This bit indicates when a USB Endpoint 3 Data packet has been received by the
S1D13A05. No more packets to endpoint 3 will be accepted until this bit is cleared. Writ-
ing a 1 clears this bit.
bit 2
bit 1
bit 0
Endpoint 2 Interrupt Status.
This bit indicates when the USB Endpoint 2 Mailbox registers have been read by the USB
host. Writing a 1 clears this bit.
Endpoint 1 Interrupt Status (Receive Mailbox Valid).
This bit indicates when the USB Endpoint 1 Mailbox registers have been written to by the
USB host. Writing a 1 clears this bit.
Upper Interrupt Active (read only).
At least one interrupt status bit is set in register REG[4008h].
Hardware Functional Specification
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Interrupt Enable Register 1
REG[4006h]
Default = 00h
Read/Write
n/a
15
14
6
13
12
4
11
3
10
2
9
8
Transmit FIFO
Almost Empty
Interrupt Enable
Receive FIFO
Almost Full
Interrupt Enable
n/a
7
5
1
0
bit 1
Transmit FIFO Almost Empty Interrupt Enable.
When set, this bit enables an interrupt to be generated when the Transmit FIFO Almost
Empty status bit is set.
Note
The Transmit FIFO Almost Empty threshold must be set greater than zero, as the FIFO
count must drop below the threshold to cause an interrupt.
bit 0
Receive FIFO Almost Full Interrupt Enable.
When set, this bit enables an interrupt to be generated when the Receive FIFO Almost Full
status bit is set.
Note
The Receive FIFO Almost Full threshold must be set less than 64, as the FIFO count
must rise above the threshold to cause an interrupt.
Interrupt Status Register 1
REG[4008h]
Default = 00h
Read/Write
n/a
15
14
6
13
12
4
11
3
10
2
9
8
Transmit FIFO
Almost Empty
Status
Receive FIFO
Almost Full Status
n/a
7
5
1
0
bit 1
Transmit FIFO Almost Empty Status.
This bit is set when the number of bytes in the Transmit FIFO is equal to the Transmit
FIFO Almost Empty Threshold, and another byte is sent to the USB bus from the FIFO.
Writing a 1 clears this bit.
bit 0
Receive FIFO Almost Full Status.
This bit is set when the number of bytes in the Receive FIFO is equal to the Receive FIFO
Almost Full Threshold, and another byte is received from the USB bus into the FIFO.
Writing a 1 clears this bit.
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Endpoint 1 Index Register
REG[4010h]
Default = 00h
Read/Write
n/a
15
14
6
13
12
4
11
3
10
2
9
8
0
n/a
Endpoint 1 Index bits 2-0 (RO)
7
5
1
bits 2-0
Endpoint 1 Index Register Bits [2:0].
This register determines which Endpoint 1 Receive Mailbox is accessed when the End-
point 1 Receive Mailbox Data register is read. This register is automatically incremented
after the Endpoint 1 Receive Mailbox Data register is read. This index register wraps
around to zero when it reaches the maximum count (7).
Endpoint 1 Receive Mailbox Data Register
REG[4012h]
Default = 00h
Read Only
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Endpoint 1 Receive Mailbox Data bits 7-0
7
5
4
3
bits 7-0
Endpoint 1 Receive Mailbox Data Bits [7:0].
This register is used to read data from one of the receive mailbox registers. Data is
returned from the register selected by the Endpoint 1 Index Register. The eight receive
mailbox registers are written by a USB bulk transfer to endpoint 1, and can be used to pass
messages from the USB host to the local CPU. The format and content of the messages are
user defined. If enabled, USB writes to this register can generate an interrupt.
Endpoint 2 Index Register
REG[4018h]
Default = 00h
Read/Write
n/a
15
14
6
13
12
4
11
3
10
2
9
8
0
n/a
Endpoint 2 Index bits 2-0
7
5
1
bits 2-0
Endpoint 2 Index Register Bits [2:0].
This register determines which Endpoint 2 Transmit Mailbox is accessed when the End-
point 2 Transmit Mailbox Data register is read or written. This register is automatically
incremented after the Endpoint 2 Transmit Mailbox Data port is read or written. This
index register wraps around to zero when it reaches the maximum count (7).
Hardware Functional Specification
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Endpoint 2 Transmit Mailbox Data Register
REG[401Ah]
Default = 00h
Read/Write
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Endpoint 2 Transmit Mailbox Data bits 7-0
7
5
4
3
bits 7-0
Endpoint 2 Transmit Mailbox Data Bits [7:0].
This register is used to read or write one of the transmit mailbox registers. The register
being accessed is selected by the Endpoint 2 Index register. The eight Transmit Mailbox
registers are written by the local CPU and are read by a USB transfer from endpoint 2. The
format and content of the messages are user defined. If enabled, USB reads from this reg-
ister can generate an interrupt.
Endpoint 2 Interrupt Polling Interval Register
REG[401Ch]
Default = FFh
Read/Write
n/a
15
14
6
13
5
12
11
10
2
9
1
8
0
Interrupt Polling Interval bits 7-0
7
4
3
bits 7-0
Interrupt Polling Interval Bits [7:0].
This register specifies the Endpoint 2 interrupt polling interval in milliseconds. It can be
read by the host through the endpoint 2 descriptor.
Endpoint 3 Receive FIFO Data Register
REG[4020h]
Default = 00h
Read Only
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Endpoint 3 Receive FIFO Data bits 7-0
7
5
4
3
bits7-0
Endpoint 3 Receive FIFO Data Bits [7:0].
This register is used by the local CPU to read USB receive FIFO data. The FIFO data is
written by the USB host using bulk or isochronous transfers to endpoint 3.
Endpoint 3 Receive FIFO Count Register
REG[4022h]
Default = 00h
Read Only
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Receive FIFO Count bits 7-0
7
5
4
3
bits 7-0
Receive FIFO Count Bits [7:0].
This register returns the number of receive FIFO entries containing valid entries. Values
range from 0 (empty) to 64 (full). This register is automatically decremented after every
read of the of the Receive FIFO Data Register (REG[4020h]).
S1D13A05
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Endpoint 3 Receive FIFO Status Register
REG[4024h]
Default = 01h
Read/Write
n/a
15
14
13
12
11
10
9
8
Receive FIFO
Empty
(read only)
Receive FIFO
Flush
Receive FIFO
Overflow
Receive FIFO
Underflow
Receive FIFO Full
(read only)
n/a
7
6
5
4
3
2
1
0
bit 4
Receive FIFO Flush.
Writing to this bit causes the receive FIFO to be flushed. Reading this bit always returns a
0.
bit 3
bit 2
Receive FIFO Overflow.
If set, this bit indicates that an attempt was made by the USB host to write to the receive
FIFO when the receive FIFO was full. Writing a 1 clears this bit.
Receive FIFO Underflow.
If set, this bit indicates that an attempt was made to read the receive FIFO when the
receive FIFO was empty. Writing a 1 clears this bit.
bit 1
bit 0
Receive FIFO Full.
If set, this bit indicates that the receive FIFO is full.
Receive FIFO Empty.
If set, this bit indicates that the receive FIFO is empty.
Endpoint 3 Maximum Packet Size Register
REG[4026h]
Default = 08h
Read/Write
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Endpoint 3 Max Packet Size bits 7-0
7
5
4
3
bits 7-0
Endpoint 3 Max Packet Size Bits [7:0].
This register specifies the maximum packet size for endpoint 3 in units of 8 bytes (default
= 64 bytes). It can be read by the host through the endpoint 3 descriptor.
Endpoint 4 Transmit FIFO Data Register
REG[4028h]
Default = 00h
Write Only
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Transmit FIFO Data bits 7-0
7
5
4
3
bits 7-0
Transmit FIFO Data Bits [7:0].
This register is used by the local CPU to write data to the transmit FIFO. The FIFO data is
read by the USB host using bulk or isochronous transfers from endpoint 4.
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Endpoint 4 Transmit FIFO Count Register
REG[402Ah]
Default = 00h
Read Only
n/a
15
14
6
13
5
12
11
10
2
9
1
8
0
Transmit FIFO Count bits 7-0
7
4
3
bits 7-0
Transmit FIFO Count Bits [7:0].
This register returns the number of transmit FIFO entries containing valid entries. Values
range from 0 (empty) to 64 (full).
Endpoint 4 Transmit FIFO Status Register
REG[402Ch]
Default = 01h
Read/Write
n/a
15
14
6
13
12
11
10
9
8
Transmit FIFO
Valid
Transmit FIFO
Flush
Transmit FIFO
Overflow
Transmit FIFO
Full (read only)
Transmit FIFO
Empty (read only)
n/a
Reserved
7
5
4
3
2
1
0
bit 5
Transmit FIFO Valid.
If set, this bit allows the data in the Transmit FIFO to be read by the next read from the
host. This bit is automatically cleared by a host read. This bit is only used if bit 0 in
USB[403Ah] Index [0Ch] is set.
bit 4
bit 3
Transmit FIFO Flush.
Writing to this bit causes the transmit FIFO to be flushed. Reading this bit always returns
a 0.
Transmit FIFO Overflow.
If set, this bit indicates that an attempt was made by the local CPU to write to the transmit
FIFO when the transmit FIFO was full. Writing a 1 clears this bit.
bit 2
bit 1
Reserved.
Transmit FIFO Full (read only).
If set, this bit indicates that the transmit FIFO is full.
bit 0
Transmit FIFO Empty (read only).
If set, this bit indicates that the transmit FIFO is empty.
Endpoint 4 Maximum Packet Size Register
REG[402Eh]
Default = 08h
Read/Write
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Endpoint 4 Max Packet Size bits 7-0
7
5
4
3
bits 7-0
Endpoint 4 Max Packet Size Bits [7:0].
This register specifies the maximum packet size for endpoint 4 in units of 8 bytes (default
= 64 bytes). It can be read by the host through the endpoint 4 descriptor.
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Revision Register
REG[4030h]
Default = 01h
Read Only
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Chip Revision bits 7-0
7
5
4
3
bits 7-0
Chip Revision Bits [7:0].
This register returns current silicon revision number of the USB client.
USB Status Register
REG[4032h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
USB Endpoint 4
STALL
USB Endpoint 4
NAK
USB Endpoint 4
ACK
USB Endpoint 3
STALL
USB Endpoint 3
NAK
USB Endpoint 3
ACK
Suspend Control
Endpoint 2 Valid
7
6
5
4
3
2
1
0
bit 7
Suspend Control
If set, this bit indicates that there is a pending suspend request. Writing a 1 clears this bit
and causes the S1D13A05 USB device to enter suspended mode.
bit 6
bit 5
bit 4
bit 3
USB Endpoint 4 STALL
The last USB IN token could not be serviced because the endpoint was stalled
(REG[4000h] bit 4 set), and was acknowledged with a STALL. Writing a 1 clears this bit.
USB Endpoint 4 NAK
The last USB packet transmitted (IN packet) encountered a FIFO underrun condition, and
was acknowledged with a NAK. Writing a 1 clears this bit.
USB Endpoint 4 ACK
The last USB packet transmitted (IN packet) was successfully acknowledged with an
ACK from the USB host. Writing a 1 clears this bit.
USB Endpoint 3 STALL
The last USB packet received (OUT packet) could not be accepted because the endpoint
was stalled (REG[4000h] bit 3 set), and was acknowledged with a STALL. Writing a 1
clears this bit.
bit 2
bit 1
bit 0
USB Endpoint 3 NAK
The last USB packet received (OUT packet) could not be accepted, and was acknowl-
edged with a NAK. Writing a 1 clears this bit.
USB Endpoint 3 ACK.
The last USB packet received (OUT packet) was successfully acknowledged with an
ACK. Writing a 1 clears this bit.
Endpoint 2 Valid.
When this bit is set, the 8-byte endpoint 2 mailbox registers have been written by the local
CPU, but not yet read by the USB host. The local CPU should not write into these regis-
ters while this bit is set.
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Frame Counter MSB Register
REG[4034h]
Default = 00h
Read Only
n/a
15
7
14
6
13
12
4
11
3
10
2
9
8
0
n/a
Frame Counter bits 10-8
5
1
Frame Counter LSB Register
REG[4036h]
Default = 00h
Read Only
n/a
15
14
6
13
5
12
11
10
2
9
1
8
0
Frame Counter bits 7-0
7
4
3
bits 10-0
Frame Counter Bits [10:0]
This register contains the frame counter from the most recent start-of-frame packet.
Extended Register Index
REG[4038h]
Default = 00h
Read/Write
n/a
15
14
6
13
5
12
11
10
2
9
1
8
0
Extended Register Index bits 7-0
7
4
3
bits 7-0
Extended Register Index Bits [7:0]
This register selects which extended data register is accessed when the REG[403Ah] is
read or written.
Extended Register Data
REG[403Ah]
Default = 04h
Read/Write
n/a
15
14
6
13
12
11
10
2
9
1
8
0
Extended Data bits 7-0
7
5
4
3
bits 7-0
Extended Data Bits [7:0]
This port provides access to one of the extended data registers. The index of the current
register is held in REG[4038h].
S1D13A05
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Vendor ID MSB
REG[403Ah], Index[00h]
Default = 04h
Read/Write
Vendor ID bits 15-8
7
6
5
4
3
2
2
1
1
0
Vendor ID LSB
REG[403Ah], Index[01h]
Default = B8h
Read/Write
Vendor ID bits 7-0
7
6
5
4
3
0
bits 15-0
Vendor ID Bits [15:0]
These registers determine the Vendor ID returned in a “Get Device Descriptor” request.
Product ID MSB
REG[403Ah], Index[02h]
Default = 88h
Read/Write
Product ID bits 15-8
7
6
5
4
3
2
1
0
Product ID LSB
REG[403Ah], Index[03h]
Default = 21h
Read/Write
Product ID bits 7-0
7
6
5
4
3
2
1
0
bits 15-0
Product ID Bits [15:0]
These registers determine the Product ID returned in a “Get Device Descriptor” request.
Release Number MSB
REG[403Ah], Index[04h]
Default = 01h
Read/Write
Release Number bits 15-8
7
6
5
4
3
2
1
0
Release Number LSB
REG[403Ah], Index[05h]
Default = 00h
Read/Write
Release Number bits 7-0
7
6
5
4
3
2
1
0
bits 15-0
Release Number Bits [15:0]
These registers determine the device release number returned in a “Get Device Descrip-
tor” request.
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Receive FIFO Almost Full Threshold
REG[403Ah], Index[06h]
Default = 3Ch
Read/Write
n/a
Receive FIFO Almost Full Threshold bits 5-0
7
6
5
4
3
2
1
0
bits 5-0
Receive FIFO Almost Full Threshold Bits [5:0]
This register determines the threshold at which the receive FIFO almost full status bit is
set.
Note
The Receive FIFO Almost Full threshold must be set less than 64, as the FIFO count
must rise above the threshold to cause an interrupt.
Transmit FIFO Almost Empty Threshold
REG[403Ah], Index[07h]
Default = 04h
Read/Write
n/a
Transmit FIFO Almost Empty Threshold bits 5-0
7
6
5
4
3
2
1
0
bits 5-0
Transmit FIFO Almost Empty Threshold Bits [5:0].
This register determines the threshold at which the transmit FIFO almost empty status bit
is set.
Note
The Transmit FIFO Almost Empty threshold must be set greater than zero, as the FIFO
count must drop below the threshold to cause an interrupt.
USB Control
REG[403Ah], Index[08h]
Default = 01h
Read/Write
USB String
Enable
n/a
4
7
6
5
3
2
1
0
bit 0
USB String Enable.
When set, this bit allows the default Vendor and Product ID String Descriptors to be
returned to the host. When this bit is cleared, the string index values in the Device
Descriptor are set to zero.
Maximum Power Consumption
REG[403Ah], Index[09h]
Default = FAh
Read/Write
Maximum Current bits 7-0
7
6
5
4
3
2
1
0
bits 7-0
Maximum Current Bits [7:0].
The amount of current drawn by the peripheral from the USB port in increments of 2 mA.
The S1D13A05 reports this value to the host controller in the configuration descriptor.
The default and maximum value is 500 mA (FAh * 2 mA).
In order to comply with the USB specification the following formula must apply:
REG[403Ah] index[09h]
≤
FAh.
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Packet Control
REG[403Ah], Index[0Ah]
Default = 00h
Read/Write
EP4 Data Toggle EP3 Data Toggle EP2 Data Toggle EP1 Data Toggle
Reserved
3
Reserved
2
n/a
1
Reserved
7
6
5
4
0
bit 7
bit 6
bit 5
bit 4
EP4 Data Toggle Bit.
Contains the value of the Data Toggle bit to be sent in response to the next IN token to
endpoint 4 from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
EP3 Data Toggle Bit.
Contains the value of the Data Toggle bit expected in the next DATA packet to endpoint 3
from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
EP2 Data Toggle Bit.
Contains the value of the Data Toggle bit to be sent in response to the next IN token to
endpoint 2 from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
EP1 Data Toggle Bit.
Contains the value of the Data Toggle bit expected in the next DATA packet to endpoint 1
from the USB host.
Note
When a write is made to this bit, the value cannot be read back before a minimum of 12
USBCLK.
bit 3
bit 2
bit 0
Reserved.
This bit must be set to 0.
Reserved.
This bit must be set to 0.
Reserved.
This bit must be set to 0.
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Reserved
REG[403Ah], Index[0Bh]
Default = 00h
Read/Write
n/a
4
Reserved
7
6
5
3
2
1
0
bit 0
Reserved.
This bit must be set to 0.
FIFO Control
REG[403Ah], Index[0Ch]
Default = 00h
Read/Write
Transmit FIFO
Valid Mode
n/a
7
6
5
4
3
2
1
0
bit 0
Transmit FIFO Valid Mode.
When set, this bit causes a NAK response to a host read request from the transmit FIFO
(EP4) unless the FIFO Valid bit (in register EP4STAT) is set. When this bit is cleared, any
data waiting in the transmit FIFO will be sent in response to a host read request, and the
FIFO Valid bit is ignored.
USBFC Input Control Register
REG[4040h]
Default = 0Dh
Read/Write
n/a
15
14
13
12
11
10
9
8
n/a
USCMPEN
Reserved
Reserved
ISO
WAKEUP
Reserved
Reserved
7
6
5
4
3
2
1
0
These bits control inputs to the USB module.
USCMPEN
bit 6
This bit controls the USB differential input receiver.
0 = differential input receiver disabled
1 = differential input receiver enabled
bits 5
bits 4
bit 3
Reserved.
This bit must be set to 0.
Reserved.
This bit must be set to 0.
ISO
This bits selects between isochronous and bulk transfer modes for the FIFOs (Endpoint 3
and Endpoint 4).
0 = Isochronous transfer mode
1 = Bulk transfer mode
bit 2
WAKEUP
This active low bit initiates a USB remote wake-up.
0 = initiate USB remote wake-up
1 = no action
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bit 1
bit 0
Reserved.
This bit must be set to 0.
Reserved.
This bit must be set to 0.
Reserved
REG[4042h]
n/a
n/a
15
7
14
6
13
5
12
11
3
10
2
9
1
8
4
0
Pin Input Status / Pin Output Data Register
REG[4044h]
Default = depends on USB input pin state
Read/Write
n/a
15
14
6
13
12
11
10
2
9
8
USBDETECT
Input Pin Status
(read only)
USBPUP Output
Pin Status
n/a
7
5
4
3
1
0
These bits can generate interrupts.
USBDETECT Input Pin Status
bit 1
This read-only bit indicates the status of the USBDETECT input pin after a steady-state
period of 0.5 seconds.
bit 0
USBPUP Output Pin Status
This bit controls the state of the USBPUP output pin.
This bit must be set to 1 to enable the USB interface and USB registers. See the S1D13A05
Programming Notes and Examples, document number X40-A-G-003-xx for further infor-
mation on this bit.
Interrupt Control Enable Register 0
REG[4046h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
USB Host
Connected
n/a
Reserved
Reserved
Reserved
Reserved
USBRESET
Reserved
7
6
5
4
3
2
1
0
These bits enable interrupts from the corresponding bit of the Interrupt Control Status/Clear
Register 0.
0 = corresponding interrupt bit disabled (masked).
1 = corresponding interrupt bit enabled.
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Interrupt Control Enable Register 1
REG[4048h]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
USB Host
Disconnect
Device
Configured
n/a
Reserved
5
Reserved
Reserved
Reserved
INT
7
6
4
3
2
1
0
These bits enable interrupts from the corresponding bit of the Interrupt Control Status/Clear
Register 1.
0 = corresponding interrupt bit disabled (masked).
1 = corresponding interrupt bit enabled.
Interrupt Control Status/Clear Register 0
REG[404Ah]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
USB Host
Connected
n/a
Reserved
5
Reserved
Reserved
Reserved
USBRESET
Reserved
7
6
4
3
2
1
0
On reads, these bits represent the interrupt status for interrupts caused by low-to-high
transitions on the corresponding signals.
0 (read) = no low-to-high event detected on the corresponding signal.
1 (read) = low-to-high event detected on the corresponding signal.
On writes, these bits clear the corresponding interrupt status bit.
0 (write) = corresponding interrupt status bit unchanged.
1 (write) = corresponding interrupt status bit cleared to zero.
These bits must always be cleared via a write to this register before first use. This will
ensure that any changes on input pins during system initialization do not generate erroneous
interrupts. The interrupt bits are used as follows.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
USB Host Connected
Indicates the USB device is connected to a USB host.
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
USBRESET
Indicates the USB device is reset using the RESET# pin or using the USB port reset.
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bit 0
Reserved.
Must be set to 0.
Interrupt Control Status/Clear Register 1
REG[404Ch]
Default = 00h
Read/Write
n/a
15
14
13
12
11
10
9
8
USB Host
Disconnected
Device
Configured
n/a
Reserved
Reserved
Reserved
Reserved
INT
7
6
5
4
3
2
1
0
On reads, these bits represent the interrupt status for interrupts caused by high-to-low
transitions on the corresponding signals.
0 (read) = no high-to-low event detected on the corresponding signal.
1 (read) = high-to-low event detected on the corresponding signal.
On writes, these bits clear the corresponding interrupt status bit.
0 (write) = corresponding interrupt status bit unchanged.
1 (write) = corresponding interrupt status bit cleared to zero.
These bits must always be cleared via a write to this register before first use. This will
ensure that any changes on input pins during system initialization do not generate erroneous
interrupts. The interrupt bits are used as follows.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
USB Host Disconnected
Indicates the USB device is disconnected from a USB host.
Reserved.
Must be set to 0.
Device Configured.
Indicates the USB device has been configured by the USB host.
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
Reserved.
Must be set to 0.
INT
Indicates an interrupt request originating from within the USB registers (REG[4000h] to
REG[403Ah]).
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Interrupt Control Masked Status Register 0
REG[404Eh]
Default = 00h
Read Only
n/a
15
14
13
12
11
10
9
8
USB Host
Connected
n/a
Reserved
Reserved
Reserved
Reserved
USBRESET
Reserved
7
6
5
4
3
2
1
0
These read-only bits represent the logical AND of the corresponding Interrupt Control
Status/Clear Register 0 (REG[404Ah])and the Interrupt Control Enable Register 0
(REG[4046h]).
Interrupt Control Masked Status Register 1
REG[4050h]
Default = 00h
Read Only
n/a
15
14
13
12
11
10
9
8
USB Host
Disconnected
Device
Configured
n/a
Reserved
Reserved
Reserved
Reserved
INT
7
6
5
4
3
2
1
0
These read-only bits represent the logical AND of the corresponding Interrupt Control
Status/Clear Register 1 (REG[404Ch]) and the Interrupt Control Enable Register 1
(REG[4048h]).
USB Software Reset Register
REG[4052h]
Default = 00h
Write Only
n/a
15
14
6
13
5
12
11
10
2
9
1
8
0
USB Software Reset (Code = 10100100) bits 7-0
7
4
3
bits 7-0
USB Software Reset Bits [7:0] (Write Only)
When the specific code of 10100100b is written to these bits the USB module of the
S1D13A05 is reset. Use of the above code avoids the possibility of accidently resetting the
USB.
USB Wait State Register
REG[4054h]
Default = 00h
Read/Write
n/a
15
14
6
13
5
12
4
11
3
10
2
9
8
n/a
USB Wait State bits 1-0
7
1
0
bits 1-0
USB Wait State Bits [1:0]
This register controls the number of wait states the S1D13A05 uses for its internal USB
support. For all bus interfaces supported by the S1D13A05 these bits must be set to 01.
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8.5 2D Acceleration (BitBLT) Registers (Offset = 8000h)
These registers control the S1D13A05 2D Acceleration engine. For detailed BitBLT
programming instructions, see the S1D13A05 Programming Notes and Examples,
document number X40A-G-003-xx.
BitBLT Control Register
REG[8000h] Default = 00000000h
Read/Write
Color
Format
Select
Dest
Linear
Select
Source
Linear
Select
n/a
25
31
30
14
29
13
28
27
26
24
23
7
22
6
21
5
20
4
19
3
18
17
1
16
BitBLT
Enable
(WO)
n/a
15
12
11
10
9
8
2
0
bit 18
BitBLT Color Format Select
This bit selects the color format that the 2D operation is applied to.
When this bit = 0, 8 bpp (256 color) format is selected.
When this bit = 1, 16 bpp (64K color) format is selected.
bit 17
BitBLT Destination Linear Select
When this bit = 1, the Destination BitBLT is stored as a contiguous linear block of
memory.
When this bit = 0, the Destination BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset register (REG[8014h]) determines the address offset
from the start of one line to the next line.
bit 16
bit 0
BitBLT Source Linear Select
When this bit = 1, the Source BitBLT is stored as a contiguous linear block of memory.
When this bit = 0, the Source BitBLT is stored as a rectangular region of memory.
The BitBLT Memory Address Offset register (REG[8014h]) determines the address offset
from the start of one line to the next line.
BitBLT Enable
This bit is write only.
Setting this bit to 1 begins the 2D BitBLT operation. This bit must not be set to 0 while a
BitBLT operation is in progress.
Note
To determine the status of a BitBLT operation use the BitBLT Busy Status bit
(REG[8004h] bit 0).
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BitBLT Status Register
REG[8004h]
Default = 00000000h
Read Only
n/a
Number of Used FIFO Entries
n/a
22
Number of Free FIFO Entries (0 means full)
31
30
29
13
28
27
26
25
24
8
23
7
21
20
19
18
17
16
FIFO
Not
Empty
FIFO
Full
Status
BitBLT
Busy
Status
FIFO
Half Full
n/a
n/a
15
14
12
11
10
9
6
5
4
3
2
1
0
bits 28-24
bits 20-16
bit 6
Number of Used FIFO Entries Bits [4:0]
These bits indicate the minimum number of FIFO entries currently in use (there may be
more values in internal pipeline stages).
Number of Free FIFO Entries Bits [4:0]
These bits indicate the number of empty FIFO entries available. If these bits return a 0, the
FIFO is full.
BitBLT FIFO Not-Empty Status
This is a read-only status bit.
When this bit = 0, the BitBLT FIFO is empty.
When this bit = 1, the BitBLT FiFO has at least one data.
To reduce system memory read latency, software can monitor this bit prior to a BitBLT
read burst operation.
The following table shows the number of words available in BitBLT FIFO under different
status conditions.
Table 8-34: BitBLT FIFO Words Available
BitBLT FIFO Full
Status
(REG[8004h] Bit 4) (REG[8004h] Bit 5) (REG[8004h] Bit 6)
BitBLT FIFO Half
Full Status
BitBLT FIFO Not Number of Words
Empty Status
available in BitBLT
FIFO
0
0
0
1
0
0
1
1
0
1
1
1
0
1 to 6
7 to 14
15 to 16
bit 5
bit 4
BitBLT FIFO Half Full Status
This is a read-only status bit.
When this bit = 1, the BitBLT FIFO is half full or greater than half full.
When this bit = 0, the BitBLT FIFO is less than half full.
BitBLT FIFO Full Status
This is a read-only status bit.
When this bit = 1, the BitBLT FIFO is full.
When this bit = 0, the BitBLT FIFO is not full.
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bit 0
BitBLT Busy Status
This bit is a read-only status bit.
When this bit = 1, the BitBLT operation is in progress.
When this bit = 0, the BitBLT operation is complete.
Note
During a BitBLT Read operation, the BitBLT engine does not attempt to keep the FIFO
full. If the FIFO becomes full, the BitBLT operation stops temporarily as data is read
out of the FIFO. The BitBLT will restart only when less than 14 values remain in the
FIFO.
BitBLT Command Register
REG[8008h] Default = 00000000h
Read/Write
n/a
BitBLT ROP Code bits 3-0
31
15
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
5
20
4
19
3
18
17
16
0
n/a
BitBLT Operation bits 3-0
2
1
bits 19-16
BitBLT Raster Operation Code/Color Expansion Bits [3:0]
ROP Code for Write BitBLT and Move BitBLT. Bits 2-0 also specify the start bit position
for Color Expansion.
Table 8-35 : BitBLT ROP Code/Color Expansion Function Selection
BitBLT ROP Code Bits Boolean Function for Write
Boolean Function for
Pattern Fill
Start Bit Position for Color
Expansion
[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BitBLT and Move BitBLT
0 (Blackness)
0 (Blackness)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
~S . ~D or ~(S + D)
~P . ~D or ~(P + D)
~S . D
~P . D
~S
~P
S . ~D
P . ~D
~D
~D
S ^ D
P ^ D
~S + ~D or ~(S . D)
~P + ~D or ~(P . D)
S . D
P . D
~(S ^ D)
D
~(P ^ D)
D
~S + D
S
~P + D
P
S + ~D
S + D
1 (Whiteness)
P + ~D
P + D
1 (Whiteness)
Note
S = Source, D = Destination, P = Pattern.
~ = NOT, . = Logical AND, + = Logical OR, ^ = Logical XOR
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bits 3-0
BitBLT Operation Bits [3:0]
Specifies the 2D Operation to be carried out based on the following table.
Table 8-36 : BitBLT Operation Selection
BitBLT Operation Bits [3:0]
BitBLT Operation
Write BitBLT with ROP.
0000
0001
Read BitBLT.
0010
Move BitBLT in positive direction with ROP.
Move BitBLT in negative direction with ROP.
Transparent Write BitBLT.
0011
0100
0101
Transparent Move BitBLT in positive direction.
Pattern Fill with ROP.
0110
0111
Pattern Fill with transparency.
Color Expansion.
1000
1001
Color Expansion with transparency.
Move BitBLT with Color Expansion.
Move BitBLT with Color Expansion and transparency.
Solid Fill.
1010
1011
1100
Other combinations
Reserved
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BitBLT Source Start Address Register
REG[800Ch]
Default = 00000000h
Read/Write
n/a
BitBLT Source Start Address bits 20-16
31
30
14
29
13
28
12
27
11
26
10
25
24
23
22
21
5
20
19
18
17
1
16
0
BitBLT Source Start Address bits 15-0
15
9
8
7
6
4
3
2
bits 20-0
BitBLT Source Start Address Bits [20:0]
A 21-bit register that specifies the source start address for the BitBLT operation.
If data is sourced from the CPU, then bit 0 is used for byte alignment within a 16-bit word
and the other address bits are ignored. In pattern fill operation, the BitBLT Source Start
Address is defined by the following equation.
Value programmed to the Source Start Address Register =
Pattern Base Address + Pattern Line Offset + Pixel Offset.
The following table shows how Source Start Address Register is defined for 8 and 16 bpp
color depths.
Table 8-37 : BitBLT Source Start Address Selection
Color Format
Pattern Base Address[20:0]
Pattern Line Offset[2:0]
Pixel Offset[3:0]
BitBLT Source Start
Address[5:3]
BitBLT Source Start
Address[2:0]
8 bpp
BitBLT Source Start Address[20:6]
BitBLT Source Start
Address[6:4]
BitBLT Source Start
Address[3:0]
16 bpp
BitBLT Source Start Address[20:7]
Note
For further information on the BitBLT Source Start Address register, see the S1D13A05
Programming Notes and Examples, document number X40A-G-003-xx.
BitBLT Destination Start Address Register
REG[8010h]
Default = 00000000h
Read/Write
n/a
BitBLT Destination Start Address bits 20-16
31
30
14
29
13
28
12
27
11
26
10
25
24
23
22
21
5
20
19
18
17
1
16
0
BitBLT Destination Start Address bits 15-0
15
9
8
7
6
4
3
2
bits 20-0
BitBLT Destination Start Address Bits [20:0]
A 21-bit register that specifies the destination start address for the BitBLT operation.
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BitBLT Memory Address Offset Register
REG[8014h]
Default = 00000000h
Read/Write
n/a
31
30
14
29
28
12
27
11
26
10
25
9
24
8
23
22
21
20
19
18
2
17
1
16
0
n/a
BitBLT Memory Address Offset bits 10-0
15
13
7
6
5
4
3
bits 10-0
BitBLT Memory Address Offset Bits [10:0]
These bits are the display’s 11-bit address offset from the starting word of line n to the
starting word of line n + 1. They are used only for address calculation when the BitBLT is
configured as a rectangular region of memory. They are not used for the displays.
BitBLT Width Register
REG[8018h] Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
20
19
3
18
2
17
1
16
0
n/a
BitBLT Width bits 9-0
15
5
4
bits 9-0
BitBLT Width Bits [9:0]
A 10-bit register that specifies the BitBLT width in pixels - 1.
BitBLT width in pixels = (REG[8018h] bits 9-0) + 1
BitBLT Height Register
REG[801Ch] Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
11
26
10
25
9
24
8
23
7
22
6
21
20
19
3
18
2
17
1
16
0
n/a
BitBLT Height bits 9-0
15
5
4
bits 9-0
BitBLT Height Bits [9:0]
A 10-bit register that specifies the BitBLT height in lines - 1.
BitBLT height in lines = (REG[801Ch] bits 9-0) + 1
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BitBLT Background Color Register
REG[8020h]
Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
11
26
10
25
24
23
22
21
5
20
4
19
3
18
2
17
1
16
0
BitBLT Background Color bits 15-0
15
9
8
7
6
bits 15-0
BitBLT Background Color Bits [15:0]
This register specifies the BitBLT background color for Color Expansion or key color for
Transparent BitBLT. For 16 bpp color depths (REG[8000h] bit 18 = 1), bits 15-0 are used.
For 8 bpp color depths (REG[8000h] bit 18 = 0), bits 7-0 are used.
BitBLT Foreground Color Register
REG[8024h] Default = 00000000h
Read/Write
n/a
31
30
14
29
13
28
12
27
11
26
10
25
24
23
22
21
5
20
4
19
3
18
2
17
1
16
0
BitBLT Foreground Color bits 15-0
15
9
8
7
6
bits 15-0
BitBLT Foreground Color Bits [15:0]
This register specifies the BitBLT foreground color for Color Expansion or Solid Fill. For
16 bpp color depths (REG[8000h] bit 18 = 1), bits 15-0 are used. For 8 bpp color depths
(REG[8000h] bit 18 = 0), bits 7-0 are used.
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8.6 2D Accelerator (BitBLT) Data Register Descriptions
The 2D Accelerator (BitBLT) data registers decode AB15-AB0 and require AB16 = 1. The
BitBLT data registers are 32-bit wide. Byte access to the BitBLT data registers is not
allowed.
2D Accelerator (BitBLT) Data Memory Mapped Region Register
AB16-AB0 = 10000h-1FFFEh, even addresses
Read/Write
BitBLT Data bits 31-16
24 23
BitBLT Data bits 15-0
31
15
30
14
29
13
28
12
27
11
26
10
25
9
22
6
21
5
20
4
19
3
18
2
17
1
16
0
8
7
bits 15-0
BitBLT Data Bits [15:0]
This register specifies the BitBLT data. This register is loosely decoded from 10000h to
1FFFEh.
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9 2D Accelerator (BitBLT) Engine
9.1 Overview
The S1D13A05 is designed with a built-in 2D BitBLT engine which increases the perfor-
mance of Bit Block Transfers (BitBLT). It supports 8 and 16 bit-per-pixel color depths.
The BitBLT engine supports rectangular and linear addressing modes for source and desti-
nation in a positive direction for all BitBLT operations except the move BitBLT which also
supports in a negative direction.
The BitBLT operations support byte alignment of all types. The BitBLT engine has a
dedicated BitBLT IO access space. This allows the BitBLT engine to support simultaneous
BitBLT and host side operations.
9.2 BitBLT Operations
The S1D13A05 2D BitBLT engine supports the following BitBLTs. For detailed infor-
mation on using the individual BitBLT operations, refer to the S1D13A05 Programming
Notes and Examples, document number X40A-G-003-xx.
• Write BitBLT.
• Move BitBLT.
• Solid Fill BitBLT.
• Pattern Fill BitBLT.
• Transparent Write BitBLT.
• Transparent Move BitBLT.
• Read BitBLT.
• Color Expansion BitBLT.
• Move BitBLT with Color Expansion.
Note
For details on the BitBLT registers, see Section 8.5, “2D Acceleration (BitBLT) Regis-
ters (Offset = 8000h)” on page 153.
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10 Frame Rate Calculation
The following formula is used to calculate the display frame rate.
fPCLK
FrameRate = --------------------------------
(HT) × (VT)
Where:
fPCLK = PClk frequency (Hz)
HT
VT
= Horizontal Total
= ((REG[20h] bits 6-0) + 1) x 8 Pixels
= Vertical Total
= ((REG[30h] bits 9-0) + 1) Lines
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11 Display Data Formats
The following diagrams show the display mode data formats for a little-endian system.
1 bpp:
Byte 0
bit 7
bit 0
P P P P
P P P P
7
0
1
2
3
4
5
6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
10
18
11
19
12
20
13
21
14
22
15
23
Byte 1
Byte 2
LUT
LUT
LUT
P
= RGB value from LUT
n
Index (A )
n
16
17
Host Address
Panel Display
Display Memory
2 bpp:
bit 7
bit 0
P P P P
P P P P
3
4
0
1
2
5
6
7
A
A
A
B
B
B
A
A
A
B
B
B
A
A
A
B
B
B
A
A
A
B
B
B
0
4
8
0
4
8
1
5
9
1
5
9
2
2
3
3
Byte 0
Byte 1
Byte 2
6
6
7
7
P
= RGB value from LUT
Index (A , B )
n
10
10
11
11
n
n
Host Address
Display Memory
Panel Display
4 bpp:
bit 7
bit 0
P P P P
P P P P
3
4
0
1
2
7
5
6
A
A
A
B
B
B
C
C
C
D
D
D
A
A
A
B
B
B
C
C
C
D
D
D
0
2
4
0
2
4
0
2
4
0
2
4
1
3
5
1
3
5
1
3
5
1
3
5
Byte 0
Byte 1
Byte 2
P
= RGB value from LUT
Index (A , B , C , D )
n
n
n
n
n
Host Address
8 bpp:
Display Memory
Panel Display
P P P P
P P P P
3
4
bit 7
bit 0
0
1
2
7
5
6
G
F
H
0
B
C
C
C
D
D
D
E
E
E
A
0
Byte 0
Byte 1
Byte 2
0
1
2
0
0
1
2
0
1
2
0
1
2
0
1
2
G
G
LUT
F
H
1
A
1
B
B
1
2
P = RGB value from LUT Index
n
(A , B , C , D , E , F , G , H )
n
n
n
n
n
n
n
n
F
H
2
A
2
Host Address
Display Memory
5-6-5 RGB
Panel Display
16 bpp:
P P P P
P P P P
0
1
2
3
4
5
6
7
bit 7
2
bit 0
0
1
0
4
2
1
3
0
G
0
G
R
B
0
G
R
B
B
B
B
0
Byte 0
Byte 1
Byte 2
Byte 3
0
0
0
0
0
Bypasses LUT
4
3
1
2
5
4
3
4-0
5-0
4-0
R
0
R
B
G
B
G
B
R
B
G
0
P
= (R
, G
, B
n
)
0
0
0
0
0
0
n
n
n
2
1
4
0
2
1
3
0
G
1
G
1
G
B
1
1
1
1
1
1
4
3
2
1
0
5
4
3
R
1
R
R
R
1
R
G
G
G
1
1
1
1
1
1
Panel Display
Host Address
Display Buffer
Figure 11-1: 4/8/16 Bit-Per-Pixel Display Data Memory Organization
Note
1. The Host-to-Display mapping shown here is for a little endian system.
2. For 16 bpp format, R , G , B represent the red, green, and blue color components.
n
n
n
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12 Look-Up Table Architecture
The following figures are intended to show the display data output path only.
Note
When Video Data Invert is enabled the video data is inverted after the Look-Up Table.
12.1 Monochrome Modes
The green Look-Up Table (LUT) is used for all monochrome modes.
1 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
6-bit Gray Data
00
01
00
01
FC
FD
FE
FF
1 bit-per-pixel data
from Display Buffer
= unused Look-Up Table entries
Figure 12-1: 1 Bit-per-pixel Monochrome Mode Data Output Path
2 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
00
01
10
11
6-bit Gray Data
01
02
03
FC
FD
FE
FF
= unused Look-Up Table entries
2 bit-per-pixel data
from Display Buffer
Figure 12-2: 2 Bit-per-pixel Monochrome Mode Data Output Path
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4 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
01
02
03
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Gray Data
FC
FD
FE
FF
4 bit-per-pixel data
from Display Buffer
= unused Look-Up Table entries
Figure 12-3: 4 Bit-per-pixel Monochrome Mode Data Output Path
8 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6
00
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
01
02
03
04
05
06
07
6-bit Gray Data
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
F8
F9
FA
FB
FC
FD
FE
FF
8 bit-per-pixel data
from Display Buffer
Figure 12-4: 8 Bit-per-pixel Monochrome Mode Data Output Path
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16 Bit-Per-Pixel Monochrome Mode
The LUT is bypassed and the green data is directly mapped for this color depth– “Display
Data Formats” on page 163..
12.2 Color Modes
1 Bit-Per-Pixel Color
Red Look-Up Table 256x6
6-bit Red Data
00
0
1
01
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
6-bit Green Data
0
1
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
6-bit Blue Data
0
1
FC
FD
FE
FF
1 bit-per-pixel data
from Image Buffer
= unused Look-Up Table entries
Figure 12-5: 1 Bit-Per-Pixel Color Mode Data Output Path
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2 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
01
02
03
00
01
10
11
6-bit Red Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
00
01
10
11
6-bit Green Data
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
00
01
10
11
6-bit Blue Data
FC
FD
FE
FF
2 bit-per-pixel data
from Image Buffer
= unused Look-Up Table entries
Figure 12-6: 2 Bit-Per-Pixel Color Mode Data Output Path
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4 Bit-Per-Pixel Color
Red Look-Up Table 256x6
00
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Red Data
6-bit Green Data
6-bit Blue Data
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FC
FD
FE
FF
= unused Look-Up Table entries
4 bit-per-pixel data
from Image Buffer
Figure 12-7: 4 Bit-Per-Pixel Color Mode Data Output Path
S1D13A05
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8 Bit-per-pixel Color Mode
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
6-bit Red Data
6-bit Green Data
6-bit Blue Data
F8
F9
FA
FB
FC
FD
FE
FF
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
Green Look-Up Table 256x6
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
00
01
02
03
04
05
06
07
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
F8
F9
FA
FB
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
F8
F9
FA
FB
FC
FD
FE
FF
8 bit-per-pixel data
from Display Buffer
Figure 12-8: 8 Bit-per-pixel Color Mode Data Output Path
16 Bit-Per-Pixel Color Mode
The LUT is bypassed and the color data is directly mapped for this color depth– “Display
Data Formats” on page 163.
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13 SwivelView™
13.1 Concept
Most computer displays are refreshed in landscape orientation – from left to right and top
to bottom. Computer images are stored in the same manner. SwivelView™ is designed to
rotate the displayed image on an LCD by 90°, 180°, or 270° in a counter-clockwise
direction. The rotation is done in hardware and is transparent to the user for all display
buffer reads and writes. By processing the rotation in hardware, SwivelView™ offers a
performance advantage over software rotation of the displayed image.
The image is not actually rotated in the display buffer since there is no address translation
during CPU read/write. The image is rotated during display refresh.
13.2 90° SwivelView™
90° SwivelView™ requires the Memory Clock (MCLK) to be at least 1.25 times the
frequency of the Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK.
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13A05 in the
following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following
sense: B-D-A-C.
physical memory
start address
A
B
SwivelView
window
display start address
(panel origin)
D
C
480
320
image seen by programmer
= image in display buffer
image refreshed by S1D13A05
Figure 13-1: Relationship Between The Screen Image and the Image Refreshed in 90° SwivelView.
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13.2.1 Register Programming
Enable 90° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[10h] bits 17:16) to 01.
Display Start Address
The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start
Address register (REG[40h]) must be programmed with the address of pixel “B”. To
calculate the value of the address of pixel “B” use the following formula (assumes 8 bpp
color depth).
REG[40h] bits 16:0 = ((image address + (panel height x bpp ÷ 8)) ÷ 4) - 1
= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) -1
= 79 (4Fh)
Line Address Offset
The Main Window Line Address Offset register (REG[44h]) is based on the display width
and programmed using the following formula.
REG[44h] bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ 32 ÷ 8 bpp
= 80 (50h)
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13.3 180° SwivelView™
The following figure shows how the programmer sees a 480x320 landscape image and how
the image is being displayed. The application image is written to the S1D13A05 in the
following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following
sense: D-C-B-A.
display start address
(panel origin)
physical memory
start address
C
A
C
B
d o w w i n
SwivelView
e w V i e l i v w S
window
A
D
480
480
image seen by programmer
= image in display buffer
image refreshed by S1D13A05
Figure 13-2: Relationship Between The Screen Image and the Image Refreshed in 180° SwivelView.
13.3.1 Register Programming
Enable 180° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[10h] bits 17:16) to 10.
Display Start Address
The display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start
Address register (REG[40h]) must be programmed with the address of pixel “D”. To
calculate the value of the address of pixel “D” use the following formula (assumes 8 bpp
color depth).
REG[40h] bits 16:0
= ((image address + (offset x (panel height - 1) + panel width) x bpp ÷ 8) ÷ 4) - 1
= ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp ÷ 8) ÷ 4) - 1
= 38399 (95FFh)
S1D13A05
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Line Address Offset
The Main Window Line Address Offset register (REG[44h]) is based on the display width
and programmed using the following formula.
REG[44h] bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 480 pixels ÷ 32 ÷ 8 bpp
= 120 (78h)
13.4 270° SwivelView™
270° SwivelView™ requires the Memory Clock (MCLK) to be at least 1.25 times the
frequency of the Pixel Clock (PCLK), i.e. MCLK ≥ 1.25PCLK.
The following figure shows how the programmer sees a 320x480 portrait image and how
the image is being displayed. The application image is written to the S1D13A05 in the
following sense: A–B–C–D. The display is refreshed by the S1D13A05 in the following
sense: C-A-D-B.
physical memory
start address
A
B
SwivelView
window
display start address
(panel origin)
D
C
480
320
image seen by programmer
= image in display buffer
image refreshed by S1D13A05
Figure 13-3: Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView.
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13.4.1 Register Programming
Enable 270° SwivelView™ Mode
Set SwivelView™ Mode Select bits (REG[10h] bits 17:16) to 11.
Display Start Address
The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start
Address register (REG[40h]) must be programmed with the address of pixel “C”. To
calculate the value of the address of pixel “C” use the following formula (assumes 8 bpp
color depth).
REG[40h] bits 16:0 = (image address + ((panel width - 1) x offset x bpp ÷ 8) ÷ 4)
= (0 + ((480 pixels - 1) x 320 pixels x 8 bpp ÷ 8) ÷ 4)
= 38320 (95B0h)
Line Address Offset
The Main Window Line Address Offset register (REG[44h]) is based on the display width
and programmed using the following formula.
REG[44h] bits 9:0
= display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ 32 ÷ 8 bpp
= 80 (50h)
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14 Picture-in-Picture Plus (PIP+)
14.1 Concept
+
+
Picture-in-Picture Plus (PIP ) enables a secondary window (or PIP window) within the
+
main display window. The PIP window may be positioned anywhere within the virtual
display and is controlled through the PIP Window control registers (REG[50h] through
REG[5Ch]). The PIP window retains the same color depth and SwivelView orientation as
+
+
the main window.
+
The following diagram shows an example of a PIP window within a main window and the
registers used to position it.
0° SwivelViewTM
+
PIP window y start position
(REG[5Ch] bits 9-0)
panel’s origin
+
PIP window y end position
(REG[5Ch] bits 25-16)
main-window
+
PIP window
+
+
PIP window x start position
PIP window x end position
(REG[58h] bits 25-16)
(REG[58h] bits 9-0)
Figure 14-1: Picture-in-Picture Plus with SwivelView disabled
Hardware Functional Specification
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14.2 With SwivelView Enabled
14.2.1 SwivelView 90°
90° SwivelViewTM
panel’s origin
+
PIP window x start position
(REG[58h] bits 9-0)
+
PIP window x end position
(REG[58h] bits 25-16)
+
PIP window
+
PIP window y start position
(REG[5Ch] bits 9-0)
+
PIP window y end position
(REG[5Ch] bits 25-16)
main-window
Figure 14-2: Picture-in-Picture Plus with SwivelView 90° enabled
14.2.2 SwivelView 180°
180° SwivelViewTM
+
PIP window x end position
+
PIP window x start position
(REG[58h] bits 25-16)
(REG[58h] bits 9-0)
+
PIP window
main-window
+
PIP window y end position
(REG[5Ch] bits 25-16)
+
PIP window y start position
panel’s origin
(REG[5Ch] bits 9-0)
Figure 14-3: Picture-in-Picture Plus with SwivelView 180° enabled
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
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14.2.3 SwivelView 270°
270° SwivelViewTM
main-window
+
PIP window y end position
(REG[5Ch] bits 25-16)
+
PIP window y start position
+
PIP window
(REG[5Ch] bits 9-0)
+
PIP window x start position
+
PIP window x end position
(REG[58h] bits 9-0)
(REG[58h] bits 25-16)
panel’s origin
Figure 14-4: Picture-in-Picture Plus with SwivelView 270° enabled
Hardware Functional Specification
Issue Date: 2012/02/27
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Revision 7.7
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15 Power Save Mode
A software initiated Power Save Mode is incorporated into the S1D13A05 to accommodate
the need for power reduction in the hand-held devices market. This mode is enable via the
Power Save Mode Enable bit (REG[14h] bit 4).
Software Power Save Mode saves power by powering down the control signals and
stopping display refresh accesses to the display buffer. For programming information on
disabling the clocks, see the S1D13A05 Programming Notes and Examples, document
number X40A-G-003-xx.
Table 15-1: Power Save Mode Function Summary
Software
Normal
Power Save
IO Access Possible?
Memory Access Possible?
Look-Up Table Registers Access Possible?
Display Active?
Yes
Yes
Yes
1
Yes
Yes
Yes
No
Yes
LCD I/F Outputs
Forced Low
Stopped
Forced Low
Active
Active
Active
Yes
PWMCLK
GPIO Pins configured for HR-TFT
GPIO Pins configured as GPIOs; Access Possible?
USB Running?
2
Yes
3
Yes
Yes
Note
1
When power save mode is enabled, the memory controller is powered down and the
status of the memory controller is indicated by the Memory Controller Power Save Sta-
tus bit (REG[14h] bit 6). However, memory reads/writes are possible during power save
mode because the S1D13A05 dynamically enables the memory controller for display
buffer accesses.
2
GPIOs can be accessed and if configured as outputs can be changed.
The power-down state of the USB section is controlled by the USBClk Enable bit
3
(REG[4000h] bit 7).
After reset, the S1D13A05 is always in Power Save Mode. Software must initialize the chip
(i.e. programs all registers) and then clear the Power Save Mode Enable bit.
S1D13A05
X40A-A-001-07
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Issue Date: 2012/02/27
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16 USB Considerations
16.1 USB Oscillator Circuit
The following circuit provides an example implementation for using an external oscillator
to drive USBCLK.
USBOSCI
USBOSCO
R
f
R
d
C
C
d
g
Figure 16-1: USB Oscillator Example Circuit
The following values are recommended for a 48MHz fundamental mode oscillator. If an
oscillator of a different value is used, the capacitive and resistive values must be adjusted
accordingly.
Table 16-1: Resistance and Capacitance Values for Example Circuit
Symbol
Value
1MΩ
470Ω
12pF
12pF
R
f
R
d
C
C
g
d
Hardware Functional Specification
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17 Mechanical Data
1.2max
+0.30
+0.10
-0.15
-0.05
10
0.35
0.1max
TOP VIEW
SIDE VIEW
+0.10
-0.05
1.0
0.45
0.08
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11
BOTTOM VIEW
All dimensions in mm
Figure 17-1: Mechanical Data PFBGA 121-pin Package
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
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18 References
The following documents contain additional information related to the S1D13A05.
Document numbers are listed in parenthesis after the document name. All documents can
be found at the Epson Research and Development Website at www.erd.epson.com.
• S1D13A05 Product Brief (X40A-C-001-xx)
• S1D13A05 Programming Notes And Examples (X40A-G-003-xx)
• S1D13A05 Register Summary (X40A-R-001-xx)
• Interfacing to the Toshiba TMPR3905/3912 Microprocessor (X40A-G-002-xx)
• Interfacing to the PC Card Bus (X40A-G-005-xx)
• S1D13A05 Power Consumption (X40A-G-006-xx)
• Interfacing to the Freescale MCF5307 "Coldfire" Microprocessor (X40A-G-010-xx)
• S1D13A05 Wind River WindML v2.0 Display Drivers (X40A-E-003-xx)
• S5U13A05B00C Rev. 1.0 Evaluation Board User Manual (X40A-G-004-xx)
• 13A05CFG Configuration Utility Users Manual (X40A-B-001-xx)
• 13A05PLAY Diagnostic Utility Users Manual (X40A-B-002-xx)
• 13A05VIEW Demonstration Utility Users Manual (X40A-B-003-xx)
• S5U13A05P00C100 Evaluation Board User Manual (X40A-G-014-xx)
• Errata No. X00Z-P-001 (X00Z-P-001-xx)
Hardware Functional Specification
Issue Date: 2012/02/27
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Revision 7.7
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19 Sales and Technical Support
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
214 Devcon Drive
San Jose, CA 95112,USA
EPSON (CHINA) CO., LTD.
7F, Jinbao Bldg., No.89 Jinbao St.,
Dongcheng District,
Beijing 100005, CHINA
Phone: +86-10-8522-1199 FAX: +86-10-8522-1125
Phone: +1-800-228-3964
FAX: +1-408-922-0238
SHANGHAI BRANCH
7F, Block B, High-Tech Bldg., 900, Yishan Road,
Shanghai 200233, CHINA
EUROPE
EPSON EUROPE ELECTRONICS GmbH
Riesstrasse 15, 80992 Munich,
GERMANY
Phone: +86-21-5423-5577 FAX: +86-21-5423-4677
SHENZHEN BRANCH
12F, Dawning Mansion, Keji South 12th Road,
Hi-Tech Park, Shenzhen 518057, CHINA
Phone: +86-755-2699-3828 FAX: +86-755-2699-3838
Phone: +49-89-14005-0
FAX: +49-89-14005-110
EPSON HONG KONG LTD.
Unit 715-723, 7/F Trade Square, 681 Cheung Sha Wan Road,
Kowloon, Hong Kong
Phone: +852-2585-4600
FAX: +852-2827-4346
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road,
Taipei 110, TAIWAN
Phone: +886-2-8786-6688 FAX: +886-2-8786-6660
EPSON SINGAPORE PTE., LTD.
1 HarbourFront Place,
#03-02 HarbourFront Tower One, Singapore 098633
Phone: +65-6586-5500
FAX: +65-6271-3182
SEIKO EPSON CORP.
KOREA OFFICE
5F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: +82-2-784-6027
FAX: +82-2-767-3677
SEIKO EPSON CORP.
MICRODEVICES OPERATIONS DIVISION
Device Sales & Marketing Dept.
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814
FAX: +81-42-587-5117
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
Epson Research and Development
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Vancouver Design Center
Change Record
X40A-A-001-07
Revision 7.7- Issued: February 27, 2012
• globally remove QFP5-128 package
• section 2.9, remove QFP package to features
• section 4.1.2, remove QFP package pin diagram
• section 4.2, remove QFP package pin descriptions
• section 18, remove QFP package mechanical drawing
Revision 7.6 - Issued: December 18, 2008
X40A-A-001-07
X40A-A-001-07
• all changes from the previous revision are in Red
• section 19, updated Sales and Technical Support addresses
Revision 7.5 - Issued: February 13, 2008
• all changes from the previous revision are in Red
• Release as revision 7.5 to align with Japan numbering
• section 18 References - remove references to obsolete application notes and change
“Interfacing to the Motorola MCF5307...” to “Interfacing to the Freescale MCF5307...”
X40A-A-001-07
Revision 7.04 - Released: September 17, 2007
• all changes from the previous revision are in Red
• section 18, updated Refereces
• section 19, updated Sales and Technical Support addresses
Revision 7.03 - Released: June 13, 2007
X40A-A-001-07
X40A-A-001-07
• all changes from the previous revision are in Red
• section 4.2.1, corrected the PFBGA Pin# listing for the DB[15:0] pin description
Revision 7.02 - Released: February 01, 2007
• all changes from the previous revision are in Red
• section 6.5, changed formula for VPS from “REG[002Ch] bits 9-0” to “REG[003Ch]
bits 9-0”
• section 6.5.1, changed formula for VPS from “REG[002Ch] bits 9-0” to “REG[003Ch]
bits 9-0”
X40A-A-001-07
Revision 7.01, Released: October 3, 2006
• all changes from the previous revision are in Red
• REG[04h] bit 0 - remove reference to CNF7
Hardware Functional Specification
Issue Date: 2012/02/27
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Revision 7.7
Page 184
Epson Research and Development
Vancouver Design Center
• section 19 Sales and Technical Support - update the addresses for North America and
Singapore
X40A-A-001-07
X40A-A-001-06
Revision 7, Released: July 7, 2006
• all changes from the previous revision are in Red
• add section 6.2 RESET# Timing
Revision 6.01
• section 3.1, figure 3-1, changed System Diagram for Generic #1 so that BS# pin is
connected to IOVDD instead of VSS (GND)
• section 4.2.1, table 4-2, changed BS# pin description for Generic #1 so that BS# pin is
connected to IOVDD instead of VSS (GND)
• REG[10h] bits 4-0, updated the Bits-Per-Pixel bit description and clarified the color
depth table
X40A-A-001-06
X40A-A-001-05
Revision 6.0
• released as revision 6.0
Revision 5.01
• section 2.9, added QFP package to features
• section 4.1.2, added QFP package pin diagram
• section 4.2, added QFP package pin descriptions
• section 18, added QFP package mechanical drawing
Revision 5.0
X40A-A-001-05
X40A-A-001-04
• released as revision 5.0
Revision 4.01
• section 4.2.2, for DRDY pin description, removed description for HR-TFT (not used)
S1D13A05
X40A-A-001-07
Hardware Functional Specification
Issue Date: 2012/02/27
Revision 7.7
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