S1D15100D00C [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, UUC48, DIE-48;
| 型号： | S1D15100D00C |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC48, DIE-48 驱动 接口集成电路 |
| 文件： | 总13页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1. S1D15100 Series
Rev. 1.0
Contents
1. DESCRIPTION ................................................................................................................................................1-1
2. FEATURES......................................................................................................................................................1-1
3. BLOCK DIAGRAM ..........................................................................................................................................1-1
4. PAD LAYOUT AND COORDINATES ..............................................................................................................1-2
5. PIN LAYOUT (S1D1500F00C ) .....................................................................................................................1-3
*
6. PIN DESCRIPTION .........................................................................................................................................1-3
7. FUNCTIONAL DESCRIPTION ........................................................................................................................1-4
8. COMMANDS ...................................................................................................................................................1-7
9. THE SUPPLY VOLTAGES ..............................................................................................................................1-8
10. ABSOLUTE MAXIMUM RATINGS .................................................................................................................. 1-9
11. DC ELECTRICAL CHARACTERISTICS ......................................................................................................... 1-9
12. AC ELECTRICAL CHARACTERISTICS........................................................................................................1-10
– i –
Rev. 1.0
S1D15100 Series
1. DESCRIPTION
2. FEATURES
The S1D15100Series is a segment driver IC for
1/4-duty LCD panels. It features 150 µW maximum
power dissipation and a wide operating supply voltage
range, making it ideal for use in battery-powered devices.
The S1D15100 series incorporates an LCD driving power
circuit and allows simple configuration of the interface
with a microcomputer, achieving a handy type unit at low
cost.
• 1/4-duty LCD segment driver
• 150 µW maximum power dissipation
• Serial data interface
• 128 bits of display data RAM
• On-chip oscillator
• LCD drive voltage generator
• Four common driver outputs
• 32 segment driver outputs
• 0.9 to 6.0 V supply for logic circuitry operation
• 1.8 to 6.0 V supply for LCD driver operation
• Series specification
S1D15100D00C : chip (Al pad)
*
S1D15100F00C : QFP12-48pin
*
3. BLOCK DIAGRAM
SEG0
to
SEG31
COM0 COM1 COM2 COM3
V
DD
V
1
2
3
LCD drive
voltage
generator
Segment drivers
Common drivers
V
V
VSS
OSC1
OSC2
Timing
Address
counter
Address
decoder
Common
Display data memory
generator
counter
circuit
Command decoder
SI
CK
C/D
CS
Command/data register
Rev. 1.0
EPSON
1–1
S1D15100 Series
4. PAD LAYOUT AND COORDINATES
(S1D15100D00C )
*
Sectional dimensions
2500
µm
Pad
30
25
35
±
300 30µm
MAX30
40
45
MAX50µm
D1510D0B
20
2500
Size of pad opening
µm
15
100µm
100µm
1
5
10
Chip size:
Chip pitch:
2500µm × 2500µm
525µm
Pad center coordinates
Unit: µm
Pin name X coordinate Y coordinate
No.
Pin name X coordinate Y coordinate
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OSC1
OSC2
V1
V2
V3
VSS
VDD
CK
SI
-898
-738
-578
-418
-258
-98
63
223
383
543
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-898
-738
-578
-418
-258
-98
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SEG 8
SEG 9
898
738
578
418
258
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
898
738
578
418
258
98
-63
SEG 10
SEG 11
SEG 12
SEG 13
SEG 14
SEG 15
SEG 16
SEG 17
SEG 18
SEG 19
SEG 20
SEG 21
SEG 22
SEG 23
SEG 24
SEG 25
SEG 26
SEG 27
SEG 28
SEG 29
SEG 30
SEG 31
98
-63
-223
-383
-543
-703
-863
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
-1091
CS
C/D
703
863
COM0
COM1
COM2
COM3
VREG
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
1091
63
224
383
543
703
863
-223
-383
-543
-703
-863
Origin: Center of the chip
Chip size: 2,500 × 2,500
1–2
EPSON
Rev. 1.0
S1D15100 Series
5. PINOUT (S1D15100F00C )
*
No.
Name
No.
Name
No.
Name
1
2
3
OSC1
OSC2
V1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
36
25
37
24
4
5
6
7
V2
V3
VSS
VDD
8
9
CK
SI
CS
Index
10
11
12
13
14
15
16
C/D
COM0
COM1
COM2
COM3
VREG
48
13
1
12
6. PIN DESCRIPTION
Pin Name
I/O
Description
Q’ty
VDD
Power supply
Plus power terminal.
1
Common to the microcomputer power terminal VCC.
VSS
Power supply
O
Minus power supply.
A 0V terminal to be connected to the system GND.
1
2
V1
V2
Power level monitor terminal for liquid crystal drive.
The levels V1 = 1/3 × V3 and V2 = 2/3 × V3 are generated from
the inside of S1D15100F00C .
*
V3
SI
Power supply
I
Power terminal for liquid crystal drive.
Potential relations: VDD > V3.
1
1
Serial data input.
Input of display data and of commands to control operation of
S1D15100F00C . When display data is input, the relations
*
between display data input and segment ON/OFF are as follows:
SI input “0” → OFF, SI input “1” → ON
CK
C/D
CS
I
I
I
Shift clock input of serial data (SI input).
SI input data is read bit by bit in the serial register at the CK
input leading edge.
1
1
1
Identification of SI input as data or command (in case of
S1D15100F00C only). The LOW level indicates data, and the
*
HIGH level does commands.
Chip select signal input (in case of S1D15100F00C only).
*
When CS input is changed from the HIGH level to the LOW
level, S1D15100F00C can accept SI inputs.
*
The CK counter is set to the initial state when the CS input is
changed from the HIGH level to the LOW level.
OSC1
OSC2
I
O
Oscillation resistance connection terminal
2
SEG0 to SEG31
COM0 to COM3
VREG
O
O
O
Segment signal for liquid crystal drive
Common signal for liquid crystal drive
Test terminal. Keep it open.
32
4
1
Total 48
Rev. 1.0
EPSON
1–3
S1D15100 Series
7. FUNCTIONAL DESCRIPTION
Command/Data Register
◊ When the CK counter counts 8 of shift clock input (CK
input) (reads the input 8-bit serial data), the serial data
taken in the command/data register is output to the
display data memory (RAM) if the input serial data is
a display data, or is output to the command decoder if
it is a command data.
◊ S1D15100 Serise identifies input serial data (SI input)
as display data or command data judging from C/D
input. It displays display data when C/D input is LOW
level or command data when the input is HIGH level.
◊ S1D15100 Serise reads and identifies C/D input at the
timing on the rising edge of 8xn of shift clock input
(CK input) from the CS = LOW level. (n=1, 2, 3, ...)
◊ The command/data register consists of an 8-bit serial
register and a 3-bit CK counter.
◊ When CS input changes from the HIGH level to the
LOW level, S1D15100 Serise comes to accept SI
inputs. Also, the CK counter is initialized when CS
input changes from the HIGH level to the LOW level.
S1D15100 Serise always accepts SI inputs. When the
built-in timing generator (CR oscillator) starts
oscillating, the CK counter is initialized.
◊ The serial register takes in serial data D7, D6, ... D0 in
this order from the SI terminal on the rising edge of the
CK. At the same time, the CK counter starts counting
the serial clock. The CK counter, when counting 8 on
the serial clock, returns to the initial state.
◊ So, serial data is taken in to the serial register in 8 bits
and is processed.
CS
SI
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
CK
C/D
Command Decoder
◊ When the command/data register data specifies any
command (when C/D input is HIGH level when serial
data is input), the command decoder takes in and
decode the data of the command/data register to control
S1D15100F00C .
*
Display Data Memory
The format of the 32 × 4-bit memory is shown in the
following figure.
Address
0
1
2
3
4
5
6
7
8
29 30 31
0
1
2
3
Bit
Each 8-bit display data byte loaded from the command/
data register is stored in two consecutive addresses as
shown in the following figure. The upper four bits are
stored at the location specified by the address counter,
and the lower four bits, at the next location. The address
counter is automatically incremented by two.
Bit 3
D7
Bit 0
D4
Bit 3
D3
Bit 0
D0
D6
D5
D2
D1
Current address
Current address + 1
1–4
EPSON
Rev. 1.0
S1D15100 Series
A single 4-bit word can be written to memory using the
Data Memory Write command as shown in the following
figure. The lower four bits are stored at the location
specified by the address counter. The address counter is
automatically incremented by one.
Note
= don’t care
◊ The display data memory address is automatically
incremented by 2 when a 8-bit display data (C/D =
LOW level) is stored, or incremented by 1 when a 4-
bit data is stored by the display data re-write command.
◊ After the display data is written in the RAM, the RAM
address is held as shown below unless the address is
reset:
1
0
0
D3
D2
D1
D0
After writing a 8-bit display data ...
the final write address is incremented by 2.
After rewriting a 4-bit display data ...
Bit 3
D3
Bit 0
D0
D2
D1
the final rewrite address is incremented by 1.
◊ Data in the display data memory synchronizes with the
COM0 to COM3 signals and is output in 32 bits to the
segment driver.
Address = n
The relations of the display data memory, the segment
terminal and common signal selection timing are as
follows:
SEG SEG SEG SEG SEG SEG SEG SEG
SEG SEG SEG
29 30 31
0
1
2
3
4
5
6
7
COM0
COM1
COM2
COM3
0
1
Bit
2
3
0
1
2
3
4
5
6
7
29 30 31
Address
Address Counter
Timing Generator
◊ The address counter is a presettable type to give 5-bit
addresses to the display data memory.
◊ In case of S1D15100 Serise, any address can be set
when the address set command is used.
A low-power oscillator can be constructed using an
external feedback resistor as shown in the following
figure.
◊ In case of S1D15100 Serise, set addresses are
automatically incremented by 2 when an 8-bit display
data is stored (C/D = LOW level), or incremented by
1 when a 4-bit data is stored by the display data
memory rewrite command.
680 kΩ
OSC1
OSC2
Rf
Alternatively, an 18 kHz external clock can be input on
OSC1, and OSC2 left open, as shown in the following
figure.
◊ The address decoder, after counting Address 31, counts
0 at the next counting and repeats as follows:
OSC1
OSC2
Open
Address 0
Address 31
External clock
Address Decoder
Common Counter
The address decoder sets addresses 0 to 31 of the display
data memory where the display data of address counter
is written.
The timing generator clock signal is frequency-divided
by the common counter to generate both the common
drive timing and the alternating frame timing.
Rev. 1.0
EPSON
1–5
S1D15100 Series
Segment and Common Drivers
The 32 segment drivers and the four common drivers are
4-level outputs that switch between VDD and the V1, V2
and V3 LCD driver voltage levels.
The output states are determined by the display data
values and the common counter as shown in the follow-
ing figure. The outputs are used to drive a 1/3-bias, 1/4-
duty LCD panel.
Frame period
V
V
V
V
DD
1
COM0
COM1
COM2
2
3
COM3
COM0
0
COM1
0
COM2
0
COM3
0
V
V
V
V
DD
1
All segments are OFF.
2
3
V
V
V
V
DD
1
1
0
0
0
2
Segments connected to COM0 are ON.
3
V
V
V
V
DD
1
Seg 0
0
1
0
0
1
2
to
Segments connected to COM1 are ON.
3
Seg 31
V
V
V
V
DD
1
0
1
0
2
3
Segments connected to COM1 or COM3 are ON.
V
V
V
V
DD
1
1
1
1
1
2
3
All segments are ON.
1–6
EPSON
Rev. 1.0
S1D15100 Series
8. COMMANDS
Display Start
The S1D15100F00C samples C/D on every eighth
Return to normal display mode. The display memory
data is output to the display.
*
rising edge of CK. If C/D is HIGH, the command/data
register contents are latched into the command decoder.
The command decoder executes the following six com-
mands.
0
1
1
Address Set
Set the address counter to the value specified by D0 to
D4.
Note:
= don’t care
Memory Write
0
0
0
D4 D3 D2 D1 D0
Store the data D0 to D3 at the location specified by the
address counter. The address counter is automatically
incremented by one. The other display memory loca-
tions are not affected.
Addresses are incremented by 2 each time a display data
(8-bit) is input. The relations between D4 to D0 and
addresses are as follows:
1
0
0
D3 D2 D1 D0
D4 D3 D2 D1 D0
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
Data are allocated to each bit of the display data memory
as follows:
Bit 3
D3
Bit 0
D0
D2
D1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
28
29
30
31
Address = n
Note:
= don’t care
Reset
Reset the S1D15100F00C . The S1D15100F00C
then enters normal operating mode, and the display turns
OFF.
*
*
Display ON
Turn all LCD segments ON. The display memory data
is not affected.
1
1
0
0
0
1
Note:
= don’t care
Note:
= don’t care
Display OFF
Turn all LCD segments OFF. The display memory data
is not affected.
0
1
0
Note:
= don’t care
Rev. 1.0
EPSON
1–7
S1D15100 Series
9. SUPPLY VOLTAGES
In addition to VDD, there are three LCD supply voltages:
V1 , V2 and V3. V3 is supplied externally, whereas V1 and
V2 are generated internally. V1, V2 and V3 are given by
the following equations.
When there is a lot of distortion in the LCD drive
waveforms, connect bleeder resistors as shown in the
following figure.
V1 = VDD – 1/3VLCD
V2 = VDD – 2/3VLCD
V3 = VDD – VLCD
where VLCD is the LCD drive voltage. The voltages must
be such that
V
V
V
V
V
DD
1
R1
R2
R3
VDD ≥ V1 ≥ V2 ≥ V3
LCD supply voltage connections when the LCD drive
supply is connected to VSS are shown in figure 1, and the
connections when the drive supply is independent of
VSS, in Figure 2.
2
3
SS
V
V
V
V
V
DD
1
2
3
SS
Figure 1. LCD drive supply connected to VSS
V
V
V
V
V
DD
1
2
3
SS
Figure 2. LCD drive supply not connected to VSS
1–8
EPSON
Rev. 1.0
S1D15100 Series
10. ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage range
LCD supply voltage range
Input voltage range
Output voltage range
Power dissipation
Operating temperature
range
Symbol
VSS
V3
Vl
VO
Rating
–7.0 to 0.3
–7.0 to 0.3
SS –0.3 to 0.3
SS –0.3 to 0.3
250
Unit
V
V
V
V
V
V
PD
mW
Topg
Tstg
Tsol
–20 to 75
–65 to 150
260
°C
Storage temperature range
Soldering temperature
(10 sec at leads)
°C
°C
Heat resistance
400 • 10
°C•Min
Note: All voltages shown are specified on a
VDD = 0 V basis.
11. DC ELECTRICAL CHARACTERISTICS
VDD = 0V, VSS = –5.0 ±0.5 V, Ta = –20 to 75 °C unless otherwise noted
Rating
Typ.
—
Parameter
Supply voltage
Symbol
Condition
Unit
Min.
–6.0
—
Max.
–0.9
—
VSS
V1
V2
V
1/3
2/3
×
×
V3
V3
LCD supply voltages
—
—
V
V3
IDDQ
–6.0
—
—
0.05
–1.8
1.0
Quiescent supply current
VSS = –6.0 V, VIN = VDD
Display mode, Rf = 680 K
VSS = –5.0 V
Input mode, VSS = –5.0 V,
fck = 200 kHz
µA
Ω
,
IDD1
IDD2
—
—
20.0
30.0
250
Supply current
µA
100
LOW-level input voltage
HIGH-level input voltage
Input leakage current
VIL
VIH
ILI
VSS
0.2 VSS
—
—
—
0.05
0.8 VSS
VDD
2.0
V
V
µA
VSS
≤
VIN
≤
VDD
SEG0 to SEG31 and COM0 to
COM3 LOW-level output voltage
SEG0 to SEG31 and COM0 to
COM3 HIGH-level output voltage
Output leakage current
VOL
IOL = 0.1 mA
—
—
—
VSS+ 0.4
—
V
V
VOH
ILO
IOH = –0.1 mA
VSS
–0.4
≤
VOUT
≤
VDD
—
—
—
—
0.05
18
16
5.0
—
—
µA
VSS = –5.0 V, Rf = 680
VSS = –3.0 V, Rf =680
Ta = 25 C, f = 1 MHz
V3 = –5.0 V, I
Ta = 25
V3 = –0.3 V, I
Ta = 25
±
2% k
Ω
Oscillator frequency
fOSC
CI
kHz
pF
±2% k
Ω
Input terminal capacity
°
5.0
8.0
∆
∆
VON I = 0.1 V,
VON I = 0.1 V,
—
—
5.0
7.5
50.
SEG0 to SEG31 and COM0 to
COM3 ON resistance
*1
°C
RON
k
Ω
10.0
°C
*1 The internal power impedance is not included in the LCD driver on resistance (RON).
Rev. 1.0
EPSON
1–9
S1D15100 Series
12. AC ELECTRICAL CHARACTERISTICS
VDD = 0 V, VSS = –5.0 ±0.5 V, Ta = –20 to 75 °C
Rating
Typ.
—
Parameter
Symbol
Condition
Unit
Min.
900
Max.
—
CK period
tCYC
tPWL1
tPWH1
tDW1
ns
ns
ns
ns
ns
ns
ns
CK LOW-level pulsewidth
CK HIGH-level pulsewidth
SI to CK setup time
400
—
—
400
100
—
—
—
—
CK to SI hold time
CS LOW-level puisewidth
CS HIGH-level pulsewidth
tDH1
200
—
—
—
—
tPWL2
tPWH2
tPWL2
≥
8tCYC
7200*1
400
—
—
Referenced to the rising edge of the
first CK cycle.
CS to CK setup time
CK to CS hold time
tDW2
tDH2
tDW3
tDH3
100
200
9
—
—
—
—
—
—
—
—
ns
ns
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
C/
D
to CK setup time
hold time
µs
CK to C/
D
1
µs
Rise time
Fall time
tr
tf
—
—
—
—
50
50
ns
ns
1
*
tCYC × 8
VDD = 0 V, VSS = –6.0 to –1.5 V, Ta = –20 to 75 °C
Rating
Typ.
—
Parameter
Symbol
Condition
Unit
Min.
10
Max.
—
—
CK period
tCYC
tPWL1
tPWH1
tDW1
µs
µs
CK LOW-level puisewidth
CK HIGH-level pulsewidth
SI to CK setup time
4.5
4.5
1.2
2.3
80*1
4.5
—
—
—
—
—
µs
µs
CK to SI hold time
tDH1
—
—
µs
CS LOW-level pulsewidth
CS HIGH-level pulsewidth
tPWL2
tPWH2
tPWL2
≥
8tCYC
—
—
—
—
µs
µs
Referenced to the rising edge of the
first CK cycle.
CS to CK setup time
CK to CS hold time
tDW2
tDH2
tDW3
tDH3
1.2
2.3
100
11
—
—
—
—
—
—
—
—
µs
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
Referenced to the rising edge of the
eighth CK cycle.
µs
C/
D
to CK setup time
hold time
µs
CK to C/
D
µs
Rise time
Fall time
tr
tf
—
—
—
—
50
50
ns
ns
1
*
tCYC × 8
1–10
EPSON
Rev. 1.0
S1D15100 Series
Timing Chart
t
PWH2
t
PWL2
CS
t
DH2
t
DW2
t
CYC
t
PWH1
CK
SI
t
f
t
PWL1
t
r
t
DW1
tDH1
t
DW3
tDH3
C/D
Timing measurement
0.2VSS
0.8VSS
0.2VSS
0.8VSS
Rev. 1.0
EPSON
1–11
相关型号：
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