EN2340QI_技术文档

EN2340QI

4A Voltage Mode Synchronous Buck PWM

DC-DC Converter with Integrated Inductor

PowerSOC

Description

Features

The EN2340QI is a Power System on a Chip

(PowerSoC) DC-DC converter. It integrates MOSFET

switches, small-signal control circuits, compensation

and an integrated inductor in an advanced 8x11x3mm

QFN module. It offers high efficiency, excellent line

and load regulation over temperature and up to the

full 4A load range. The EN2340QI operates over a

wide input voltage range and is specifically designed

to meet the precise voltage and fast transient

requirements of high-performance products. The

EN2340 features frequency synchronization to an

external clock, power OK output voltage monitor,

programmable soft-start along with thermal and over

current protection. The device’s advanced circuit

design, ultra high switching frequency and proprietary

integrated inductor technology delivers high-quality,

ultra compact, non-isolated DC-DC conversion.

•

Integrated Inductor, MOSFETs, Controller

Wide Input Voltage Range: 4.5V – 14V

Guaranteed 4A I_OUTat 85°C with No Airflow

Frequency Synchronization (External Clock)

2% V_OUTAccuracy (Over Line/Load/Temperature)

High Efficiency (Up to 95%)

Output Enable Pin and Power OK signal

Programmable Soft-Start Time

Pin Compatible with the EN2360QI (6A)

Under Voltage Lockout Protection (UVLO)

Programmable Over Current Protection

Thermal Shutdown and Short Circuit Protection

RoHS Compliant, MSL Level 3, 260^oC Reflow

Applications

The Enpirion solution significantly helps in system

design and productivity by offering greatly simplified

•

Space Constrained Applications

Distributed Power Architectures

board

design,

layout

and

manufacturing

requirements. In addition, overall system level

reliability is improved given the small number of

components required with the Enpirion solution.

Output Voltage Ripple Sensitive Applications

Beat Frequency Sensitive Applications

Servers, Embedded Computing Systems,

LAN/SAN Adapter Cards, RAID Storage Systems,

Industrial Automation, Test and Measurement,

and Telecommunications

All Enpirion products are RoHS compliant and lead-

free manufacturing environment compatible.

Efficiency vs. Output Current

100

95

90

85

Actual Solution Size

80

75

70

65

60

55

50

200mm²

CONDITIONS

V_IN= 8.0V

AVIN = 3.3V

Dual Supply

VOUT = 5.0V

0

0.5

1

1.5

2

2.5

3

3.5

4

OUTPUT CURRENT(A)

Figure 1. Simplified Applications Circuit

Figure 2. Highest Efficiency in Smallest Solution Size

(Footprint Optimized)

www.enpirion.com

06878

April 16, 2012

Rev: B

EN2340QI

Ordering Information

Part Number

EN2340QI

EN2340QI-E

Package Markings

EN2340QI

Temp Rating (°C)

Package Description

68-pin (8mm x 11mm x 3mm) QFN T&R

QFN Evaluation Board

-40 to +85

EN2340QI

Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm

Pin Assignments (Top View)

48

S_OUT

1

NC

KEEP OUT

47

S_IN

2

NC

46

3

4

BGND

VDDB

NC

45

44 BTMP

5

69

PGND

43

6

PG

KEEP OUT

42

AVINO

7

41

PVIN

8

40

PVIN

9

39

PVIN

10

11

12

13

14

38

PVIN

37

PVIN

36

PVIN

35

PVIN

Figure 3: Pin Out Diagram (Top View)

NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.

However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.

NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically

connected to the PCB. Refer to Figure 10 for details.

NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.

Pin Description

I/O Legend:

P=Power

G=Ground

NC=No Connect

I=Input O=Output

I/O=Input/Output

NAME I/O

FUNCTION

1-15,

25-26,

59, 64-

68

NO CONNECT – These pins may be internally connected. Do not connect them to each

NC other or to any other electrical signal. Failure to follow this guideline may result in device

damage.

NC

Regulated converter output. Connect these pins to the load and place output capacitor

between these pins and PGND pins 29-34.

16-24

VOUT

O

NO CONNECT – These pins are internally connected to the common switching node of the

NC(SW) NC internal MOSFETs. They are not to be electrically connected to any external signal, ground,

or voltage. Failure to follow this guideline may result in damage to the device.

27-28,

61-63

Enpirion Confidential

www.enpirion.com, Page 2

06878

April 16, 2012

Rev: B

EN2340QI

NAME I/O

FUNCTION

Input/output power ground. Connect these pins to the ground electrode of the input and

output filter capacitors. See VOUT and PVIN pin descriptions for more details.

Input power supply. Connect to input power supply. Decouple with input capacitor to

PGND pins 29-34.

29-34

PGND

G

35-41

42

PVIN

P

Internal 3V linear regulator output. Connect this pin to AVIN (Pin 51) for applications where

operation from a single input voltage (PVIN) is required. If AVINO is being used, place a

1µF, X5R/X7R, capacitor between AVINO and AGND as close as possible to AVINO.

AVINO

O

43

44

PG

BTMP

I/O Place a 0.1µF, X5R/X7R, capacitor between this pin and BTMP.

I/O See pin 43 description.

Internal regulated voltage used for the internal control circuitry. Place a 1.0µF, X7R,

capacitor between this pin and BGND.

See pin 45 description.

45

46

47

48

49

VDDB

BGND

S_IN

O

G

I

Digital Input. This pin accepts either an input clock to phase lock the internal switching

frequency or a S_OUT signal from another EN2340QI. Leave this pin floating if not used.

Digital Output. PWM signal is output on this pin. Leave this pin floating if not used.

Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power

system state indication. POK is logic high when VOUT is within -10% of VOUT nominal.

Input Enable. Applying a logic high to this pin enables the output and initiates a soft-start.

Applying a logic Low disables the output. Do not leave floating.

3.3V Input power supply for the controller. Place a 0.1µF, X7R, capacitor between AVIN

and AGND.

Analog Ground. This is the Ground return for the controller. Needs to be connected to a

quiet ground.

S_OUT

POK

O

50

51

ENABLE

AVIN

I

P

G

52, 53,

60

AGND

External Feedback Input. The feedback loop is closed through this pin. A voltage divider at

54

VFB

I/O VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A

phase lead capacitor from this pin to VOUT is also required to stabilize the loop.

55

56

EAOUT

SS

O

Optional Error Amplifier output. Allows for customization of the control loop.

Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The

value of this capacitor determines the startup time.

I/O

Programmable over-current protection. Placement of a resistor on this pin will adjust the

57

RCLX

I/O over-current protection threshold. See Table 2 for the recommended RCLX Value to set

OCP at the nominal value specified in the Electrical Characteristics table.

Adding a resistor (R_FS) to this pin will adjust the switching frequency of the EN2340QI. See

I/O Table 1 for suggested resistor values on R_FSfor various PVIN/VOUT combinations to

maximize efficiency. Do not leave floating.

58

69

FADJ

Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-

sinking purposes.

PGND

Enpirion Confidential

www.enpirion.com, Page 3

06878

April 16, 2012

Rev: B

EN2340QI

Absolute Maximum Ratings

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating

conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute

maximum rated conditions for extended periods may affect device reliability.

PARAMETER

Voltages on : PVIN, VOUT

SYMBOL

MIN

-0.5

MAX

15

UNITS

V

Voltages on: EN, POK, M/S

-0.3

0.3

V_IN+0.3

3

V

V/ms

V

PVIN Slew Rate

Pin Voltages – AVINO, AVIN, ENABLE, POK, S_IN, S_OUT

Pin Voltages – VFB, SS, EAOUT, RCLX, FADJ

Storage Temperature Range

2.5

6.0

-0.5

-65

2.75

150

260

2000

500

V

T_STG

°C

V

Maximum Operating Junction Temperature

Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A

ESD Rating (based on Human Body Model)

ESD Rating (based on CDM)

T_{J-ABS Max}

V

Recommended Operating Conditions

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Voltage Range

PVIN

4.5

14

V

AVIN: Controller Supply Voltage

Output Voltage Range (Note 1)

Output Current

AVIN

V_OUT

I_OUT

T_A

2.5

5.5

5

V

0.75

4

A

Operating Ambient Temperature

Operating Junction Temperature

-40

+85

+125

°C

T_J

Thermal Characteristics

PARAMETER

SYMBOL

TYP

UNITS

Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)

18

°C/W

θ_JA

Thermal Resistance: Junction to Case (0 LFM)

Thermal Shutdown

2

°C/W

°C

θ_JC

T_SD

160

35

Thermal Shutdown Hysteresis

T_SDH

°C

Note 1: RCLX resistor value may need to be raised for V_OUT> V_IN– 2.5V to increase current limit threshold.

Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for

high thermal conductivity boards.

Enpirion Confidential

www.enpirion.com, Page 4

06878

April 16, 2012

Rev: B

EN2340QI

Electrical Characteristics

NOTE: V_IN=12V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.

Typical values are at T_A= 25°C.

PARAMETER

Operating Input Voltage

SYMBOL

PVIN

TEST CONDITIONS

MIN TYP MAX UNITS

4.5

14.0

V

Controller Input Voltage

AVIN

2.5

5.5

V

AVIN Under Voltage

Lock-Out Rising

Voltage above which UVLO is not

asserted

AVIN_UVLOR

2.3

V

AVIN Under Voltage

Lock-Out Falling

Voltage below which UVLO is

asserted

AVIN_OVLOF

I_AVIN

2.1

7

V

mA

V

AVIN pin Input Current

Internal Linear

Regulator Output

AVINO

3.3

IPVIN_S

IAVIN_S

V_FB

PVIN=12V, AVIN=3.3V, ENABLE=0V

VIN = 12V, I_LOAD= 0, TA = 25°C Only

4.5V ≤ V^IN≤ 14V; 0A ≤ I_LOAD≤ 4A

500

50

μA

V

Shut-Down Supply

Current

Feedback Pin Voltage

0.7425 0.750 0.7575

V_FB

0.735

0.750

0.765

V

VFB pin input leakage current

(Note 3)

Feedback Pin Input

Leakage Current

I_FB

t_RISE

-5

5

nA

ms

nF

V_OUTRise Time

C_SS= 47nF (Note 4 and Note 5)

3.2

47

Soft-Start Capacitor

Range

C_{SS_RANGE}

10

68

4

Maximum Continuous

Output Current

I_{OUT_Max_Cont}

A

Over Current Trip Level

Disable Threshold

I_OCP

V_DISABLE

V_ENABLE

T_ENLOCKOUT

I_ENABLE

Reference Table 2

6

A

V

ENABLE pin logic Low

ENABLE pin logic High

0.0

1.8

0.6

ENABLE Threshold

ENABLE Lockout Time

ENABLE Input Current

Switching Frequency

AVIN

V

8

4

ms

μA

MHz

180k internal pull-down (Note 3)

F_SW

R_FS=3kΩ

1.0

External SYNC Clock

Frequency Lock Range

F_{PLL_LOCK}

Range of SYNC clock frequency

0.9

1.8

1.3

MHz

S_IN Threshold – Low

S_IN Threshold – High

S_OUT Threshold – Low

V_{S_IN_LO}

V_{S_IN_HI}

S_IN clock logic low level

S_IN clock logic high level

S_OUT clock logic low level

0.8

2.5

0.8

V

V_{S_OUT_LO}

S_OUT Threshold –

High

V_{S_OUT_HI}

S_OUT clock logic high level

2.5

V

POK Lower Threshold

POK Output low Voltage

POK Output Hi Voltage

POK_LT

V_POKL

V_POKH

V_OUT/ V_{OUT_NOM}

90

%

V

With 4mA current sink into POK

PVIN range: 4.5V ≤ V_IN≤ 14V

0.4

AVIN

V

POK pin V_OHleakage

current (Note 3)

I_POKL

POK high

1

µA

Note 3: Parameter not production tested but is guaranteed by design.

Note 4: Rise time calculation begins when AVIN > V_UVLOand ENABLE = HIGH.

Note 5: V_OUTRise Time Accuracy does not include soft-start capacitor tolerance.

Enpirion Confidential

www.enpirion.com, Page 5

06878

April 16, 2012

Rev: B

EN2340QI

Typical Performance Curves

Efficiency vs. Output Current

95

100

95

90

85

80

75

70

65

60

55

50

90

85

80

75

VOUT = 5.0V

VOUT = 3.3V

VOUT = 2.5V

VOUT = 1.8V

VOUT = 1.2V

VOUT = 1.0V

70

VOUT = 3.3V

65

CONDITIONS

V_IN= 8.0V

VOUT = 2.5V

CONDITIONS

V_IN= 12.0V

AVIN = 3.3V

Dual Supply

VOUT = 1.8V

VOUT = 1.2V

VOUT = 1.0V

60

55

50

CONDITIONS

AVIN = 3.3V

V_IN= 8.0V

Dual Supply

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

OUTPUT CURRENT(A)

Efficiency vs. Output Current

Output Voltage vs. Output Current

100

95

90

85

80

75

70

65

60

55

50

1.010

1.008

1.006

1.004

1.002

1.000

0.998

0.996

0.994

0.992

0.990

VIN = 5V

VIN = 8V

VIN = 12V

VOUT = 3.3V

VOUT = 2.5V

VOUT = 1.8V

CONDITIONS

V

= 5.0V

VOUT = 1.2V

VOUT = 1.0V

C^IO^NNDITIONS

CONDCIOTINODNISTIONS

V_{OUT_}V_NIONM==51.0.0VV

AVIN = 3.3V

V

= 8.0V

D^Iu^Nal Supply

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OUTPUT CURRENT(A)

0

0.5

1

1.5

2

2.5

3

3.5

4

OUTPUT CURRENT(A)

Output Voltage vs. Output Current

2.510

2.508

2.506

2.504

2.502

2.500

2.498

2.496

2.494

2.492

2.490

3.310

3.308

3.306

3.304

3.302

3.300

3.298

3.296

3.294

3.292

3.290

VIN = 8V

VIN = 5V

CONDITIONS

V_{OUT_NOM}= 2.5V

CONDITIONS

V_{OUT_NOM}= 3.3V

VIN = 8V

VIN = 12V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OUTPUT CURRENT(A)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OUTPUT CURRENT(A)

Enpirion Confidential

www.enpirion.com, Page 6

06878

April 16, 2012

Rev: B

EN2340QI

Typical Performance Curves (Continued)

Output Voltage vs. Input Voltage

1.020

1.015

1.010

1.005

1.000

0.995

0.990

3.320

Load = 0A

Load = 1A

Load = 2A

Load = 3A

Load = 4A

Load = 0A

Load = 1A

Load = 2A

Load = 3A

Load = 4A

CONDITIONS

V_{OUT_NOM}=1.0V

CONDITIONS

V_{OUT_NOM}=3.3V

3.315

3.310

3.305

3.300

3.295

3.290

3.285

3.280

2

4

6

8

10

12

14

16

85

2

4

6

8

10

12

14

16

85

INPUTVOLTAGE (V)

Output Voltage vs. Temperature

1.204

1.203

1.202

1.201

1.200

1.199

1.198

1.197

1.196

1.204

1.203

1.202

1.201

1.200

1.199

1.198

1.197

1.196

CONDITIONS

V_IN= 8V

_{OUT_NOM}=1.2V

CONDITIONS

V_IN= 10V

V_{OUT_NOM}=1.2V

V

LOAD = 0A

LOAD = 1A

LOAD = 2A

LOAD = 3A

LOAD = 4A

LOAD = 0A

LOAD = 1A

LOAD = 2A

LOAD = 3A

LOAD = 4A

-40

-15

10

35

60

-40

-15

10

35

60

AMBIENT TEMPERATURE ( C)

Output Voltage vs. Temperature

1.204

1.203

1.202

1.201

1.200

1.199

1.198

1.197

1.196

1.204

1.203

1.202

1.201

1.200

1.199

1.198

1.197

1.196

CONDITIONS

V_IN= 12V

_{OUT_NOM}=1.2V

CONDITIONS

V_IN= 14V

V_{OUT_NOM}=1.2V

V

LOAD = 0A

LOAD = 1A

LOAD = 2A

LOAD = 3A

LOAD = 4A

LOAD = 0A

LOAD = 1A

LOAD = 2A

LOAD = 3A

LOAD = 4A

-40

-15

10

35

60

-40

-15

10

35

60

AMBIENT TEMPERATURE ( C)

Enpirion Confidential

www.enpirion.com, Page 7

06878

April 16, 2012

Rev: B

EN2340QI

Typical Performance Characteristics

Output Ripple at 20MHz Bandwidth

Output Ripple at 500MHz Bandwidth

CONDITIONS

VIN = 12V

VOUT = 1V

IOUT = 2A

CIN = 2 x 22µF (1206)

COUT = 2 x 47 µF (1206)

CONDITIONS

VIN = 12V

VOUT = 1V

IOUT = 2A

CIN = 2 x 22µF (1206)

COUT = 2 x 47 µF (1206)

VOUT

(AC Coupled)

VOUT

(AC Coupled)

Output Ripple at 20MHz Bandwidth

Output Ripple at 500MHz Bandwidth

CONDITIONS

VIN = 12V

VOUT = 1V

IOUT = 4A

CIN = 2 x 22µF (1206)

CONDITIONS

VIN = 12V

VOUT = 1V

IOUT = 4A

CIN = 2 x 22µF (1206)

COUT = 2 x 47 µF (1206)

VOUT

COUT = 2 x 47 µF (1206)

(AC Coupled)

Enable Startup/Shutdown Waveform (0A)

Enable Startup/Shutdown Waveform (4A)

ENABLE

VOUT

ENABLE

VOUT

POK

CONDITIONS

VIN = 12V, VOUT = 1.0V, No Load, Css = 47nF

CIN = 2 x 22µF (1206), COUT = 2 x 47 µF (1206)

LOAD

CONDITIONS

VIN = 12V, VOUT = 1.0V, LOAD = 4A, Css = 47nF

CIN = 2 x 22µF (1206), COUT = 2 x 47 µF (1206)

Enpirion Confidential

www.enpirion.com, Page 8

06878

April 16, 2012

Rev: B

EN2340QI

Typical Performance Characteristics (Continued)

Load Transient from 0 to 2A

Load Transient from 0 to 4A

VOUT

(AC Coupled)

CONDITIONS

VIN = 12V, VOUT = 1.2V

CIN = 2 x 22µF (1206)

COUT = 2 x 47µF (1206)

VIN = 12V, VOUT = 1.2V

CIN = 2 x 22µF (1206)

COUT = 2 x 47µF (1206)

LOAD

Load Transient from 0 to 2A

Load Transient from 0 to 4A

VOUT

(AC Coupled)

CONDITIONS

VIN = 12V, VOUT = 2.5V

CIN = 2 x 22µF (1206)

COUT = 2 x 47µF (1206)

VIN = 12V, VOUT = 2.5V

CIN = 2 x 22µF (1206)

COUT = 2 x 47µF (1206)

LOAD

Enpirion Confidential

www.enpirion.com, Page 9

06878

April 16, 2012

Rev: B

EN2340QI

Functional Block Diagram

Figure 4: Functional Block Diagram

Functional Description

frequency of the EN2340QI enables the use of

small size input and output capacitors, as well as a

wide loop bandwidth within a small foot print.

Synchronous Buck Converter

The EN2340QI is a highly integrated synchronous,

buck converter with integrated controller, power

MOSFET switches and integrated inductor. The

nominal input voltage (PVIN) range is 4.5V to 14V

and can support up to 4A of continuous output

current. The output voltage is programmed using

an external resistor divider network. The control

loop utilizes a Type IV Voltage-Mode compensation

network and maximizes on a low-noise PWM

topology. Much of the compensation circuitry is

internal to the device. However, a phase lead

capacitor is required along with the output voltage

feedback resistor divider to complete the Type IV

compensation network.. The high switching

Protection Features:

The power supply has the following protection

features:

•

Programmable Over-Current Protection

Thermal Shutdown with Hysteresis.

Under-Voltage Lockout Protection

Additional Features:

•

Switching Frequency Synchronization.

Programmable Soft-Start

Power OK Output Monitoring

Enpirion Confidential

www.enpirion.com, Page 10

06878

April 16, 2012

Rev: B

EN2340QI

Power Up Sequence

The EN2340QI is designed to be powered by either

a single input supply (PVIN) or two separate

supplies: one for PVIN and the other for AVIN.

Single Input Supply Application (PVIN):

The EN2340QI has an internal linear regulator that

converts PVIN to 3.0V. The output of the linear

regulator is provided on the AVINO pin. AVINO

should be connected to AVIN on the EN2340QI. In

this application, the following external components

are required: Place a 1µF, X5R/X7R, capacitor

between AVINO and AGND as close as possible to

AVINO.

Place a 0.1µF, X5R/X7R, capacitor

between AVIN and AGND as close as possible to

AVIN. In addition, place a resistor (R_VB) between

VDDB and AVIN, as shown in Figure 1. Enpirion

recommends R_VB=4.75kΩ. In this application,

ENABLE cannot be asserted before PVIN. If no

external enable signal is used, tying ENABLE to

AVIN meets this requirement.

Figure 5: Dual Input Supply (PVIN and AVIN)

Recommended Schematic

Frequency Synchronization

The switching frequency of the EN2340QI can be

phase-locked to an external clock source to move

unwanted beat frequencies out of band. The

internal switching clock of the EN2340QI can be

phase locked to a clock signal applied to the S_IN

pin. An activity detector recognizes the presence of

an external clock signal and automatically phase-

locks the internal oscillator to this external clock.

Phase-lock will occur as long as the input clock

frequency is in the range of 0.9MHz to 1.3MHz.

When no clock is present, the device reverts to the

free running frequency of the internal oscillator.

Adding a resistor (R_FS) to the FADJ pin will adjust

the frequency lower. If a 3KΩ resistor is placed on

FADJ the nominal switching frequency of the

EN2340QI is 1MHz. The efficiency performance of

Dual Input Supply Application (PVIN and AVIN):

In this application, place a 0.1µF, X7R, capacitor

between AVIN and AGND as close as possible to

AVIN. Refer to Figure 5 for a recommended

schematic for a dual input supply application.

For dual input supply applications, the sequencing

of the two input supplies, PVIN and AVIN, is very

important. During power up, neither ENABLE nor

PVIN should be asserted before AVIN. There are

two common acceptable turn-on/off sequences for

the device. ENABLE can be tied to AVIN and come

up with it, and PVIN can be ramped up and down

as needed. Alternatively, PVIN can be brought high

after AVIN is asserted, and the device can be

turned on and off by toggling the ENABLE pin.

the

EN2340QI

for

various

PVIN/VOUT

combinations can be optimized by adjusting the

switching frequency. Table 1 shows recommended

R_FSvalues for various PVIN/VOUT combinations in

order to optimize performance of the EN2340QI.

Enable Operation

The ENABLE pin provides a means to enable

normal operation or to shut down the device. A

logic high will enable the converter into normal

operation. When the ENABLE pin is asserted (high)

the device will undergo a normal soft-start. A logic

low will disable the converter. A logic low will power

down the device in a controlled manner and the

device is subsequently shut down. The ENABLE

signal has to be low for at least the ENABLE

Lockout Time (8ms) in order for the device to be re-

enabled.

PVIN

VOUT

5.0V

3.3V

2.5V

1.2V

1.0V

2.5V

1.2V

1.0V

R_FS

15K

10K

12V

1.65K

1.3K

22.1K

4.87K

3.01K

5V

Pre-Bias Operation

Table 1: Recommended R_FSValues

The EN2340QI is not designed to be turned on into

a pre-biased output voltage.

Enpirion Confidential

www.enpirion.com, Page 11

06878

April 16, 2012

Rev: B

EN2340QI

The OCP trip point is nominally set as specified in

the Electrical Characteristics table. In the event the

OCP circuit trips consistently in normal operation,

the device enters a hiccup mode. While in hiccup

mode, the device is disabled for a short while and

restarted with a normal soft-start. The hiccup time

is approximately 32ms. This cycle can continue

indefinitely as long as the over current condition

persists.

The OCP trip point can be programmed to trip at a

lower level via the RCLX pin. The value of the

resistor connected between RCLX and ground will

determine the OCP trip point. Generally, the higher

the RCLX value, the higher the current limit

threshold. Note that if RCLX pin is left open the

output current will be unlimited and the device will

not have current limit protection. Reference Table 2

for a list of recommended resistor values on RCLX

that will set the OCP trip point at the typical value of

6A, also specified in the Electrical Characteristics

table.

Spread Spectrum Mode

The external clock frequency may be swept

between 0.9MHz and 1.3MHz at repetition

rates of up to 10 kHz in order to reduce EMI

frequency components.

Soft-Start Operation

Soft start is a means to ramp the output voltage

gradually upon start-up. The output voltage rise

time is controlled by the choice of soft-start

capacitor, which is placed between the SS pin (pin

56) and the AGND pin (pin 52).

Rise Time (ms): T_R≈ C_ss[nF] x 0.067

During start-up of the converter, the reference

voltage to the error amplifier is linearly increased to

its final level by an internal current source of

approximately 10µA. Typical soft-start rise time is

~3.2ms with SS capacitor value of 47nF. The rise

time is measured from when V_IN> V_UVLORand

ENABLE pin voltage crosses its logic high

threshold to when V_OUTreaches its programmed

value.

V_OUTRange

R_CLXValue

31.6kꢀ

33.2kꢀ

0.75V < V_OUT≤ 1.2V

1.2V < V_OUT≤ 2.0V

2.0V < V_OUT≤ 5.0V

POK Operation

36.5kꢀ

The POK signal is an open drain signal (requires a

pull up resistor to AVIN or similar voltage) from the

converter indicating the output voltage is within the

specified range. Typically, a 100kꢀ or lower

resistance is used as the pull-up resistor. The POK

signal will be logic high (AVIN) when the output

voltage is above 90% of the programmed V_OUT. If

the output voltage goes outside of this range, the

POK signal will be a logic low.

Table 2: Recommended R_CLXValues vs. V_OUT

Thermal Overload Protection

Thermal shutdown circuit will disable device

operation when the junction temperature exceeds

approximately 150ºC. After a thermal shutdown

event, when the junction temperature drops by

approx 20ºC, the converter will re-start with a

normal soft-start.

Over-Current Protection (OCP)

Input Under-Voltage Lock-Out (UVLO)

The current limit function is achieved by sensing

the current flowing through a sense PFET. When

the sensed current exceeds the current limit, both

power FETs are turned off for the rest of the

switching cycle. If the over-current condition is

removed, the over-current protection circuit will re-

enable PWM operation. If the over-current condition

persists, the circuit will continue to protect the load.

Internal circuits ensure that the converter will not

start switching until the input voltage is above the

specified minimum voltage. Hysteresis, input de-

glitch and output leading edge blanking ensures

high noise immunity and prevents false UVLO

triggers.

Application Information

Output Voltage Programming and Loop

Compensation

components and the equations to calculate their

values. The values recommended for C_Aand R_CA

will vary with each PVIN and VOUT combination.

The EN2340 solution can be optimized for either

smallest size or highest performance. Please see

Table 5 for a list of recommended C_Aand R_CA

values for each solution option.

The EN2340QI output voltage is programmed using

a simple resistor divider network. A phase lead

capacitor (C_A) plus a resistor (R_CA) are required for

stabilizing the loop. Figure 6 shows the required

Enpirion Confidential

www.enpirion.com, Page 12

06878

April 16, 2012

Rev: B

EN2340QI

The EN2340QI output voltage is determined by the

voltage presented at the VFB pin. This voltage is

set by way of a resistor divider between VOUT and

AGND with the midpoint going to VFB.

capacitors in order to provide high frequency

decoupling.

Table

3

contains

a

list of

recommended input capacitors.

Recommended Input Capacitors

The EN2340QI uses a type IV compensation

network.

Most of this network is integrated.

Description

MFG

P/N

22µF, 16V,

X5R, 10%,

1206

22µF, 16V,

X5R, 20%,

1206

However a phase lead capacitor and a resistor are

required in parallel with the upper resistor of the

external feedback network (see Figure 6). Total

compensation is optimized for either low output

ripple or small solution size, and will result in a wide

loop bandwidth and excellent load transient

performance for most applications. See Table 5 for

compensation values for both options based on

input and output voltage conditions.

In some cases modifications to the compensation

may be required. The EN2340QI provides the

capability to modify the control loop response to

allow for customization for specific applications.

For more information, contact Enpirion Applications

Engineering support (techsupport@enpirion.com).

Murata

GRM31CR61C226ME15

EMK316ABJ226ML-T

Taiyo Yuden

Table 3: Recommended Input Capacitors

Output Capacitor Selection

As seen from Table 5, the EN2340QI has been

optimized for use with either two 47µF/1206 or two

22µF/0805 output capacitors. Low ESR ceramic

capacitors are required with X5R or X7R rated

dielectric formulation. Y5V or equivalent dielectric

formulations must not be used as these lose

too much capacitance with frequency,

temperature and bias voltage. Table 4 contains a

list of recommended output capacitors

180

R_A=

(R_Ain kΩ)

VOUT

Output ripple voltage is determined by the

aggregate output capacitor impedance. Capacitor

impedance, denoted as Z, is comprised of

capacitive reactance, effective series resistance,

ESR, and effective series inductance, ESL

reactance.

Round R_Aup to closest

standard value higher than

the calculated value.

V_FB× R_A

R_B=

(V_OUT−V_FB)

Placing output capacitors in parallel reduces the

impedance and will hence result in lower ripple

voltage.

V

is 0.75V

⎛

⎞

FB

⎜

⎟

nominal

⎝

⎠

1

=

+

+ ... +

Z_TotalZ₁Z₂

Z_n

Figure 6: V_OUTResistor Divider & Compensation

Components. RA equation is only valid

for Low V_OUTripple option. For small

solution size, see Table 5.

Recommended Output Capacitors

Description

MFG

P/N

47µF, 6.3V, X5R,

20%, 1206

Murata

GRM31CR60J476ME19L

Input Capacitor Selection

The EN2340QI requires

a

22µF/1206 input

47µF, 10V, X5R,

20%, 1206

Taiyo

Yuden

LMK316BJ476ML-T

ECJ-2FB1A226M

capacitor. Low-cost, low-ESR ceramic capacitors

should be used as input capacitors for this

converter. The dielectric must be X5R or X7R

rated. Y5V or equivalent dielectric formulations

must not be used as these lose too much

capacitance with frequency, temperature and

bias voltage. In some applications, lower value

capacitors are needed in parallel with the larger,

22µF, 10V, X5R,

20%, 0805

Panasonic

22µF, 10V, X5R,

20%, 0805

Taiyo

Yuden

LMK212BJ226MG-T

Table 4: Recommended Output Capacitors

Enpirion Confidential

www.enpirion.com, Page 13

06878

April 16, 2012

Rev: B

EN2340QI

Low V_OUTRipple

C_IN= 1 x 22µF/1206

C_OUT= 2 x 47µF/1206

R_A= 180/(Vout^0.5) kΩ

Smallest Solution Size

C_IN= 1 x 22µF/1206

C_OUT= 2 x 22µF/0805

Nominal

Deviation

(mV)

Nominal

Ripple

(mV)

R_CA

(kꢀ)

Deviation

(mV)

(Note 6)

≤34

33

PVIN

V_OUT

C_A(pF)

Ripple

(kꢀ)

R_A(kꢀ)

C_A(pF)

(mV)

(Note 6)

≤1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

5.0V

≤1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

5.0V

≤1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

5.0V

≤1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

5.0V

≤1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

≤1.0V

1.2V

1.5V

1.8V

2.5V

10

12

30

27

≤5

6

≤47

75

43

27

39

0.1

5.1

0.1

5.1

0.1

5.1

0.1

5.1

0.1

≤10

13

15

18

26

35

42

≤10

13

15

17

25

32

39

≤9

13

14

17

26

30

33

≤10

12

14

16

23

25

30

≤9

12

14

16

19

22

≤9

11

13

14

48

53

54

55

63

97

≤48

49

53

54

66

99

≤45

46

54

56

57

68

98

≤51

51

54

57

64

70

110

≤60

63

65

68

75

85

≤73

75

76

80

88

15

22

27

39

47

18

22

27

33

47

56

33

39

47

56

27

24

18

8.2

22

20

18

15

10

18

16

12

5

6

8

11

18

≤4

5

6

56

51

75

27

75

56

51

75

27

30

75

56

75

100

91

39

33

22

47

39

22

38

41

59

63

115

≤35

37

38

44

59

63

128

≤35

39

43

50

70

83

140

≤41

43

46

53

71

85

127

≤46

51

56

61

83

106

≤56

63

70

78

14V

12V

10V

8.0V

7

10

16

≤3

4

5

6

7

9

14

≤3

4

5

6

8

10

≤3

4

5

82

100

56

47

33

100

82

68

82

10

100

4.3

8.2

75

56

100

91

100

82

100

6.6V

5V

5

6

≤3

3

4

98

Table 5: R_A, C_A, and R_CAValues for Various PVIN/VOUT Combinations: Low V_OUTRipple vs. Smallest Solution Size. See

Figure 6. Use the equations in Figure 6 to calculate R_A(for low V_OUTripple option) and R_B.

Note 6: Nominal Deviation is for a 2A load transient step.

Enpirion Confidential

www.enpirion.com, Page 14

06878

April 16, 2012

Rev: B

EN2340QI

Thermal Considerations

Thermal considerations are important power supply

design facts that cannot be avoided in the real

world. Whenever there are power losses in a

system, the heat that is generated by the power

dissipation needs to be accounted for. The Enpirion

PowerSoC helps alleviate some of those concerns.

For V_IN= 12V, V_OUT= 3.3V at 4A, η ≈ 90%

η = P_OUT/ P_IN= 90% = 0.9

P_IN= P_OUT/ η

P_IN≈ 13.2W / 0.9 ≈ 14.67W

The power dissipation (P_D) is the power loss in the

system and can be calculated by subtracting the

output power from the input power.

The Enpirion EN2340QI DC-DC converter is

packaged in an 8x11x3mm 68-pin QFN package.

The QFN package is constructed with copper lead

frames that have exposed thermal pads. The

exposed thermal pad on the package should be

soldered directly on to a copper ground pad on the

printed circuit board (PCB) to act as a heat sink.

The recommended maximum junction temperature

for continuous operation is 125°C. Continuous

operation above 125°C may reduce long-term

reliability. The device has a thermal overload

protection circuit designed to turn off the device at

an approximate junction temperature value of

150°C.

P_D= P_IN– P_OUT

≈ 14.67W – 13.2W ≈ 1.47W

With the power dissipation known, the temperature

rise in the device may be estimated based on the

theta JA value (θ_JA). The θ_JAparameter estimates

how much the temperature will rise in the device for

every watt of power dissipation. The EN2340QI has

a θ_JAvalue of 18 ºC/W without airflow.

Determine the change in temperature (ΔT) based

on P_Dand θ_JA.

ΔT = P_Dx θ_JA

The EN2340QI is guaranteed to support the full 4A

output current up to 85°C ambient temperature.

The following example and calculations illustrate

the thermal performance of the EN2340QI.

ΔT ≈ 1.47W x 18°C/W = 26.46°C ≈ 27°C

The junction temperature (T_J) of the device is

approximately the ambient temperature (T_A) plus

the change in temperature. We assume the initial

ambient temperature to be 25°C.

Example:

V_IN= 12V

T_J= T_A+ ΔT

V

_OUT= 3.3V

_OUT= 4A

First calculate the output power.

_OUT= 3.3V x 4A = 13.2W

T_J≈ 25°C + 27°C ≈ 52°C

I

The maximum operating junction temperature

(T_JMAX) of the device is 125°C, so the device can

operate at a higher ambient temperature. The

maximum ambient temperature (T_AMAX) allowed can

be calculated.

P

Next, determine the input power based on the

efficiency (η) shown in Figure 7.

T_AMAX= T_JMAX– P_Dx θ_JA

≈ 125°C – 27°C ≈ 98°C

Efficiency vs. Output Current

100

90

The maximum ambient temperature the device can

reach is 98°C given the input and output conditions.

Note that the efficiency will be slightly lower at

higher temperatures and this calculation is an

estimate.

80

70

60

50

40

30

20

10

0

90%

CONDITIONS

V_IN= 12.0V

VOUT = 3.3V

0

0.5

1

1.5

2

2.5

3

3.5

4

OUTPUT CURRENT(A)

Figure 7: Efficiency vs. Output Current

Enpirion Confidential

www.enpirion.com, Page 15

06878

April 16, 2012

Rev: B

EN2340QI

Engineering Schematic

Figure 8: Engineering Schematic with Engineering Notes

Enpirion Confidential

www.enpirion.com, Page 16

06878

April 16, 2012

Rev: B

EN2340QI

Layout Recommendation

Recommendation 4: The thermal pad underneath

the component must be connected to the system

ground plane through as many vias as possible.

The drill diameter of the vias should be 0.33mm,

and the vias must have at least 1 oz. copper plating

on the inside wall, making the finished hole size

around 0.20-0.26mm. Do not use thermal reliefs or

spokes to connect the vias to the ground plane.

This connection provides the path for heat

dissipation from the converter.

Recommendation 5: Multiple small vias (the same

size as the thermal vias discussed in

recommendation 4) should be used to connect

ground terminal of the input capacitor and output

capacitors to the system ground plane. It is

preferred to put these vias along the edge of the

GND copper closest to the +V copper. These vias

connect the input/output filter capacitors to the

GND plane, and help reduce parasitic inductances

in the input and output current loops. If vias cannot

be placed under the capacitors, then place them on

both sides of the slit in the top layer PGND copper.

Recommendation 6: AVIN is the power supply for

the small-signal control circuits. It should be

connected to the input voltage at a quiet point. In

Figure 9 this connection is made at the input

capacitor.

Recommendation 7: The layer 1 metal under the

device must not be more than shown in Figure 9.

Refer to the section regarding Exposed Metal on

Bottom of Package. As with any switch-mode

DC/DC converter, try not to run sensitive signal or

control lines underneath the converter package on

other layers.

Recommendation 8: The V_OUTsense point should

be just after the last output filter capacitor. Keep the

sense trace short in order to avoid noise coupling

into the node. Contact Enpirion Technical Support

for any remote sensing applications.

Recommendation 9: Keep R_A, C_A, R_B, and R_CA

close to the VFB pin (Refer to Figure 9). The VFB

pin is a high-impedance, sensitive node. Keep the

trace to this pin as short as possible. Whenever

possible, connect R_Bdirectly to the AGND pins 52

and 53 instead of going through the GND plane.

Figure 9: Top Layer Layout with Critical Components

(Top View). See Figure 8 for corresponding schematic.

This layout only shows the critical components and

top layer traces for minimum footprint in single-

supply mode with ENABLE tied to AVIN. Alternate

circuit configurations & other low-power pins need

to be connected and routed according to customer

application. Please see the Gerber files at

www.enpirion.com for details on all layers.

Recommendation 1: Input and output filter

capacitors should be placed on the same side of

the PCB, and as close to the EN2340QI package

as possible. They should be connected to the

device with very short and wide traces. Do not use

thermal reliefs or spokes when connecting the

capacitor pads to the respective nodes. The +V and

GND traces between the capacitors and the

EN2340QI should be as close to each other as

possible so that the gap between the two nodes is

minimized, even under the capacitors.

Recommendation 2: The PGND connections for

the input and output capacitors on layer 1 need to

have a slit between them in order to provide some

separation between input and output current loops.

Recommendation 3: The system ground plane

should be the first layer immediately below the

surface layer. This ground plane should be

continuous and un-interrupted below the converter

and the input/output capacitors.

Recommendation 10: Follow all the layout

recommendations as close as possible to optimize

performance. Enpirion provides schematic and

layout reviews for all customer designs. Contact

Enpirion Applications Engineering for detailed

support (techsupport@enpirion.com).

Enpirion Confidential

www.enpirion.com, Page 17

06878

April 16, 2012

Rev: B

EN2340QI

Design Considerations for Lead-Frame Based Modules

Exposed Metal on Bottom of Package

Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in

overall foot print. However, they do require some special considerations.

In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame

cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several

small pads being exposed on the bottom of the package, as shown in Figure 10.

Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.

The PCB top layer under the EN2340QI should be clear of any metal (copper pours, traces, or vias) except for

the thermal pad. The “shaded-out” area in Figure 10 represents the area that should be clear of any metal on

the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted

connections even if it is covered by soldermask.

The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from

causing bridging between adjacent pins or other exposed metal under the package. Please consult the

Enpirion Manufacturing Application Note for more details and recommendations.

Figure 10: Lead-Frame exposed metal (Bottom View)

Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.

Enpirion Confidential

www.enpirion.com, Page 18

06878

April 16, 2012

Rev: B

EN2340QI

Recommended PCB Footprint

Figure 11: EN2340QI PCB Footprint (Top View)

Enpirion Confidential

www.enpirion.com, Page 19

06878

April 16, 2012

Rev: B

EN2340QI

Package and Mechanical

Figure 12: EN2340QI Package Dimensions (Bottom View)

Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm

Contact Information

Enpirion, Inc.

Perryville III Corporate Park

53 Frontage Road - Suite 210

Hampton, NJ 08827 USA

Phone: 1.908.894.6000

Fax: 1.908.894.6090

Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is

believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may

result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment

used in hazardous environment without the express written authority from Enpirion

Enpirion Confidential

www.enpirion.com, Page 20

06878

April 16, 2012

Rev: B


型号：	EN2340QI
厂家：	ENPIRION, INC.
描述：	204A Voltage Mode Synchronous Buck PWM 204A电压模式同步降压PWM
文件：	总20页 (文件大小：1108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EN2340QI [ENPIRION]

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