MC-4532DA726PFB-A10 [ELPIDA]
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE; 32 m字72 - BIT同步动态RAM模块登记注册类型型号: | MC-4532DA726PFB-A10 |
厂家: | ELPIDA MEMORY |
描述: | 32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
文件: | 总16页 (文件大小:180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532DA726
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4532DA726 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of
128M SDRAM: µPD45128441 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
Module type
MC-4532DA726EFB-A80
MC-4532DA726EFB-A10
MC-4532DA726PFB-A80
MC-4532DA726PFB-A10
MC-4532DA726XFB-A80
MC-4532DA726XFB-A10
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
100 MHz
100 MHz
77 MHz
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
PC100 Registered DIMM
Rev. 1.2 Compliant
125 MHz
100 MHz
100 MHz
77 MHz
125 MHz
100 MHz
100 MHz
77 MHz
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0072N10 (1st edition)
This product became EOL in March, 2004.
(Previous No. M13633EJ8V0DS00)
Date Published January 2001 CP(K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4532DA726
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ± 10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
Ordering Information
Part number
Clock frequency
(MAX.)
Package
Mounted devices
MC-4532DA726EFB-A80
MC-4532DA726EFB-A10
MC-4532DA726PFB-A80
MC-4532DA726PFB-A10
MC-4532DA726XFB-A80
MC-4532DA726XFB-A10
125 MHz
100 MHz
125 MHz
100 MHz
125 MHz
100 MHz
168-pin Dual In-line Memory Module 18 pieces of µPD45128441G5 (Rev. E)
(Socket Type)
(10.16 mm (400) TSOP (II))
Edge connector: Gold plated
43.18 mm height
18 pieces of µPD45128441G5 (Rev. P)
(10.16 mm (400) TSOP (II))
18 pieces of µPD45128441G5 (Rev. X)
(10.16 mm (400) TSOP (II))
Data Sheet E0072N10
2
MC-4532DA726
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ0
DQ1
DQ2
DQ3
Vcc
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
V
SS
VSS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
CB4
DQ14
DQ15
CB0
CB5
CB1
V
SS
V
SS
NC
NC
Vcc
NC
NC
Vcc
/WE
/CAS
DQMB4
DQMB5
NC
DQMB0
DQMB1
/CS0
NC
/RAS
VSS
V
SS
A0
A2
A1
A3
A4
A5
A6
A7
A8
A9
A10
BA0(A13)
A11
Vcc
BA1(A12)
Vcc
A0 - A11
: Address Inputs
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CLK0
[Row: A0 - A11, Column: A0 - A9, A11]
VSS
VSS
CKE0
NC
NC
/CS2
DQMB2
DQMB3
NC
BA0 (A13), BA1(A12) : SDRAM Bank Select
DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs
DQMB6
DQMB7
NC
Vcc
Vcc
NC
NC
CLK0 - CLK3
CKE0
: Clock Input
NC
NC
CB6
CB7
CB2
: Clock Enable Input
: Write Protect
CB3
V
SS
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
WP
/CS0, /CS2
/RAS
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
DQ52
NC
DQ20
NC
NC
NC
/CAS
REGE
NC
V
SS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
/WE
DQMB0 - DQMB7
SA0 - SA2
SDA
: DQ Mask Enable
: Address Input for EEPROM
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
V
SS
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
SCL
VCC
V
SS
VSS
CLK3
NC
CLK2
NC
VSS
: Ground
SA0
SA1
SA2
Vcc
WP
SDA
SCL
Vcc
REGE
NC
: Register / Buffer Enable
: No Connection
Data Sheet E0072N10
3
MC-4532DA726
Block Diagram
/RCS0
RDQMB4
RDQMB0
DQ 3
DQ 2
DQ 1
DQ 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 32
DQ 33
DQ 34
DQ 35
DQM
D0
DQM
DQM
/CS
/CS
/CS
/CS
D9
DQ 7
DQ 6
DQ 5
DQ 4
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 36
DQ 37
DQ 38
DQ 39
DQM
D1
D
10
RDQMB1
RDQMB5
DQ 11
DQ 10
DQ 9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 40
DQ 41
DQ 42
DQ 43
DQ 0
DQ 1
DQ 2
DQ 3
DQM
/CS
/CS
/CS
DQM
/CS
/CS
/CS
D1 - D17
Register1, Register2, PLL
C
V
CC
D
2
D11
D1 - D17
Register1, Register2, PLL
DQ 8
V
SS
DQ 45
DQ 44
DQ 46
DQ 47
DQ 0
DQ 1
DQ 2
DQ 3
DQ 15
DQ 14
DQ 12
DQ 13
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D3
DQM
D12
SERIAL PD
CB 5
CB 4
CB 7
CB 6
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
CB 2
CB 3
CB 0
CB 1
DQM
SDA
SCL
D
4
D13
WP
A0
A1
A2
47kΩ
SA0 SA1 SA2
/RCS2
RDQMB2
RDQMB6
DQ 18
DQ 19
DQ 17
DQ 16
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 48
DQ 49
DQ 50
DQ 51
DQM
DQM
D5
/CS
/CS
/CS
/CS
DQ 1
DQ 2
DQ 3
D14
10 Ω
CLK1 - CLK3
12pF
DQ 23
DQ 22
DQ 21
DQ 20
DQ 0
DQ 1
DQ 2
DQ 3
DQ 52
DQ 53
DQ 54
DQ 55
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D6
DQM
D15
RDQMB3
RDQMB7
DQ 27
DQ 26
DQ 25
DQ 24
DQ 56
DQ 57
DQ 58
DQ 59
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D16
/CS
/CS
DQM
D7
/CS
/CS
10 Ω
CLK : D0, D1, D9
CLK0
CLK : D2, D10, D11
CLK : D3, D4, D12
CLK : D5, D13, D14
CLK : D6, D7, D15
CLK : D8, D16, D17
CLK : Register1, Register2
PLL
DQ 31
DQ 30
DQ 29
DQ 28
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D8
DQM
D17
RA7 - RA11,
RBA0, RBA1
A7 - A11,
BA0, BA1
A0 - A6 : D0 - D17
A0 - A6
RA0 - RA6
A7 - A11, BA0, BA1 : D0 - D17
CKE : D0 - D17
/RAS : D0 - D17
/CAS : D0 - D17
/WE : D0 - D17
RCKE0
/RRAS
/RCAS
/RWE
/RAS
/CAS
/WE
CKE0
RDQMB 2, RDQMB 3,
RDQMB 6, RDQMB 7
DQMB2, DQMB3,
DQMB6, DQMB7
Register1
Register2
/CS2
/RCS2
RDQMB0, RDQMB1,
RDQMB4, RDQMB5
DQMB0, DQMB1,
DQMB4, DQMB5
/RCS0
/CS0
LE
REGE
LE
VCC
10kΩ
Remarks 1. The value of all resistors of DQs is 10 Ω.
2. D0 - D17: µPD45128441 (8M words × 4 bits × 4 banks)
3. REGE ≤ VIL: Buffer mode
REGE ≥ VIH: Register mode
4. Register: HD74ALVC16835
PLL: HD74CDC2509B
Data Sheet E0072N10
4
MC-4532DA726
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
CC
V
T
V
V
IO
PD
TA
mA
W
Power dissipation
21
Operating ambient temperature
Storage temperature
0 to 70
°C
°C
Tstg
–55 to +125
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
IH
V
CC
High level input voltage
Low level input voltage
Operating ambient temperature
V
+ 0.3
V
IL
V
+0.8
70
V
A
T
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
Test condition
MIN.
4
TYP.
MAX.
10
Unit
pF
CI1
A0 – A11, BA0(A13), BA1 (A12),
/RAS, /CAS, /WE
CI2
CI3
CI4
CI5
CI/O
CLK0
15
7
25
20
10
10
13
CKE0
/CS0, /CS2
4
DQMB0 -DQMB7
DQ0 - DQ63, CB0 - CB7
3
Data input/output capacitance
5
pF
Data Sheet E0072N10
5
MC-4532DA726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
ICC1
Test condition
Grade MIN. MAX. Unit Notes
Operating current
Burst length = 1
tRC ≥ tRC (MIN.), IO = 0 mA
/CAS latency = 2 -A80
2,100 mA
2,100
1
-A10
/CAS latency = 3 -A80
-A10
2,100
2,100
Precharge standby current in
power down mode
ICC2P
CKE VIL (MAX.), tCK = 15 ns
268
98
mA
mA
≤
CC2
IL (MAX.) CK
I
PS CKE ≤ V
, t = ∞
Precharge standby current in
non power down mode
ICC2N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
610
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ ,
224
Input signals are stable.
Active standby current in
power down mode
ICC3P
CKE ≤ VIL (MAX.), tCK = 15 ns
340
152
790
mA
mA
ICC3PS CKE VIL (MAX.), tCK =
≤
∞
CC3
IH (MIN.) CK
IH (MIN.)
Active standby current in
non power down mode
I
N
CKE ≥ V
, t = 15 ns, /CS ≥ V
,
Input signals are changed one time during 30 ns.
CC3
IH (MIN.) CK
I
NS CKE ≥ V
, t = ∞ ,
440
Input signals are stable.
CC4
CK
CK (MIN.)
O
Operating current
(Burst mode)
I
t
≥ t
, I = 0 mA
/CAS latency = 2 -A80
2,190 mA
1,830
2
3
-A10
/CAS latency = 3 -A80
-A10
2,640
2,280
CBR (Auto) Refresh current
ICC5
tRC tRC (MIN.)
/CAS latency = 2 -A80
-A10
4,440 mA
4,440
≥
/CAS latency = 3 -A80
-A10
4,440
4,440
Self refresh current
ICC6
CKE 0.2 V
286
+10
+20
+1.5
mA
≤
I (L)
I
Input leakage current
I
V = 0 to 3.6 V, All other pins not under test = 0 V
–10
–20
–1.5
2.4
µA
Input leakage current (CKE0)
Output leakage current
High level output voltage
Low level output voltage
O (L)
I
O
D
OUT
is disabled, V = 0 to 3.6 V
µA
V
VOH
VOL
IO = –4.0 mA
IO = +4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet E0072N10
6
MC-4532DA726
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Value
2.4 / 0.4
1.4
Unit
V
V
1
ns
V
Output timing measurement reference level
1.4
t
CK
t
CH
t
CL
2.4 V
CLK
1.4 V
0.4 V
t
SETUP
t
HOLD
2.4 V
1.4 V
0.4 V
Input
t
AC
t
OH
Output
Data Sheet E0072N10
7
MC-4532DA726
Synchronous Characteristics
Parameter
Symbol
tCK3
-A80
-A10
Unit
Note
MIN.
8
MAX.
MIN.
10
MAX.
Clock cycle time
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
(125 MHz)
(100 MHz)
ns
ns
ns
ns
MHz
%
CK2
t
10
(100 MHz)
13
(77 MHz)
Access time from CLK
tAC3
tAC2
6
6
6
7
1
1
Input clock frequency
Input CLK duty cycle
Data-out hold time
50
40
3
125
60
50
40
3
100
60
OH3
/CAS latency = 3
/CAS latency = 2
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
tOH2
tLZ
3
3
Data-out low-impedance time
Data-out high- impedance time
0
0
HZ3
/CAS latency = 3
/CAS latency = 2
t
3
6
6
3
6
7
tHZ2
3
3
DS
t
Data-in setup time
Data-in hold time
2
2
tDH
tAS
1
1
Address setup time
Address hold time
CKE setup time
2
2
AH
t
1
1
tCKS
tCKH
2
2
CKE hold time
1
1
CKSP
CKE setup time (Power down exit)
t
2
2
Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 -
DQMB7) setup time
tCMS
2
2
Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 -
DQMB7) hold time
tCMH
1
1
ns
Note 1. Output load
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
Data Sheet E0072N10
8
MC-4532DA726
Asynchronous Characteristics
Parameter
Symbol
tRC
-A80
-A10
Unit
Note
MIN.
MAX.
MIN.
MAX.
ACT to REF/ACT command period (Operation)
REF to REF/ACT command period (Refresh)
ACT to PRE command period
70
70
ns
ns
RC1
t
70
78
tRAS
tRP
48
120,000
50
120,000
ns
PRE to ACT command period
20
20
ns
RCD
Delay time ACT to READ/WRITE command
ACT(one) to ACT(another) command period
Data-in to PRE command period
t
20
20
ns
tRRD
16
20
ns
DPL
t
−1CLK+8
−1CLK+10
ns
Data-in to ACT(REF) command
period (Auto precharge)
/CAS latency = 3
/CAS latency = 2
tDAL3
tDAL2
20
20
2
20
20
2
ns
ns
RSC
t
Mode register set cycle time
Transition time
CLK
ns
tT
0.5
30
64
1
30
64
REF
Refresh time (4,096 refresh cycles)
t
ms
Data Sheet E0072N10
9
MC-4532DA726
Serial PD
(1/2)
Byte No.
0
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
3
4
5
6
7
8
9
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
0BH
01H
48H
00H
01H
80H
A0H
60H
60H
02H
80H
04H
04H
01H
8FH
04H
06H
01H
01H
1FH
0EH
A0H
D0H
60H
70H
00H
14H
14H
10H
14H
14H
14H
30H
32H
40H
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
256 bytes
SDRAM
12 rows
11 columns
1 bank
72 bits
0
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 Cycle time
-A80
-A10
-A80
-A10
10 ns
6 ns
10
CL = 3 Access time
6 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
ECC
Normal
x4
SDRAM width
Error checking SDRAM width
Minimum clock delay
x4
1 clock
1, 2, 4, 8, F
4 banks
2, 3
Burst length supported
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
/WE latency supported
SDRAM module attributes
0
0
Registered
SDRAM device attributes : General
CL = 2 Cycle time
-A80
10 ns
13 ns
6 ns
-A10
-A80
-A10
24
CL = 2 Access time
7 ns
25-26
RP(MIN.)
27
28
29
30
31
t
-A80
-A10
-A80
-A10
-A80
-A10
-A80
-A10
20 ns
20 ns
tRRD(MIN.)
16 ns
20 ns
tRCD(MIN.)
20 ns
20 ns
tRAS(MIN.)
48 ns
50 ns
Module bank density
256M bytes
Data Sheet E0072N10
10
MC-4532DA726
(2/2)
Byte No.
32
Function Described
Hex
20H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Command and address signal input
0
0
1
0
0
0
0
0
2 ns
1 ns
setup time
33
Command and address signal input hold
time
10H
0
0
0
1
0
0
0
0
34
35
Data signal input setup time
Data signal input hold time
20H
10H
00H
12H
3AH
A0H
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
2 ns
1 ns
36-61
62
SPD revision
1.2 A
63
Checksum for bytes 0 - 62
-A80
-A10
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
Intel specification /CAS
latency support
64H
87H
85H
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
1
100 MHz
-A80
-A10
Timing Chart
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0072N10
11
MC-4532DA726
Package Drawing
168-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Y
Z
N
M1 (AREA B)
R
Q
L
M
T
A
B
S
M2 (AREA A)
J
H
(OPTIONAL HOLES)
U
K
C
E
B
I
G
D
A1 (AREA A)
ITEM MILLIMETERS
A
A1
B
133.35
133.35±0.13
11.43
C
36.83
D
6.35
D1
D2
E
2.0
detail of A part
W
detail of B part
D2
3.125
54.61
G
H
6.35
1.27 (T.P.)
8.89
I
J
24.495
42.18
K
L
17.78
M
M1
M2
N
43.18±0.13
23.40
V
P
19.78
X
D1
4.0 MAX.
1.0
P
Q
R
R2.0
4.0±0.10
φ
S
3.0
T
1.27±0.1
4.0 MIN.
U
V
0.2±0.15
1.0±0.05
2.54±0.10
3.0 MIN.
W
X
Y
Z
3.0 MIN.
M168S-50A107
Data Sheet E0072N10
12
MC-4532DA726
[MEMO]
Data Sheet E0072N10
13
MC-4532DA726
[MEMO]
Data Sheet E0072N10
14
MC-4532DA726
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet E0072N10
15
MC-4532DA726
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
•
The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
M8E 00. 4
相关型号:
MC-4532DA727-A75
Synchronous DRAM Module, 32MX72, 5.4ns, MOS, 43.18 MM HEIGHT, 1.27 MM PITCH, DIMM-168
ELPIDA
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