MC-4532DA727EF-A75 [ELPIDA]
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE; 32 m字72 - BIT同步动态RAM模块登记注册类型
| 型号： | MC-4532DA727EF-A75 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
| 文件： | 总15页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532DA727
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4532DA727 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of
128M SDRAM: µPD45128441 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK.
Part number
MC-4532DA727EF-A75
MC-4532DA727PF-A75
MC-4532DA727XF-A75
MC-4532DA727XFA-A75
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
133 MHz
100 MHz
133 MHz
100 MHz
133 MHz
100 MHz
133 MHz
100 MHz
5.4 ns
6.0 ns
5.4 ns
6.0 ns
5.4 ns
6.0 ns
5.4 ns
6.0 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0073N20 (Ver.2.0)
Date Published September 2001 (K)
Printed in Japan
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4532DA727
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-4532DA727EF-A75
MC-4532DA727PF-A75
MC-4532DA727XF-A75
MC-4532DA727XFA-A75
133 MHz
168-pin Dual In-line Memory Module 18 pieces of µPD45128441G5 (Rev. E)
(Socket Type)
(10.16mm (400) TSOP (II))
Edge connector: Gold plated
43.18 mm height
18 pieces of µPD45128441G5 (Rev. P)
(10.16mm (400) TSOP (II))
18 pieces of µPD45128441G5 (Rev. X)
(10.16mm (400) TSOP (II))
30.48 mm height
18 pieces of µPD45128441G5 (Rev. X)
(10.16mm (400) TSOP (II))
Data Sheet E0073N20
2
MC-4532DA727
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
V
SS
V
SS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
CB4
DQ14
DQ15
CB0
CB5
CB1
V
SS
V
SS
NC
NC
Vcc
NC
NC
Vcc
/WE
/CAS
DQMB4
DQMB5
NC
DQMB0
DQMB1
/CS0
NC
/RAS
V
SS
V
SS
A0
A2
A1
A3
A4
A0 - A11
: Address Inputs
A5
A6
A7
A8
A9
[Row: A0 - A11, Column: A0 - A9, A11]
BA0(A13), BA1(A12) : SDRAM Bank Select
DQ0-DQ63, CB0-CB7: Data Inputs/Outputs
A10
BA0(A13)
A11
Vcc
BA1(A12)
Vcc
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CLK0
V
SS
VSS
CLK0 - CLK3
CKE0
: Clock Input
CKE0
NC
NC
/CS2
DQMB2
DQMB3
NC
: Clock Enable Input
: Write Protect
DQMB6
DQMB7
NC
WP*
Vcc
Vcc
NC
NC
NC
NC
/CS0, /CS2
/RAS
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
CB6
CB7
CB2
CB3
V
SS
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
/CAS
/WE
DQ52
NC
DQ20
NC
DQMB0 - DQMB7
SA0 - SA2
SDA
: DQ Mask Enable
: Address Input for EEPROM
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
NC
NC
REGE
NC
V
SS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
V
SS
VSS
SCL
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
VCC
VSS
: Ground
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
REGE
NC
: Register / Buffer Enable
: No Connection
SS
V
SS
V
CLK3
NC
CLK2
NC
*
* : 81 pin of MC-4532DA727XFA is NC pin.
SA0
SA1
SA2
Vcc
WP
SDA
SCL
Vcc
Data Sheet E0073N20
3
MC-4532DA727
Block Diagram
/RCS0
RDQMB4
RDQMB0
DQ 3
DQ 2
DQ 1
DQ 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 32
DQ 33
DQ 34
DQ 35
DQM
D0
DQM
DQM
/CS
/CS
/CS
/CS
D9
DQ 7
DQ 6
DQ 5
DQ 4
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 36
DQ 37
DQ 38
DQ 39
DQM
D1
D
10
D1 - D17
Register1, Register2, Register3,
PLL
V
CC
SS
RDQMB1
RDQMB5
C
DQ 11
DQ 10
DQ 9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 40
DQ 41
DQ 42
DQ 43
DQ 0
DQ 1
DQ 2
DQ 3
D1 - D17
Register1, Register2, Register3,
PLL
DQM
/CS
/CS
/CS
DQM
/CS
/CS
/CS
V
D
2
D11
DQ 8
DQ 45
DQ 44
DQ 46
DQ 47
DQ 0
DQ 1
DQ 2
DQ 3
DQ 15
DQ 14
DQ 12
DQ 13
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D3
DQM
D12
SERIAL PD
SDA
WP
SCL
A0
A1
A2
CB 5
CB 4
CB 7
CB 6
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
CB 2
CB 3
CB 0
CB 1
DQM
47kΩ
D
4
D13
SA0 SA1 SA2
/RCS2
MC-4532DA727XFA
have no this circuit.
RDQMB6
RDQMB2
DQ 18
DQ 19
DQ 17
DQ 16
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 48
DQ 49
DQ 50
DQ 51
DQM
DQM
D5
/CS
/CS
/CS
/CS
DQ 1
DQ 2
DQ 3
D14
10 Ω
CLK1 - CLK3
12 pF
DQ 23
DQ 22
DQ 21
DQ 20
DQ 0
DQ 1
DQ 2
DQ 3
DQ 52
DQ 53
DQ 54
DQ 55
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D6
DQM
D15
RDQMB3
RDQMB7
10 Ω
DQ 27
DQ 26
DQ 25
DQ 24
DQ 56
DQ 57
DQ 58
DQ 59
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
CLK : D0, D1, D9
CLK : D2, D10, D11
CLK : D3, D4, D12
CLK : D5, D13, D14
CLK : D6, D7, D15
CLK : D8, D16, D17
CLK : Register1, Register2,Register3
CLK0
DQM
D16
/CS
/CS
DQM
D7
/CS
/CS
PLL
DQ 31
DQ 30
DQ 29
DQ 28
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D8
DQM
D17
A0 - A3, A10 : D0 - D3, D9 - D13
BA0, BA1
RA0A - RA3A, RA10A
RBA0A, RBA1A
RA0B - RA3B, RA10B
RBA0B, RBA1B
A0 - A3,A10
BA0, BA1
A0 - A3, A10 : D4 - D8, D14 - D17
BA0, BA1
A0 - A3, A10
BA0, BA1
A4 - A9, A11 : D4 - D8, D14 - D17
RA4B - RA9B, RA11B
A4 - A9, A11 : D0 - D3, D9 - D13
RA4A - RA9A, RA11A
/RRASA
A4 - A9, A11
A4 - A9, A11
/RRASB
/RCASB
/RAS : D4 - D8, D14 - D17
/RAS : D0 - D3, D9 - D13
/RAS
/RAS
Register1
Register2
/LE
/CAS : D4 - D8, D14 - D17
/CAS
/CAS
/RCASA
RCKE0A
RCKE0B
/CAS : D0 - D3, D9 - D13
CKE : D0 - D4, D9 - D12
CKE : D5 - D8, D13 - D17
CKE0
DQMB0 - DQMB7
/CS0, /CS2
/WE
RDQMB0 - RDQMB7
REGE
CC
/LE
V
/RCS0, /RCS2
Register3
/LE
/WE : D0 - D3, D9 - D13
CKE : D4 - D8, D14 - D17
/RWEA
/RWEB
10kΩ
Remarks 1. The value of all resistors of DQs is 10 Ω.
2. D0 - D17: µPD45128441 (8M words × 4 bits × 4 banks)
3. REGE ≤ VIL: Buffer mode
REGE ≥ VIH: Register mode
Data Sheet E0073N20
4
MC-4532DA727
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
22
Operating ambient temperature
Storage temperature
TA
0 to 70
°C
°C
Tstg
–55 to +125
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
Low level input voltage
Operating ambient temperature
VCC + 0.3
+ 0.8
70
V
VIL
V
TA
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
7
TYP.
MAX.
20
Unit
pF
Input capacitance
A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
CI2
CI3
CI4
CI5
CI/O
CLK0
15
7
25
20
10
12
13
CKE0
/CS0, /CS2
4
DQMB0-DQMB7
DQ0 - DQ63, CB0 - CB7
3
Data input/output capacitance
5
pF
Data Sheet E0073N20
5
MC-4532DA727
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
ICC1
Test condition
Grade MIN. MAX. Unit Notes
Operating current
Burst length = 1
/CAS latency = 2 -A75
/CAS latency = 3 -A75
2,200 mA
2,290
1
tRC ≥ tRC (MIN.), IO = 0 mA
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL (MAX.), tCK = 15 ns
268
98
mA
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞
ICC2N
Precharge standby current in
non power down mode
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
610
mA
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
ICC3P CKE ≤ VIL (MAX.), tCK = 15 ns
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞
ICC3N
224
340
152
790
Active standby current in
power down mode
mA
mA
Active standby current in
non power down mode
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
440
Operating current
ICC4
tCK ≥ tCK (MIN.), IO = 0 mA
/CAS latency = 2 -A75
/CAS latency = 3 -A75
/CAS latency = 2 -A75
/CAS latency = 3 -A75
2,290 mA
2,920
2
3
(Burst mode)
CBR (Auto) Refresh current
ICC5
tRC ≥ tRC (MIN.)
4,540 mA
4,720
Self refresh current
ICC6
II (L)
CKE ≤ 0.2 V
286
+20
+1.5
mA
µA
µA
V
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = –4.0 mA
–20
–1.5
2.4
IO (L)
VOH
VOL
IO = +4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet E0073N20
6
MC-4532DA727
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Value
2.4 / 0.4
1.4
Unit
V
V
1
ns
V
Output timing measurement reference level
1.4
t
CK
t
CH
t
CL
2.4 V
CLK
1.4 V
0.4 V
t
SETUP
t
HOLD
2.4 V
1.4 V
0.4 V
Input
t
AC
t
OH
Output
Data Sheet E0073N20
7
MC-4532DA727
Synchronous Characteristics
Parameter
Symbol
-A75
Unit
Note
MIN.
7.5
MAX.
Clock cycle time
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
tCK3
tCK2
tAC3
tAC2
(133 MHz)
(100 MHz)
5.4
ns
ns
ns
ns
MHz
%
10
Access time from CLK
1
1
6.0
Input clock frequency
50
45
133
Input CLK duty cycle
55
Data-out hold time
tOH
tLZ
2.7
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Data-out low-impedance time
Data-out high-impedance time
/CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
3.0
3.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
1.5
5.4
6.0
Data-in setup time
Data-in hold time
tDH
Address setup time
Address hold time
CKE setup time
tAS
tAH
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0, /CS2, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
0.8
ns
Note 1. Output load
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
Data Sheet E0073N20
8
MC-4532DA727
Asynchronous Characteristics
Parameter
Symbol
-A75
Unit
Note
MIN.
67.5
67.5
45
MAX.
ACT to REF/ACT command period (operation)
REF to REF/ACT command period (refresh)
ACT to PRE command period
tRC
tRC1
tRAS
tRP
ns
ns
ns
ns
ns
ns
ns
ns
ns
120,000
PRE to ACT command period
20
Delay time ACT to READ/WRITE command
ACT(one) to ACT(another) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
tDAL3
tDAL2
tRSC 2
tT
20
15
8
Data-in to ACT(REF) command
period (Auto precharge)
/CAS latency = 3
/CAS latency = 2
1CLK+22.5
1CLK+20
CLK
1
Mode register set cycle time
Transition time
0.5
30
64
ns
Refresh time (4,096 refresh cycles)
tREF
ms
Note 1. This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
Data Sheet E0073N20
9
MC-4532DA727
Serial PD
(1/2)
Byte No.
0
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
0BH
01H
48H
00H
01H
75H
54H
02H
80H
04H
04H
01H
8FH
04H
06H
01H
01H
1FH
0EH
A0H
60H
00H
14H
0FH
14H
2DH
40H
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
1
0
1
0
256 bytes
SDRAM
12 rows
11 columns
1 bank
72 bits
0
3
4
Number of columns
Number of banks
5
6
Data width
7
Data width (continued)
Voltage interface
8
LVTTL
7.5 ns
5.4 ns
ECC
9
CL = 3 Cycle time
-A75
-A75
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25-26
27
28
29
30
31
CL = 3 Access time
DIMM configuration type
Refresh rate/type
Normal
×4
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
/WE latency supported
SDRAM module attributes
×4
1 clock
1, 2, 4, 8, F
4 banks
2, 3
0
0
Registered
SDRAM device attributes : General
CL = 2 Cycle time
CL = 2 Access time
-A75
10 ns
6 ns
-A75
tRP(MIN.)
-A75
-A75
-A75
-A75
20 ns
tRRD(MIN.)
15 ns
tRCD(MIN.)
20 ns
tRAS(MIN.)
45 ns
Module bank density
256M bytes
Data Sheet E0073N20
10
MC-4532DA727
(2/2)
Byte No.
32
Function Described
Hex
15H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
1.5 ns
Command and address signal input
0
0
0
1
0
1
0
1
setup time
33
Command and address signal input hold
time
08H
0
0
0
0
1
0
0
0
0.8 ns
34
35
Data signal input setup time
Data signal input hold time
15H
08H
00H
02H
E9H
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1.5 ns
0.8 ns
36-61
62
SPD revision
JEDEC 2
63
Checksum for bytes 0 - 62
-A75
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
Intel specification /CAS
latency support
64H
85H
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
1
100 MHz
-A75
Timing Chart
Refer to the µPD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0073N20
11
MC-4532DA727
Package Drawing
MC-4532DA727EF, MC-4532DA727PF, MC-4532DA727XF
Front side
Unit: mm
(DATUM -A-)
3.0 min
4.00 max
Component area
(Front)
1
84
B
A
C
8.89
11.43
54.61
36.83
42.18
24.495
133.35 ± 0.13
1.27 ± 0.1
Back side
2 – φ 3.00
8 5
1 6 8
Component area
(Back)
R2.0
(DATUM -A-)
Detail A
Detail B
R FULL
Detail C
(DATUM -A-)
R FULL
1.27(T.P.)
1.00
6.35
2.0
6.35
4.175
2.0
1.00 ± 0.05
Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.
Data Sheet E0073N20
12
MC-4532DA727
MC-4532DA727XFA
Unit: mm
Front side
(DATUM -A-)
4.00 max
3.0 min
Component area
(Front)
1
84
B
A
C
8.89
11.43
1.27 ± 0.1
54.61
36.83
42.18
24.495
133.35 ± 0.13
Back side
2 – φ 3.00
8 5
1 6 8
Component area
(Back)
R2.0
(DATUM -A-)
Detail A
Detail B
R FULL
Detail C
(DATUM -A-)
R FULL
1.27(T.P.)
1.00
6.35
2.0
6.35
4.175
2.0
1.00 ± 0.05
Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.
Data Sheet E0073N20
13
MC-4532DA727
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0073N20
14
MC-4532DA727
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
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