MC-4532DA727-A75 [ELPIDA]
Synchronous DRAM Module, 32MX72, 5.4ns, MOS, 43.18 MM HEIGHT, 1.27 MM PITCH, DIMM-168;
| 型号： | MC-4532DA727-A75 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | Synchronous DRAM Module, 32MX72, 5.4ns, MOS, 43.18 MM HEIGHT, 1.27 MM PITCH, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532DA727
32M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4532DA727 is an 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of
128M SDRAM: µPD45128441 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency and Access time from CLK.
Part number
/CAS latency
CL = 3
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
MC-4532DA727-A75
133 MHz
5.4 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1999
©
Document No.
M14210EJ1V0DS00 (1st edition)
Date Published March 1999 NS CP(K)
Printed in Japan
MC-4532DA727
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-4532DA727EF-A75
133 MHz
168-pin Dual In-line Memory Module 18 pieces of µPD45128441G5 (Rev. E)
(Socket Type)
(400 mil TSOP (II))
Edge connector : Gold plated
43.18 mm (1.7 inch) height
2
Data Sheet M14210EJ1V0DS00
MC-4532DA727
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ0
DQ1
DQ2
DQ3
Vcc
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
VSS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
CB4
DQ14
DQ15
CB0
CB5
CB1
VSS
VSS
NC
NC
Vcc
NC
NC
Vcc
/WE
/CAS
DQMB4
DQMB5
NC
DQMB0
DQMB1
/CS0
NC
/RAS
VSS
V
SS
A0
A2
A1
A3
A4
A5
A6
A7
A8
A0 - A11
: Address Inputs
A9
A10
BA0(A13)
A11
Vcc
BA1(A12)
Vcc
[Row: A0 - A11, Column: A0 - A9, A11]
BA0(A13), BA1 (A12) : SDRAM Bank Select
DQ0-DQ63, CB0-CB7: Data Inputs/Outputs
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CLK0
VSS
VSS
CKE0
NC
NC
/CS2
DQMB2
DQMB3
NC
CLK0 - CLK3
CKE0
: Clock Input
DQMB6
DQMB7
NC
: Clock Enable Input
: Write Protect
Vcc
Vcc
NC
NC
WP
NC
NC
CB6
CB7
CB2
/CS0, /CS2
/RAS
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
CB3
VSS
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
/CAS
DQ52
NC
DQ20
NC
/WE
NC
NC
DQMB0 - DQMB7
SA0 - SA2
SDA
: DQ Mask Enable
: Address Input for EEPROM
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
REGE
NC
VSS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
VSS
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
SCL
CC
V
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
SS
V
: Ground
REGE
NC
: Register / Buffer Enable
: No Connection
VSS
CLK3
NC
SA0
SA1
SA2
Vcc
SDA
SCL
Vcc
3
Data Sheet M14210EJ1V0DS00
MC-4532DA727
Block Diagram
/RCS0
RDQMB4
RDQMB0
DQ 3
DQ 2
DQ 1
DQ 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 32
DQ 33
DQ 34
DQ 35
DQM
D0
DQM
DQM
/CS
/CS
/CS
/CS
D9
DQ 7
DQ 6
DQ 5
DQ 4
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 36
DQ 37
DQ 38
DQ 39
DQM
D1
D
10
D1 - D17
Register1, Register2, Register3,
PLL
V
CC
RDQMB1
RDQMB5
C
DQ 11
DQ 10
DQ 9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 40
DQ 41
DQ 42
DQ 43
DQ 0
DQ 1
DQ 2
DQ 3
D1 - D17
Register1, Register2, Register3,
PLL
DQM
/CS
/CS
/CS
DQM
/CS
/CS
/CS
GND
D
2
D11
DQ 8
DQ 45
DQ 44
DQ 46
DQ 47
DQ 0
DQ 1
DQ 2
DQ 3
DQ 15
DQ 14
DQ 12
DQ 13
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D3
DQM
D12
SERIAL PD
SDA
WP
SCL
A0
A1
A2
CB 5
CB 4
CB 7
CB 6
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
CB 2
CB 3
CB 0
CB 1
DQM
47kΩ
D
4
D13
SA0 SA1 SA2
/RCS2
RDQMB6
RDQMB2
DQ 18
DQ 19
DQ 17
DQ 16
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 48
DQ 49
DQ 50
DQ 51
DQM
DQM
D5
/CS
/CS
/CS
/CS
DQ 1
DQ 2
DQ 3
D14
10 Ω
CLK1 - CLK3
12 pF
DQ 23
DQ 22
DQ 21
DQ 20
DQ 0
DQ 1
DQ 2
DQ 3
DQ 52
DQ 53
DQ 54
DQ 55
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D6
DQM
D15
RDQMB3
RDQMB7
10 Ω
DQ 27
DQ 26
DQ 25
DQ 24
DQ 56
DQ 57
DQ 58
DQ 59
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
CLK : D0, D1, D9
CLK : D2, D10, D11
CLK : D3, D4, D12
CLK : D5, D13, D14
CLK : D6, D7, D15
CLK : D8, D16, D17
CLK : Register1, Register2,Register3
CLK0
DQM
D16
/CS
/CS
DQM
D7
/CS
/CS
PLL
12pF
DQ 31
DQ 30
DQ 29
DQ 28
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
D8
DQM
D17
A0 - A3, A10 : D0 - D3, D9 - D13
BA0, BA1
RA0A - RA3A, RA10A
RBA0A, RBA1A
RA0B - RA3B, RA10B
RBA0B, RBA1B
A0 - A3,A10
BA0, BA1
A0 - A3, A10 : D4 - D8, D14 - D17
BA0, BA1
A0 - A3, A10
BA0, BA1
A4 - A9, A11 : D4 - D8, D14 - D17
RA4B - RA9B, RA11B
A4 - A9, A11 : D0 - D3, D9 - D13
RA4A - RA9A, RA11A
/RRASA
A4 - A9, A11
A4 - A9, A11
/RRASB
/RCASB
/RAS : D4 - D8, D14 - D17
/RAS : D0 - D3, D9 - D13
/RAS
/RAS
Register1
Register2
/LE
/CAS : D4 - D8, D14 - D17
/CAS
/CAS
/RCASA
RCKE0A
RCKE0B
/CAS : D0 - D3, D9 - D13
CKE : D0 - D4, D9 - D12
CKE : D5 - D8, D13 - D17
CKE0
DQMB0 - DQMB7
/CS0, /CS2
/WE
RDQMB0 - RDQMB7
REGE
CC
/LE
V
/RCS0, /RCS2
Register3
/LE
/WE : D0 - D3, D9 - D13
CKE : D4 - D8, D14 - D17
/RWEA
/RWEB
10kΩ
Remarks 1. The value of all resistors of DQs is 10 Ω.
2. D0 - D17: µPD45128441 (8M words × 4 bits × 4 banks)
3. REGE ≤ VIL: Buffer mode
IH
REGE ≥ V : Register mode
4. Register: HD74ALVCF162834
PLL: HD74CDCF2510B
4
Data Sheet M14210EJ1V0DS00
MC-4532DA727
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
22
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
Low level input voltage
VCC + 0.3
+ 0.8
70
V
VIL
V
Operating ambient temperature
TA
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
TYP.
MAX.
Unit
pF
Input capacitance
A0 - A11, BA0(A13), BA1 (A12), T.B.D.
/RAS, /CAS, /WE
T.B.D.
CI2
CI3
CI4
CI5
CI/O
CLK0 - CLK3
CKE0
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
/CS0, /CS2
DQMB0-DQMB7
DQ0 - DQ63, CB0 - CB7
Data input/output capacitance
pF
5
Data Sheet M14210EJ1V0DS00
MC-4532DA727
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
Burst length = 1, tRC ≥ tRC(MIN.) ,
IO = 0 mA
MIN. MAX. Unit Notes
Operating current
ICC1
mA
mA
mA
1
2,290
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns
power down mode ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
Precharge standby current in ICC2N CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
268
86
610
non power down mode
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞,
224
Input signals are stable.
Active standby current in
power down mode
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
mA
mA
340
132
790
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞,
440
Input signals are stable.
Operating current
(Burst mode)
ICC4
tCK ≥ tCK(MIN.) , IO = 0 mA
mA
mA
2
3
2,920
CBR (Auto) refresh current
ICC5
tRC ≥ tRC(MIN.)
4,540
Self refresh current
ICC6 CKE ≤ 0.2 V, tCK = 15 ns
II(L) VI = 0 to 3.6 V, All other pins not under test = 0 V
mA
µA
µA
V
286
+20
+1.5
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
–20
–1.5
2.4
IO(L) DOUT is disabled, VO = 0 to 3.6 V
VOH IO = – 4.0 mA
VOL IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
Data Sheet M14210EJ1V0DS00
MC-4532DA727
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
T
• AC measurements assume t = 1ns.
IH
IL
• Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V and V .
T
IH (MIN.)
IL (MAX.)
and V
• If t is longer than 1ns, reference level for measuring timing of input signals is V
.
• An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
t
SETUP
t
HOLD
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
7
Data Sheet M14210EJ1V0DS00
MC-4532DA727
Synchronous Characteristics (Registered Mode)
Parameter
Symbol
-A75
Unit
Note
MIN.
7.5
MAX.
Clock cycle time
tCK
tAC
(133 MHz)
5.4
ns
ns
MHz
%
Access time from CLK
Input clock frequency
Input CLK duty cycle
Data-out hold time
1
1
50
45
133
55
tOH
tLZ
2.7
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data-out low-impedance time
Data-out high- impedance time
Data-in setup time
tHZ
3
6
tDS
1.5
0.8
1.5
0.8
1.5
0.8
1.5
1.5
Data-in hold time
tDH
Address setup time
tAS
Address hold time
tAH
CKE setup time
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
Command (/CS0 - /CS3, /RAS, /CAS,
/WE, DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS,
/WE, DQMB0 - DQMB7) hold time
tCMH
0.8
ns
Note 1. Output load
1.4 V
50 Ω
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
8
Data Sheet M14210EJ1V0DS00
MC-4532DA727
Asynchronous Characteristics (Registered Mode)
Parameter
Symbol
-A75
Unit
Note
MIN.
MAX.
REF to REF/ACT command period
ACT to PRE command period
tRC
tRAS
tRP
9
6
CLK
CLK
CLK
CLK
CLK
CLK
ns
16,000
PRE to ACT command period
3
Delay time ACT to READ/WRITE command
ACT(0) to ACT(1) command period
Data-in to PRE command period
Data-in to ACT(REF) command period(Auto precharge)
Mode register set cycle time
tRCD
tRRD
tDPL
tDAL
tRSC
tT
3
2
1
20
2
CLK
ns
Transition time
0.5
30
64
Refresh time (4,096 refresh cycles)
tREF
ms
9
Data Sheet M14210EJ1V0DS00
MC-4532DA727
Serial PD
Byte No.
0
(1/2)
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
Total number of bytes of serial PD memory
08H
04H
0CH
0BH
01H
48H
00H
01H
75H
54H
02H
80H
04H
04H
01H
8FH
04H
04H
01H
01H
1FH
0EH
00H
17H
0FH
17H
2DH
40H
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
256 bytes
SDRAM
12 rows
11 columns
1 bank
72 bits
0
Fundamental memory type
Number of rows
3
4
Number of columns
Number of banks
Data width
5
6
7
Data width (continued)
Voltage interface
8
LVTTL
7.5 ns
5.4 ns
ECC
9
CL = 3 Cycle time
-A75
-A75
10
11
12
13
14
15
16
17
18
19
20
21
22
23-26
27
CL = 3 Access time
DIMM configuration type
Refresh rate/type
Normal
×4
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
×4
1 clock
1, 2, 4, 8, F
4 banks
3
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
0
SDRAM module attributes
SDRAM device attributes : General
Registered
tRP(MIN.)
-A75
23 ns(22.5ns)
15 ns
28
29
30
31
tRRD(MIN.)
-A75
-A75
-A75
tRCD(MIN.)
23 ns(22.5ns)
45 ns
tRAS(MIN.)
Module bank density
256M bytes
10
Data Sheet M14210EJ1V0DS00
MC-4532DA727
(2/2)
Byte No.
32
Function Described
Hex
15H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
1.5 ns
Command and address signal input
setup time
0
0
0
1
0
1
0
1
33
Command and address signal input hold
time
08H
0
0
0
0
1
0
0
0
0.8 ns
34
35
Data signal input setup time
15H
08H
00H
02H
EDH
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
1.5 ns
0.8 ns
Data signal input hold time
SPD revision
36-61
62
JEDEC 2
63
Checksum for bytes 0 - 62
-A75
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
Intel specification /CAS
latency support
64H
85H
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
1
100 MHz
-A75
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).
11
Data Sheet M14210EJ1V0DS00
MC-4532DA727
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
N
A'(AREA B)
Y
Z
Q
S
(OPTIONAL HOLES)
B
A
T
H
J
K
C
I
G
D
E
B
A(AREA A)
M2
(AREA A)
M1
(AREA B)
ITEM MILLIMETERS
detail of
part
detail of
part
A
133.35±0.13
133.35
W
A'
B
B'
C
C'
D
E
11.43
73.406
36.83
29.972
6.35
54.61
6.35
G
P
G
H
I
D
1.27 (T.P.)
8.89
J
24.495
42.18
17.78
43.18
23.4
K
L
M
M1
M2
N
P
19.78
4.0 MAX.
1.0
Q
R2.0
R
S
T
4.0±0.1
3.0
1.27±0.1
4.0 MIN.
0.2±0.15
1.0±0.05
2.54 MIN.
3.0 MIN.
3.0 MIN.
U
V
W
X
Y
Z
12
Data Sheet M14210EJ1V0DS00
MC-4532DA727
[MEMO]
13
Data Sheet M14210EJ1V0DS00
MC-4532DA727
[MEMO]
14
Data Sheet M14210EJ1V0DS00
MC-4532DA727
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Data Sheet M14210EJ1V0DS00
MC-4532DA727
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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