W194-70GT [CYPRESS]
PLL Based Clock Driver, W19 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8;
| 型号： | W194-70GT |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, W19 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W194
Frequency Multiplier and Zero Delay Buffer
Features
Table 1. Configuration Options
• Two outputs
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
FS0
0
FS1
0
OUT1
2 X REF
4 X REF
REF
OUT2
REF
• Configuration options allow various multiplications of
the reference frequency—refer to Table 1 to determine
the specific option which meets your multiplication
needs
1
0
2 X REF
REF/2
0
1
• Available in 8-pin SOIC package
1
1
8 X REF
4 X REF
8 X REF
2 X REF
16 X REF
4 X REF
2 X REF
4 X REF
REF
Key Specifications
0
0
Operating Voltage: .............................. 3.3V±5% or 5.0±10%
1
0
Operating Range: .......................10 MHz < f
< 133 MHz
OUT1
0
1
Absolute Jitter: ......................................................... ±500 ps
Output to Output Skew: .............................................. 250 ps
1
1
8 X REF
Propagation Delay: ................................................... ±350 ps
Propagation delay is affected by input rise time.
Block Diagram
Pin Configuration
SOIC
External feedback connection to
OUT1 or OUT2, not both
FBIN
FBIN
IN
1
2
3
4
8
7
6
5
OUT2
VDD
OUT1
FS1
GND
FS0
FS0
÷Q
FS1
Phase
Detector
Charge
Pump
IN
Reference
Input
Loop
Filter
Output
Buffer
OUT1
OUT2
VCO
Output
Buffer
÷2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 16, 2000, rev. *B
W194
Pin Definitions
Pin
Pin Name
IN
Pin No.
Type
Pin Description
2
1
I
I
Reference Input: The output signals will be synchronized to this signal.
FBIN
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations will be synchronized to the REF signal input (IN).
OUT1
OUT2
VDD
6
8
7
O
O
P
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Output 2: The frequency of the signal provided by this pin is one-half of the frequency of
OUT1. See Table 1.
Power Connections: Connect to 3.3V or 5V. This pin should be bypassed with a 0.1-µF
decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance.
GND
3
P
I
Ground Connection: Connect all grounds to the common system ground plane.
FS0:1
4, 5
Function Select Inputs: Tie to V (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
DD
“How to Implement Zero Delay,” and “Inserting Other Devices
in Feedback Path.”
Overview
The W194-70 is a two-output zero delay buffer and frequency
multiplier. It provides an external feedback path allowing max-
imum flexibility when implementing the Zero Delay feature.
This is explained further in the sections of this data sheet titled
The W194-70 is a pin-compatible upgrade of the Cypress
W42C70-01. The W194-70 addresses some application de-
pendent problems experienced by users of the older device.
Ferrite
Bead
CA
Power Supply Connection
G
V+
µ
10 F
C8
G
µ
0.01 F
OUT 2
22
Ω
FBIN
IN
1
OUTPUT 2
8
µ
C9 = 0.1 F
VDD
7
G
2
3
OUT 1
22
Ω
OUTPUT 1
GND
6
G
FS0
FS1
5
4
Figure 1. Schematic/Suggested Layout
2
W194
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
How to Implement Zero Delay
Typically, Zero Delay Buffers (ZDBs) are used because a de-
signer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
Referring to Figure 2, if the traces between the ASIC/Buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs from
the ASIC/Buffer is more complex however, as any propagation
delay from the ZDB output to the ASIC/Buffer output must be
accounted for.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
Zero
Reference
Delay
Signal
Buffer
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affected by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.
ASIC/
Buffer
Feedback
Input
A
Inserting Other Devices in Feedback Path
Figure 2. 6 Output Buffer in the Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals to the signal coming from
some other device. This implementation can be applied to any
3
W194
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
W
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
B
P
D
: T = 0°C to 70°C, V = 3.3V ±5%
DC Electrical Characteristics
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
Unit
mA
V
I
Unloaded, 100 MHz
17
35
DD
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.8
IL
V
2.0
2.4
V
IH
OL
V
I
I
= 12 mA
= 8 mA
0.4
V
OL
OL
V
Output High Voltage
I
I
= 12 mA
= 8 mA
V
OH
OL
OL
I
I
Input Low Current
Input High Current
V
V
= 0V
5
5
µA
µA
IL
IN
IN
= V
IH
DD
: T = 0°C to 70°C, V = 5V ±10%
DC Electrical Characteristics
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
35
Unit
mA
V
I
Unloaded, 100 MHz
17
DD
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.8
IL
V
V
2.0
2.4
V
IH
OL
I
I
= 12 mA
= 8 mA
0.4
V
OL
OL
V
Output High Voltage
I
I
= 12 mA
= 8 mA
V
OH
OL
OL
I
I
Input Low Current
Input High Current
V
V
= 0V
5
5
µA
µA
IL
IN
IN
= V
IH
DD
4
W194
AC Electrical Characteristics: T = 0°C to +70°C, V = 3.3V ±5%
A
DD
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
[1]
f
f
t
t
t
t
t
t
t
t
t
Input Frequency
OUT2 = REF
OUT1 15-pF load
MHz
IN
[6]
Output Frequency
Output Rise Time
Output Fall Time
10
133
3.5
2.5
10
MHz
OUT
R
2.0V to 0.8V, 15-pF load
2.0V to 0.8V, 15-pF load
ns
ns
F
[2]
Input Clock Rise Time
ns
ICLKR
ICLKF
PD
[2]
Input Clock Fall Time
10
ns
[3, 4]
FBIN to REF Skew
Duty Cycle
Measured at V /2
–2
0.6
50
2
ns
DD
[5]
15-pF load
40
60
%
D
PLL Lock Time
Jitter, Cycle-to-Cycle
Power supply stable
1.0
300
ms
ps
LOCK
JC
[8]
Die out Time
100
Clock Cycles
DC
AC Electrical Characteristics: T = 0°C to +70°C, V = 5.0V ±10%
A
DD
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
MHz
MHz
ns
[1]
f
Input Frequency
OUT2 = REF
OUT1 15-pF load
IN
[6]
f
t
t
t
t
t
t
t
t
Output Frequency
Output Rise Time
Output Fall Time
10
133
2.5
1.5
10
OUT
R
2.0V to 0.8V, 15-pF load
2.0V to 0.8V, 15-pF load
ns
F
[2]
Input Clock Rise Time
ns
ICLKR
ICLKF
PD
[2]
Input Clock Fall Time
10
ns
[3, 4]
FBIN to REF Skew
Duty Cycle
Measured at V /2
–2
0.6
50
2
ns
DD
[5, 7]
15-pF load
40
60
%
D
PLL Lock Time
Jitter, Cycle-to-Cycle
Power supply stable
1.0
200
ms
ps
LOCK
JC
Ordering Information
Package
Ordering Code
Option
-70
Name
Package Type
8-pin SOIC (150-mil)
W194
G
Document #: 38-00794-B
Notes:
1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration).
2. Longer input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V.
4. Skew is measured at 1.4V on rising edges.
5. Duty cycle is measured at 1.4V.
6. For the higher drive -11, the load is 20 pF.
7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.
8. 33 MHz reference input suddenly stopped (0MHz). Number of cycles provided prior to output falling to <16 MHz.
5
W194
Package Diagram
8-Pin Small Outlined Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
©2020 ICPDF网 联系我们和版权申明