W195BH_技术文档

PRELIMINARY

W195B

Frequency Generator for Integrated Core Logic

SDRAM, APIC, 48MHz Output Skew: ........................250 ps

Features

PCI Output Skew:........................................................500 ps

• Maximized EMI suppression using Cypress’s Spread

Spectrum Technology

• Low jitter and tightly controlled clock skew

• Highly integrated device providing clocks required for

CPU, core logic, and SDRAM

• Two copies of CPU clocks

CPU to SDRAM Skew (@100 MHz):..................4.5 to 5.5 ns

CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns

3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns

PCI to APIC Skew: ....................................................± 0.5 ns

Table 1. Frequency Selections

• Nine copies of SDRAM clocks

• Eight copies of PCI clock

FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC

• One copy of synchronous APIC clock

• Two copies of 66-MHz outputs

• Two copies of 48-MHz outputs

• One copy of selectable 24- or 48-MHz clock

• One copy of double strength 14.31818-MHz reference

clock

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

133.6 133.6

Reserved

100.2 100.2

66.8 33.4 16.7

66.8

105

110

114

119

124

129

95

100.2

105

110

114

119

124

129

95

70

73.3 36.7 18.3

76 38 19

35 17.5

• Power-down control

79.3 39.7 19.8

82.7 41.3 20.7

64.5 32.3 16.1

63.3 31.7 15.8

69 34.5 17.3

75 37.5 18.8

2

• I C interface for turning off unused clocks

Key Specifications

CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps

138

150

75

138

150

113

90

APIC, 48MHz, 3V66, PCI Outputs

Cycle-to-Cycle Jitter: .................................................. 500 ps

90

60

30

15

CPU, 3V66 Output Skew: ........................................... 175 ps

83.3

125

83.3 41.7 20.8

Pin Configuration^[1]

Block Diagram

VDDQ3

VDDQ2

APIC

VDDQ2

CPU0

CPU1

REF2x/FS3*

VDDQ3

X1

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

REF2X/FS3*

X1

X2

XTAL

OSC

X2

GND

VDDQ3

3V66_0

3V66_1

GND

FS0*/PCI0

FS1^/PCI1

FS2*/PCI2

GND

PCI3

PCI4

VDDQ3

PCI5

PCI6

PCI7

GND

PLL REF FREQ

GND

VDDQ3

SDRAM0

SDRAM1

SDRAM2

GND

VDDQ2

CPU0:1

Divider,

Delay,

and

Phase

Control

Logic

I²C

Logic

2

SDATA

SCLK

SDRAM3

SDRAM4

SDRAM5

VDDQ3

SDRAM6

SDRAM7

SDRAM8

GND

PWRDWN#*

SCLK

VDDQ3

GND

SDATA

FS3*

FS2*

FS1*

FS0*

APIC

VDDQ3

3V66_0:1

2

PCI0/FS0*

PLL 1

PCI1/FS1*

PCI2/FS2*

48MHz_0

48MHz_1

SI0/24_48#MHz*

VDDQ3

PCI3:7

5

9

SDRAM0:8

Note:

PWRDWN#

1. Internal 250K pull-up or pull down resistors present on inputs

marked with * or ^ respectively. Design should not rely solely on

internal pull-up or pull down resistor to set I/Opins HIGH orLOW

respectively.

VDDQ3

PLL2

48MHz_0:1

2

SI0/24_48#MHz*

/2

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 13, 1999, rev. **

PRELIMINARY

W195B

Pin Definitions

Type

Pin Name

Pin No.

Pin Description

REF2x/FS3

1

I/O

Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock out-

put. This pin also serves as the select strap to determine device operating frequency

as described in Table 1.

X1

3

4

I

Crystal Input: This pin has dual functions. It can be used as an external 14.318-

MHz crystal connection or as an external reference frequency input.

X2

Crystal Output: An input connection for an external 14.318-MHz crystal connec-

tion. If using an external reference, this pin must be left unconnected.

PCI0/FS0

10

I/O

PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also

serves as the select strap to determine device operating frequency as described in

Table 1.

PCI1/FS1

PCI2/FS2

11

12

I/O

PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also

serves as the select strap to determine device operating frequency as described in

Table 1.

PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin

doubles as the select strap to determine device operating frequency as described

in Table 1.

PCI3:7

14, 15, 17, 18,

19

O

PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually

turned off via I C interface.

2

3V66_0:1

48MHz_0:1

7,8

66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled

by FS0:3 (see Table 1).

21, 22

23

O

48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.

SIO/

24_48#MHz

I/O

Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.

During power-up, it also serves as a selection strap. If it is sampled HIGH, the output

frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.

PWRDWN#

CPU0:1

29

I

Power Down Control: LVTTL-compatible input that places the device in power-

down mode when held LOW.

45, 44

O

CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies

depending on the configuration of FS0:3. Voltage swing is set by V

.

DDQ2

SDRAM0:8,

41, 40, 39, 37,

36, 35, 33, 32,

31

SDRAM Clock Outputs: 3.3V outputs for SDRAM. The operating frequency is

controlled by FS0:3 (see Table 1).

O

APIC

47

Synchronous APIC Clock Outputs: Clock outputs running synchronous with the

PCI clock outputs. Voltage swing set by V

.

DDQ2

2

SDATA

SCLK

25

28

I/O

I

Data pin for I C circuitry.

2

Clock pin for I C circuitry.

VDDQ3

2, 6, 16, 24, 27,

34, 42

P

3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buff-

ers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V.

VDDQ2

GND

46, 48

P

2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-

nect to 2.5V or 3.3V.

5, 9, 13, 20, 26,

30, 38, 43

G

Ground Connections: Connect all ground pins to the common system ground

plane.

2

PRELIMINARY

W195B

Output Strapping Resistor

Series Termination Resistor

Clock Load

W195B

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10 k

Ω

Q

D

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

is delivered on the pins. If the power supply has not yet

reached full value, output frequency initially may be below tar-

get but will increase to target once supply voltage has stabi-

lized. In either case, a short output clock cycle may be pro-

duced from the CPU clock outputs when the outputs are

enabled.

Overview

The W195B is a highly integrated frequency timing generator,

supplying all the required clock sources for an Intel® architec-

ture platform using graphics integrated core logic.

Functional Description

Offsets Among Clock Signal Groups

I/O Pin Operation

Figure 2 and Figure 3 represent the phase relationship among

the different groups of clock outputs from W195B when it is

providing a 66-MHz CPU clock and a 100-MHz CPU clock,

respectively. It should be noted that when CPU clock is oper-

ating at 100 MHz, CPU clock output is 180 degrees out of

phase with SDRAM clock outputs.

Pin # 1, 10, 11, 12, 23 are dual-purpose l/O pins. Upon power-

up the pin acts as a logic input. An external 10-kΩ strapping

resistor should be used. Figure 1 shows a suggested method

for strapping resistor connections.

After 2 ms, the pin becomes an output. Assuming the power

supply has stabilized by then, the specified output frequency

0 ns

10 ns

20 ns

30 ns

40 ns

CPU 66 Period

CPU 66-MHz

SDRAM 100 Period

SDRAM 100-MHz

Hub-PC

3V66 66-MHz

PCI 33-MHz

REF 14.318-MHz

USB 48-MHz

APIC

Figure 2. Group Offset Waveforms (66.8 CPU Clock, 100.2 SDRAM Clock)

3

PRELIMINARY

W195B

0 ns

10 ns

20 ns

30 ns

40 ns

CPU 100 Period

CPU 100-MHz

SDRAM 100 Period

SDRAM 100-MHz

Hub-PC

3V66 66-MHz

PCI 33-MHz

REF 14.318-MHz

USB 48-MHz

APIC

Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)

Power Down Control

W195B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and

all clock outputs are driven LOW.

0ns

25ns

50ns

75ns

Center

1

2

VCO Internal

CPU 100MHz

3V66 66MHz

PCI 33MHz

APIC

PwrDwn

SDRAM 100MHz

REF 14.318MHz

USB 48MHz

[2, 3, 4, 5]

Figure 4. PWRDWN# Timing Diagram

Notes:

2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW

transition.

3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W195B.

4. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.

5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.

4

PRELIMINARY

W195B

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

Spread Spectrum Generator

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the am-

plitudes of the radiated electromagnetic emissions are re-

duced. This effect is depicted in Figure 5.

The output clock is modulated with a waveform depicted in

Figure 6. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is –0.5% of the selected fre-

quency. Figure 6 details the Cypress spreading pattern.

Cypress does offer options with more spread and greater EMI

reduction. Contact your local Sales representative for details

on these devices.

As shown in Figure 5, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is

dB = 6.5 + 9*log (P) + 9*log (F)

10

EMI Reduction

Spread

Spectrum

Enabled

Non-

Spread

Spectrum

Figure 5. Typical Clock and SSFTG Comparison

MAX.

MIN.

Figure 6. Typical Modulation Profile

5

PRELIMINARY

W195B

1 bit

7 bits

1

8 bits

1

Start bit

Slave Address

R/W

Ack

Command Code

Ack

Byte Count = N

Ack

1 bit

Data Byte 1

8 bits

Ack

Data Byte 2

8 bits

Ack

1

...

Data Byte N

8 bits

Ack

1

Stop

1

[6]

Figure 7. An Example of a Block Write

Serial Data Interface

fer a maximum of 32 data bytes. The slave receiver address

for W195B is 11010010. Figure 7 shows an example of a block

write.

The W195B features a two-pin, serial data interface that can

be used to configure internal register settings that control par-

ticular device functions.

The command code and the byte count bytes are required as

the first two bytes of any transfer. W195B expects a command

code of 0000 0000. The byte count byte is the number of ad-

ditional bytes required for the transfer, not counting the com-

mand code and byte count bytes. Additionally, the byte count

byte is required to be a minimum of 1 byte and a maximum of

32 bytes to satisfy the above requirement. Table 2 shows an

example of a possible byte count value.

Data Protocol

The clock driver serial protocol accepts only block writes from

the controller. The bytes must be accessed in sequential order

from lowest to highest byte with the ability to stop after any

complete byte has been transferred. Indexed bytes are not al-

lowed.

A transfer is considered valid after the acknowledge bit corre-

sponding to the byte count is read by the controller. The com-

mand code and byte count bytes are ignored by the W195B.

However, these bytes must be included in the data write se-

quence to maintain proper byte allocation.

A block write begins with a slave address and a write condition.

After the command code the core logic issues a byte count

which describes how many more bytes will follow in the mes-

sage. If the host had 20 bytes to send. The first byte would be

the number 20 (14h), followed by the 20 bytes of data. The byte

count may not be 0. A block write command is allowed to trans-

Table 2. Example of Possible Byte Count Value

Byte Count Byte

Notes

MSB

0000

0010

LSB

0000

0001

0010

0011

0100

0101

0110

0111

0000

Not allowed. Must have at least one byte.

Data for functional and frequency select register (currently byte 0 in spec)

Reads first two bytes of data. (byte 0 then byte 1)

Reads first three bytes (byte 0, 1, 2 in order)

Reads first four bytes (byte 0, 1, 2, 3 in order)

[7]

Reads first five bytes (byte 0, 1, 2, 3, 4 in order)

[7]

Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)

Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)

Max. byte count supported = 32

Table 3. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Output Disable

Any individual clock output(s) can be disabled.

Disabled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI and sys-

tem power. Examples are clock outputs to unused

PCI slots.

(Reserved)

Reserved function for future device revision or pro- No user application. Register bit must be written as 0.

duction device testing.

Notes:

6. The acknowledgment bit is returned by the slave/receiver (W195B).

7. Byte 6 and 7 are not defined for W195B.

6

PRELIMINARY

W195B

2. All unused register bits (reserved and N/A) should be writ-

ten to a “0” level.

Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

3. All register bits labeled “Initialize to 0" must be written to

zero during initialization. Failure to do so may result in high-

er than normal operating current. The controller will read

back the last written value.

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

[8]

Byte 0: Control Register (1 = Enable, 0= Disable)

Bit

Pin#

Name

Reserved

Default

Pin Function

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

1

0

Reserved

-

Reserved

24/48MHz

48MHz

Reserved

-

Reserved

-

Reserved

-

23

Reserved

(Active/Inactive)

Reserved

21, 22

-

Reserved

[8]

Byte 1: Control Register (1 = Enable, 0= Disable)

Bit

Pin#

32

33

35

36

37

39

40

41

Name

SDRAM7

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

(Active/Inactive)

SDRAM6

SDRAM5

SDRAM4

SDRAM3

SDRAM2

SDRAM1

SDRAM0

[8]

Byte 2: Control Register (1 = Enable, 0= Disable)

Bit

Pin#

19

18

17

15

14

12

11

-

Name

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PCI7

PCI6

PCI5

PCI4

PCI3

PCI2

PCI1

1

0

(Active/Inactive)

Reserved

Note:

8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be

configured during the normal modes of operation.

7

PRELIMINARY

W195B

Byte 3: Reserved Register (1 = Enable, 0= Disable)

Bit

Pin#

Name

Reserved

Default

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

Reserved

Byte 4: Reserved Register (1 = Enable, 0= Disable)

Bit

Pin#

Name

Default

Pin Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

-

SEL3

SEL2

SEL1

SEL0

0

See Table 4

FS(0:3) Override

0 = Select operating frequency by FS(0:3) strapping

1 = Select operating frequency by SEL(0:4) bit settings

Bit 2

Bit 1

Bit 0

-

SEL4

0

See Table 4

Reserved

Byte 5: Reserved Register (1 = Enable, 0= Disable)

Bit

Pin#

Name

Reserved

Default

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

Reserved

Byte 6: Reserved Register (1 = Enable, 0= Disable)

Bit

Pin#

Name

Reserved

Default

Pin Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

0

Reserved

8

PRELIMINARY

W195B

Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

Data Byte 4, Bit 3 = 1

Bit 2

Bit 7

Bit 6

Bit 5

Bit 4

Spread

SEL_4

SEL_3

SEL_2

SEL_1

SEL_0

CPU

SDRAM

3V66

66.8

Reserved

66.8

71.3

74.7

78

PCI

APIC

Spectrum

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

133.6

33.4

16.7

±0.5%

100.2

66.8

107

112

117

121

155

145

136

140

72

100.2

107

33.4

35.7

37.3

39

16.7

17.8

18.7

19.5

20.2

19.4

18.1

17

±0.5%

OFF

112

117

121

80.7

77.5

72.5

68

40.3

38.8

36.3

34

155

145

136

140

70

35

17.5

18

108

72

36

130

127

125

133.6

130

65

32.5

31.8

31.3

33.4

16.3

15.9

15.6

16.7

127

63.5

62.5

66.8

Reserved

66.8

70

125

133.6

100.2

66.8

105

110

114

119

124

129

95

100.2

105

110

114

119

124

129

95

33.4

35

16.7

17.5

18.3

19

OFF

73.3

76

36.7

38

79.3

82.7

64.5

63.3

69

39.7

41.3

32.3

31.7

34.5

37.5

30

19.8

20.7

16.1

15.8

17.3

18.8

15

138

150

75

138

150

113

90

75

90

60

83.3

125

83.3

41.7

20.8

9

PRELIMINARY

W195B

DC Electrical Characteristics

DC parameters must be sustainable under steady state (DC) conditions.

Absolute Maximum DC Power Supply

Parameter

Description

3.3V Core Supply Voltage

Min.

–0.5

–65

Max.

4.6

Unit

V

DDQ3

2.5V I/O Supply Voltage

Storage Temperature

3.6

V

DDQ2

S

T

150

°C

Absolute Maximum DC I/O

Parameter

Description

Min.

–0.5

2000

Max.

4.6

Unit

V

3.3V Core Supply Voltage

i/o3

i/o2

2.5V I/O Supply Voltage

3.6

V

ESD prot.

V

DC Operating Requirements

Parameter

Description

Condition

3.3V±5%

2.5V±5%

Min.

Max.

3.465

2.625

Unit

V

3.3V Core Supply Voltage

3.3V I/O Supply Voltage

2.5V I/O Supply Voltage

3.135

2.375

DD3

V

DDQ3

DDQ2

V

= 3.3V±5%

DD3

ih3

il3

3.3V Input High Voltage

3.3V Input Low Voltage

V

2.0

V

+0.3

DD

V

DD3

V

–0.3

0.8

SS

[9]

I

Input Leakage Current

0<V <V

DDQ3

–5

+5

µA

il

in

V

= 2.5V±5%

= 3.3V±5%

DDQ2

V

2.5V Output High Voltage

2.5V Output Low Voltage

I

=(–1 mA)

2.0

2.4

V

oh2

oh

V

I =(1 mA)

ol

0.4

ol2

V

DDQ3

V

3.3V Output High Voltage

3.3V Output Low Voltage

=(–1 mA)

oh

V

oh3

V

I =(1 mA)

0.4

ol3

ol

V

DDQ3

poh3

pol3

V

PCI Bus Output High Voltage

PCI Bus Output Low Voltage

=(–1 mA)

V

oh

I =(1 mA)

0.55

ol

C

Input Pin Capacitance

Xtal Pin Capacitance

Output Pin Capacitance

Pin Inductance

5

22.5

6

pF

nH

°C

in

13.5

xtal

out

L

0

7

T

Ambient Temperature

No Airflow

70

a

Note:

9. Input Leakage Current does not include inputs with pull-up or pull-down resistors.

10

PRELIMINARY

W195B

AC Electrical Characteristics

T = 0°C to +70°C, V

= 3.3V±5%, V

= 2.5V±5%

DDQ2

A

DDQ3

f

= 14.31818 MHz

XTL

Spread Spectrum function turned off

66.6-MHz Host

100-MHz Host

Parameter

Description

Min.

15.0

5.2

Max.

15.5

N/A

1.6

Min.

10.0

3.0

Max.

10.5

N/A

1.6

Unit

ns

Notes

T

Host/CPUCLK Period

10

13

14

Period

HIGH

LOW

RISE

FALL

Host/CPUCLK High Time

Host/CPUCLK Low Time

Host/CPUCLK Rise Time

Host/CPUCLK Fall Time

ns

5.0

2.8

ns

0.4

ns

0.4

1.6

0.4

1.6

ns

T

SDRAM CLK Period

10.0

3.0

2.8

0.4

10.5

N/A

1.6

10.0

3.0

2.8

0.4

10.5

N/A

1.6

ns

10

13

14

Period

HIGH

LOW

RISE

FALL

SDRAM CLK High Time

SDRAM CLK Low Time

SDRAM CLK Rise Time

SDRAM CLK Fall Time

1.6

T

APIC CLK Period

60.0

25.5

25.3

0.4

64.0

N/A

1.6

60.0

25.5

25.3

0.4

64.0

N/A

1.6

ns

10

13

14

Period

HIGH

LOW

RISE

FALL

APIC CLK High Time

APIC CLK Low Time

APIC CLK Rise Time

APIC CLK Fall Time

0.4

1.6

0.4

1.6

T

3V66 CLK Period

15.0

5.25

5.05

0.5

16.0

N/A

2.0

15.0

5.25

5.05

0.5

16.0

N/A

2.0

ns

10, 12

13

Period

HIGH

LOW

RISE

FALL

3V66 CLK High Time

3V66 CLK Low Time

3V66 CLK Rise Time

3V66 CLK Fall Time

14

0.5

2.0

0.5

2.0

T

PCI CLK Period

30.0

12.0

0.5

N/A

2.0

30.0

12.0

0.5

N/A

2.0

ns

10, 11

13

Period

HIGH

LOW

RISE

FALL

PCI CLK High Time

PCI CLK Low Time

PCI CLK Rise Time

PCI CLK Fall Time

14

0.5

2.0

0.5

2.0

tp , tp

Output Enable Delay (All outputs)

Output Disable Delay (All outputs)

All Clock Stabilization from Power-Up

1.0

10.0

3

1.0

10.0

3

ns

ZL

ZH

tp , tp

LZ

t

ms

stable

Notes:

10. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.

11.

12.

T

_HIGHis measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.

_LOWis measured at 0.4V for all outputs.

13. The time specified is measured from when V_DDQ3achieves its nominal operating level (typical condition V_DDQ3= 3.3V) until the frequency output is stable and

operating within specification.

14. T_RISEand T_FALLare measured as a transition through the threshold region V_ol= 0.4V and V_oh= 2.0V (1 mA) JEDEC specification.

11

PRELIMINARY

W195B

Group Skew and Jitter Limits

Output Group

Skew, Jitter

Pin-Pin Skew Max

Cycle-Cycle Jitter

250 ps

Duty Cycle

45/55

Nom Vdd

2.5V

Measure Point

1.25V

1.5V

CPU

SDRAM

APIC

175 ps

250 ps

175 ps

500 ps

N/A

250 ps

45/55

3.3V

500 ps

45/55

2.5V

1.25V

1.5V

48MHz

3V66

500 ps

45/55

3.3V

500 ps

45/55

3.3V

1.5V

PCI

500 ps

45/55

3.3V

1.5V

REF

1000 ps

45/55

3.3V

1.5V

Test Point

Output

Buffer

Test Load

Clock Output Wave

T_PERIOD

Duty Cycle

T_HIGH

2.0

1.25

2.5V Clocking

Interface

0.4

T_LOW

T_RISE

T_FALL

T_PERIOD

Duty Cycle

T_HIGH

2.4

1.5

0.4

3.3V Clocking

Interface

T_LOW

T_RISE

T_FALL

Figure 8. Output Buffer

Ordering Information

Package

Name

Ordering Code

Package Type

48-pin SSOP (300 mils)

W195B

H

Intel is a registered trademark of Intel Corporation.

Document #: 38-00815

12

PRELIMINARY

W195B

Package Diagram

48-Pin Shrink Small Outline Package (SSOP, 300 mils)

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	W195BH
厂家：	CYPRESS
描述：	Processor Specific Clock Generator, 150MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48
文件：	总13页 (文件大小：143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W195BH [CYPRESS]

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