W196_技术文档

PRELIMINARY

W196

Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

CPU Cycle to Cycle Jitter: ..........................................250 ps

Features

CPU, PCI Output Edge Rate:.........................................≥1 V/ns

• Maximized EMI suppression using Cypress’s Spread

Spectrum Technology

CPU0:1 Output Skew: ................................................175 ps

PCI_F, PCI1:6 Output Skew: .......................................500 ps

CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)

REF2X/SEL48#, SCLOCK, SDATA: ............... 250-kΩ pull-up

FS1:............................................................250-kΩ pull-down

FS0:...................................................No pull-up or pull-down

• System frequency synthesizer for 440BX, 440ZX, and

VIA Apollo Pro-133

2

• I C programmable to 155 MHz (32 selectable

frequencies)

• Two skew-controlled copies of CPU output

• Seven copies of PCI output (synchronous w/CPU out-

put)

• One copy of 14.31818-MHz IOAPIC output

• One copy of 48-MHz USB output

Note:

Internal pull-up or pull-down resistors should not be re-

lied upon for setting I/O pins HIGH or LOW.

Table 1. Pin Selectable Frequency

• Selectable 24-/48-MHz clock is determined by resistor

straps on power up

• One high-drive output buffer that produces a copy of

the 14.318-MHz reference

FS1

1

FS0

1

CPU(0:1)

133.3 MHz

105 MHz

100 MHz

66.8 MHz

PCI

33.3 MHz

35 MHz

• Isolated core VDD pin for noise reduction

1

0

1

33.3 MHz

Key Specifications

0

Supply Voltages: ....................................... V

V

= 3.3V±5%

= 2.5V±5%

DDQ3

DDQ2

Block Diagram

Pin Configuration

VDDQ3

REF2X/SEL48#

GND

X1

X2

XTAL

OSC

VDDQ3

IOAPIC

PLL Ref Freq

X1

X2

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GND

2

REF2X/SEL48#

VDDQ3

VDDQ2

IOAPIC

VDDQ2

CPU0

GND

3

PCI_F

4

VDDQ2

CPU0

PCI1

5

PCI2

6

PCI3

7

CPU1

GND

PCI4

8

CPU1

VDDQ3

GND

VDDQ3

PCI5

9

10

11

12

13

14

PCI6

SDATA

SCLOCK

FS0

FS1

FS0

PLL 1

VDDQ3

48MHz

24_48MHz/FS1

÷2/÷3

GND

VDDQ3

PCI_F

PCI1

PCI2

PCI3

PCI4

PCI5

PCI6

GND

2

SDATA

SCLOCK

I C

LOGIC

VDDQ3

48MHz

PLL2

24_48MHz/FS1

GND

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 28, 1999, rev. **

PRELIMINARY

W196

Pin Definitions

No.

Type

Pin Name

Pin Description

CPU0:1

22, 21

O

CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by

FS0:1 or the serial data interface. See Table 1 and Table 5. Output voltage swing is

set by the voltage applied to VDDQ2.

PCI1:6

PCI_F

5, 6, 7, 8, 10,

11, 4

O

PCI Bus Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs

run synchronously to the CPU clock. Voltage swing is set by the power connection

to VDDQ3.

IOAPIC

24

13

14

O

I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage

swing is set by the power connection to VDDQ2.

48MHz

48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by

voltage applied to VDDQ3.

24_48MHz/FS1

I/O

24-MHz or 48-MHz Output/Frequency Select 1 Input: Frequency is set by the state

of pin 27 on power-up. This pin doubles as the select strap to determine device

operating frequency as described in Table 1.

REF2X/SEL48#

27

I/O

I/O Dual-Function REF2X and SEL48# Pin: Upon power-up, the state of SEL48#

is latched. The initial state is set by either a 10K resistor to GND or to V . A 10K

DD

resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to V , pin

DD

14 will output 2 4MHz. After 2 ms, the pin becomes a high-drive output that produces

a copy of 14.318 MHz.

FS0

16

I

I/O

I

Frequency Selection 0 Input: Selects CPU clock frequency as shown in Table 1

on page 1.

2

SDATA

SCLOCK

X1

18

I C Data Pin: Data should be presented to this input as described in the I C section

of this data sheet. Internal 250-kΩ pull-up resistor.

2

17

I C Clock Pin: The I C Data clock should be presented to this input as described in

2

the I C section of this data sheet.

1

I

Crystal Connection or External Reference Frequency Input: Connect to either

a 14.318-MHz crystal or other reference signal.

X2

2

I

Crystal Connection: An input connection for an external 14.318-MHz crystal. If

using an external reference, this pin must be left unconnected.

VDDQ3

VDDQ2

GND

9, 12, 20, 26

23, 25

P

G

Power Connection: Power supply for core logic and PLL circuitry, PCI, 48/24MHz,

and Reference output buffers. Connect to 3.3V supply.

Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to

2.5V supply.

3, 15, 19, 28

Ground Connections: Connect all ground pins to the common system ground

plane.

2

PRELIMINARY

W196

buffer is enabled, which converts the l/O pin into an operating

Functional Description

clock output. The 2-ms timer is started when V

reaches

DD

I/O Pin Operation

2.0V. The input bits can only be reset by turning V

off and

DD

then back on again.

Pins 14 and 27 are dual-purpose l/O pins. Upon power-up

these pins act as logic inputs, allowing the determination of

assigned device functions. A short time after power-up, the

logic state of these pins is latched and the pins become clock

outputs. This feature reduces device pin count by combining

clock outputs with input select pins.

It should be noted that the strapping resistors have no signifi-

cant effect on clock output signal integrity. The drive imped-

ance of the clock output is 20Ω (nominal), which is minimally

affected by the 10-kΩ strap to ground or V . As with the se-

DD

ries termination resistor, the output strapping resistor should

be placed as close to the l/O pin as possible in order to keep

the interconnecting trace short. The trace from the resistor to

An external 10-kΩ “strapping” resistor is connected between

the l/O pin and ground or V . Connection to ground sets a

DD

ground or V should be kept less than two inches in length to

DD

latch to “0”, connection to V sets a latch to “1.” Figure 1 and

DD

prevent system noise coupling during input logic sampling.

Figure 2 show two suggested methods for strapping resistor

connections.

When the clock output is enabled following the 2-ms input pe-

riod, a 14.318-MHz output frequency is delivered on the pin,

Upon W196 power-up, the first 2 ms of operation is used for

input logic selection. During this period, the REF2X and

24_48MHz clock output buffers are three-stated, allowing the

output strapping resistor on the l/O pin to pull the pin and its

associated capacitive clock load to either a logic HIGH or LOW

state. At the end of the 2-ms period, the established logic “0”

or “1” condition of the l/O pin is then latched. Next the output

assuming that V has stabilized. If V has not yet reached

DD

full value, output frequency initially may be below target but will

increase to target once V voltage has stabilized. In either

DD

case, a short output clock cycle may be produced from the

CPU clock outputs when the outputs are enabled.

V_DD

Output Strapping Resistor

Series Termination Resistor

10 kΩ

(Load Option 1)

Clock Load

W196

Output

Buffer

Power-on

Hold

Output

Low

Output Three-state

10 kΩ

(Load Option 0)

Reset

Timer

Q

D

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

Jumper Options

Output Strapping Resistor

V_DD

Series Termination Resistor

10 kΩ

Clock Load

W196

R

Output

Buffer

Power-on

Reset

Timer

Resistor Value R

Hold

Output

Low

Output Three-state

Q

D

Data

Latch

Figure 2. Input Logic Selection Through Jumper Option

3

PRELIMINARY

W196

chipset. Clock device register changes are normally made

upon system initialization, if required. The interface can also

be used during system operation for power management func-

tions. Table 2 summarizes the control functions of the serial

data interface.

Serial Data Interface

The W196 features a two-pin, serial data interface that can be

used to configure internal register settings that control partic-

ular device functions. Upon power-up, the W196 initializes with

default register settings. Therefore, the use of this serial data

interface is optional. The serial interface is write-only (to the

clock chip) and is the dedicated function of device pins SDATA

and SCLOCK. In motherboard applications, SDATA and

SCLOCK are typically driven by two logic outputs of the

Operation

Data is written to the W196 in ten bytes of eight bits each.

Bytes are written in the order shown in Table 3.

Table 2. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Clock Output Disable

Any individual clock output(s) can be disabled.

Disabled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI and

system power. Examples are clock outputs to un-

used PCI slots.

CPU Clock Frequency Provides CPU/PCI frequency selections beyond For alternate microprocessors and power man-

Selection

the selections that are provided by the FS0:1 pins. agement options. Smooth frequency transition al-

Frequency is changed in a smooth and controlled lows CPU frequency change under normalsystem

fashion.

operation.

Output Three-state

Test Mode

Puts all clock outputs into a high-impedance state. Production PCB testing.

All clock outputs toggle in relation to X1 input, in- Production PCB testing.

ternal PLL is bypassed. Refer to Table 4.

(Reserved)

Reserved function for future device revision or pro- No user application. Register bit must be written

duction device testing.

as 0.

Table 3. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

1

Slave Address

11010010

Commands the W196 to accept the bits in Data Bytes 3–6 for internal

register configuration. Since other devices may exist on the same com-

mon serial data bus, it is necessary to have a specific slave address for

each potential receiver. The slave receiver address for the W196 is

11010010. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver).

2

3

Command

Code

Don’t Care

Unused by the W196, therefore bit values are ignored (“don’t care”). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Command Code Byte is part of the standard serial com-

munication protocol and may be used when writing to another addressed

slave receiver on the serial data bus.

Byte Count

Unused by the W196, therefore bit values are ignored (“don’t care”). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Byte Count Byte is part of the standard serial communi-

cation protocol and may be used when writing to another addressed slave

receiver on the serial data bus.

4

5

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Don’t Care

Refer to Cypress SDRAM drivers.

6

7

Refer to Table 4

The data bits in these bytes set internal W196 registers that control device

operation. The data bits are only accepted when the Address Byte bit

sequence is 11010010, as noted above. For description of bit control

functions, refer to Table 4, Data Byte Serial Configuration Map.

8

9

10

4

PRELIMINARY

W196

Writing Data Bytes

Table 5 details additional frequency selections that are avail-

able through the serial data interface.

Each bit in the data bytes control a particular device function

except for the “reserved” bits which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit

7. Table 4 gives the bit formats for registers located in Data

Bytes 3–6.

Table 6 details the select functions for Byte 3, bits 1 and 0.

Table 4. Data Bytes 3–6 Serial Configuration Map

Affected Pin

Bit Control

Bit(s)

Pin No.

Pin Name

Control Function

SEL_3

0

1

Default

Data Byte 3

7

6

5

4

3

--

Refer to Table 5

0

SEL_2

SEL_1

SEL_0

Frequency Table

Selection

Frequency Controlled Frequency Controlled

byexternalFS0:1 pins by BYT3 SEL_(3:0)

(Table 1)

Table 5

2

--

(Reserved)

Bit 1 Bit 0

--

0

1–0

Function (See Table 6 for function details)

Spread Spectrum Off

10

0

1

0

1

0

1

Test Mode

Spread Spectrum On (default)

All Outputs Three-stated

Data Byte 4

7

--

14

--

(Reserved)

--

Active

--

0

1

0

1

0

1

6

24/48MHz Clock Output Disable

Low

--

5

--

(Reserved)

4

--

(Reserved)

--

3

--

(Reserved)

--

2

21

--

CPU1

--

Clock Output Disable

(Reserved)

Low

--

Active

--

1

0

22

CPU0

Clock Output Disable

Low

Active

Data Byte 5

7

4

11

10

-

PCI_F

PCI6

PCI5

--

Clock Output Disable

(Reserved)

Low

--

Active

--

1

0

1

6

5

4

3

8

PCI4

PCI3

PCI2

PCI1

Clock Output Disable

Low

Active

2

7

1

6

0

5

Data Byte 6

7

6

5

4

3

2

1

--

(Reserved)

--

0

1

0

--

IOAPIC

--

(Reserved)

24

--

Clock Output Disable

(Reserved)

Low

--

Active

--

(Reserved)

--

(Reserved)

--

[1]

27

REF2X

Clock Output Disable

Low

Active

1

[1]

0

1

Note:

1. Bits 0 and 1 of Data Byte 6 in Table 4 must be programmed as the same value.

5

PRELIMINARY

W196

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Data Byte 3, Bit [7:4, 1:0]

Output Frequency

If Spread Is On

Bit 7

Bit 6

Bit 5

Bit 4

CPU, SDRAM

Clocks (MHz)

PCI Clocks

(MHz)

Spread Percentage

Bit [1:0]

00

10

SEL_3

SEL_2

SEL_1

SEL_0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

78

81

39

40.5

37.8

33.4

39

OFF

113.5

66.8

117

118.5

122

100

126

135

137

138.5

142

144

155

133.3

124

75

OFF

39.5

37.3

33.3

31.5

33.75

34.25

34.62

35.5

36

OFF

38.75

33.3

41.3

37.5

41.65

33.4

30

OFF

±0.5% Center

83.3

66.8

90

112

95

37.3

31.67

33.3

40

100

120

115

110

105

140

150

124

133.3

38.3

36.67

35

37.5

31

33.3

Table 6. Select Function for Data Byte 3, Bits 0:1

Input Conditions

Output Conditions

REF2X,

Data Byte 3

Function

Spread Spectrum OFF

Test Mode

Bit 1

Bit 0

CPU0:1 PCI_F, PCI1:6

IOAPIC

14.318 MHz

X1

48MHZ

48 MHz

X1/2

24MHZ

24 MHz

X1/4

0

1

0

1

0

1

Note 2

X1/2

Note 2

CPU/2, 3, or 4

±0.5%

Spread Spectrum ON (default)

±0.5%

Hi-Z

14.318 MHz

Hi-Z

48 MHz

Hi-Z

24 MHz

Hi-Z

Three-state

Hi-Z

Note:

2. CPU and PCI frequency selections are listed in Table 1 and Table 5.

6

PRELIMINARY

W196

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-

manent damage to the device. These represent a stress rating

only. Operation of the device at these or any other conditions

above those specified in the operating sections of this specifi-

cation is not implied. Maximum conditions for extended peri-

ods may affect reliability.

Parameter

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

–0.5 to +7.0

–65 to +150

0 to +70

Unit

V

, V

DD IN

T

°C

kV

STG

T

Operating Temperature

A

T

Ambient Temperature under Bias

Input ESD Protection

–55 to +125

2 (min.)

B

ESD

PROT

DC Electrical Characteristics: T = 0°C to +70°C, V

= 3.3V±5%, V = 2.5V±5%

DDQ2

A

DDQ3

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

I

Combined 3.3V Supply Current

CPU0:1 =100 MHz

Outputs Loaded

85

30

mA

DDQ3

[3]

I

Combined 2.5V Supply Current

CPU0:1 =100 MHz

DDQ3

[3]

Outputs Loaded

Logic Inputs

V

Input Low Voltage

Input High Voltage

GND – 0.3

0.8

V + 0.3

DD

V

IL

2.0

IH

[4]

I

Input Low Current

–25

µA

IL

IH

[4]

Input High Current

10

Clock Outputs

V

Output Low Voltage

I

= 1 mA

= –1 mA

= 1.25V

= 1.5V

50

mV

V

OL

OH

V

Output High Voltage

3.1

2.2

45

OH

V

Output High Voltage CPU0:1/IOAPIC

V

OH

I

Output Low Current

CPU0:1

V

60

110

90

80

140

170

90

mA

OL

PCI_F, PCI1:6

IOAPIC

85

= 1.25V

= 1.5V

65

REF2X

110

50

140

70

48MHz, 24MHz

= 1.5V

I

Output High Current CPU0:1

PCI_F, PCI1:6

= 1.25V

= 1.5V

35

50

80

OH

60

95

130

140

150

90

IOAPIC

= 1.25V

= 1.5V

45

87

REF2X

100

50

130

70

48MHz, 24MHz

= 1.5V

Crystal Oscillator

X1 Input Threshold Voltage

[5]

V

= 3.3V

1.65

14

V

TH

DDQ3

C

Load Capacitance, as seen by

External Crystal

pF

LOAD

[6]

[7]

C

X1 Input Capacitance

Pin X2 unconnected

28

pF

IN,X1

Notes:

3. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.

4. W196 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).

5. X1 input threshold voltage (typical) is V_DD/2.

6. The W196 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is

14 pF; this includes typical stray capacitance of short PCB traces to crystal.

7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

7

PRELIMINARY

W196

DC Electrical Characteristics: T = 0°C to +70°C, V

= 3.3V±5%, V

= 2.5V±5% (continued)

DDQ2

A

DDQ3

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Pin Capacitance/Inductance

C

Input Pin Capacitance

Output Pin Capacitance

Input Pin Inductance

Except X1 and X2

5

6

7

pF

nH

IN

OUT

IN

L

AC Electrical Characteristics

T = 0°C to +70°C, V

= 3.3V±5%,V

= 2.5V± 5%, f

= 14.31818 MHz

XTL

A

DDQ3

DDQ2

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output; Spread Spectrum clocking is disabled.

CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)

CPU = 66.8 MHz

CPU = 100 MHz

Parameter

Description

Period

Test Condition/Comments

Measured on rising edge at 1.25V

Duration of clock cycle above 2.0V

Duration of clock cycle below 0.4V

Min. Typ. Max. Min. Typ. Max. Unit

t

15

5.2

5.0

1

15.5

10

3.0

2.8

1

10.5

ns

P

H

L

High Time

Low Time

ns

Output Rise Edge Rate Measured from 0.4V to 2.0V

Output Fall Edge Rate Measured from 2.0V to 0.4V

4

V/ns

%

R

F

D

1

Duty Cycle

Measured on rising and falling edge at

45

55

45

55

1.25V

t

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.25V. Max-

imum difference of cycle time between

two adjacent cycles.

200

250

ps

JC

t

f

Output Skew

Measured on rising edge at 1.25V

175

3

175

3

ps

SK

Frequency Stabiliza-

tion from Power-up

(cold start)

Assumes full supply voltage reached

within 1 ms from power-up. Short cycles

exist prior to frequency stabilization.

ms

ST

Z

AC Output Impedance Average value during switching transi-

tion. Used for determining series termi-

nation value.

20

Ω

o

8

PRELIMINARY

W196

PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF

CPU = 66.8/100 MHz

Parameter

Description

Test Condition/Comments

Measured on rising edge at 1.5V

Min.

30

12

1

Typ. Max. Unit

t

Period

ns

P

High Time

Duration of clock cycle above 2.4V

Duration of clock cycle below 0.4V

Measured from 0.4V to 2.4V

H

L

Low Time

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

4

V/ns

%

R

F

Measured from 2.4V to 0.4V

1

Measured on rising and falling edge at 1.5V

45

55

250

D

JC

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum

ps

difference of cycle time between two adjacent cycles.

t

Output Skew

Measured on rising edge at 1.5V

500

4

ps

ns

SK

CPU to PCI Clock Skew

Covers all CPU/PCI outputs. Measured on rising

edge at 1.5V. CPU leads PCI output.

1

O

f

Frequency Stabilization

from Power-up (cold start) from power-up. Short cycles exist prior to frequency

stabilization.

Assumes full supply voltage reached within 1 ms

3

ms

ST

Z

AC Output Impedance

Average value during switching transition. Used for

determining series termination value.

20

Ω

o

IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 66.8/100 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.0V

Min.

Typ.

Max.

Unit

MHz

V/ns

%

f

14.31818

t

f

1

4

R

Measured from 2.0V to 0.4V

F

Measured on rising and falling edge at 1.25V

45

55

1.5

D

Frequency Stabilization

Assumes full supply voltage reached within

ms

ST

from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

15

Ω

o

REF2X Clock Output (Lump Capacitance Test Load = 20 pF)

CPU = 66.8/100 MHz

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.4V

Min.

Typ.

Max. Unit

f

14.318

MHz

t

f

0.5

45

2

V/ns

%

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

55

3

D

FrequencyStabilizationfrom Assumes full supply voltage reached within

ms

ST

Power-up (cold start)

AC Output Impedance

1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

Average value during switching transition. Used

for determining series termination value.

15

Ω

o

9

PRELIMINARY

W196

48-MHZ and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max. Unit

f

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

48.008

24.004

MHz

f

Deviation from 48 MHz

PLL Ratio

(48.008 – 48)/48

+167

ppm

D

m/n

(14.31818 MHz x 57/17 = 48.008 MHz)

Measured from 0.4V to 2.4V

57/17, 57/34

t

f

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

0.5

45

2

V/ns

%

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

Assumes full supply voltage reached within 1 ms

55

3

D

Frequency Stabilization

ms

ST

from Power-up (cold start) from power-up. Short cycles exist prior to fre-

quency stabilization.

Z

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

25

Ω

o

Ordering Information

Package

Name

Ordering Code

Package Type

W196

G

28-pin SOIC (300 mils)

Document #: 38-00842

10

PRELIMINARY

W196

Package Diagram

28-Pin Small Outline Integrated Circuit (SOIC, 300 mils)

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	W196
厂家：	CYPRESS
描述：	Spread Spectrum FTG for 440BX and VIA Apollo Pro-133 扩频FTG的440BX和威盛Apollo Pro的-133
文件：	总11页 (文件大小：141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W196 [CYPRESS]

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