U631H16SC25G1 [CYPRESS]
2KX8 NON-VOLATILE SRAM, 25ns, PDSO28, 0.300 INCH, LEAD FREE, SOP-28;
| 型号： | U631H16SC25G1 |
| 厂家： | 
CYPRESS |
| 描述： | 2KX8 NON-VOLATILE SRAM, 25ns, PDSO28, 0.300 INCH, LEAD FREE, SOP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U631H16
SoftStore 2K x 8 nvSRAM
Features
tion), or from the EEPROM to the
SRAM (the RECALL ) operation)
are initiated through software
sequences.
! Packages: PDIP28 (300 mil)
PDIP28 (600 mil)
! High-performance CMOS nonvola-
tile static RAM 2048 x 8 bits
! 25, 35 and 45 ns Access Times
! 12, 20 and 25 ns Output Enable
Access Times
SOP28 (300 mil)
SOP24 (300 mil)
The U631H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Description
! Software STORE Initiation
(STORE Cycle Time < 10 ms)
! Automatic STORE Timing
! 105 STORE cycles to EEPROM
! 10 years data retention in
EEPROM
The U631H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
! Automatic RECALL on Power Up
! Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
! Unlimited RECALL cycles from
EEPROM
! Unlimited Read and Write to
SRAM
Internally, RECALL is a two step
procedure. First, the SRAM data is
The U631H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
! Single 5 V ± 10 % Operation
! Operating temperature ranges:
0 to 70 °C
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM.
-40 to 85 °C
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
! QS 9000 Quality Standard
! ESD characterization according
! MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Data transfers from the SRAM to
the EEPROM (the STORE opera-
Pin Description
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
1
2
3
4
5
6
7
8
n.c.
n.c.
A7
A6
A5
A4
A3
A2
A1
VCC
W
n.c.
A8
A9
n.c.
G
1
2
3
4
5
6
7
8
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
W
G
Signal Name Signal Description
A0 - A10
DQ0 - DQ7
Address Inputs
Data In/Out
PDIP
SOP
28
A10
E
SOP
24
Chip Enable
E
A10
E
Output Enable
Write Enable
Power Supply Voltage
Ground
G
W
VCC
VSS
9
DQ7
DQ6
DQ5
DQ4
DQ3
9
10
11
12
13
14
A0
DQ7
DQ6
DQ5
DQ4
DQ3
10
11
12
DQ0
DQ1
DQ2
VSS
17
16
15
Top View
Top View
1
April 20, 2004
U631H16
Block Diagram
EEPROM Array
32 x (64 x 8)
VCC
VSS
STORE
RECALL
A5
A6
A7
A8
A9
SRAM
Array
32 Rows x
64 x 8 Columns
Store/
Recall
Control
VCC
DQ0
DQ1
Column I/O
DQ2
DQ3
Software
Detect
Column Decoder
A0 - A10
DQ4
DQ5
DQ6
G
A0 A1 A2 A3 A4A10
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
High-Z
*
*
H
H
H
L
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
Output Voltage
VO
PD
V
Power Dissipation
W
Operating Temperature
C-Type
K-Type
0
70
85
°C
°C
Ta
-40
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
April 20, 2004
U631H16
Recommended Operation
Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
Input Low Voltage
Input High Voltage
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC
VIL
= 5.5 V
= 0.8 V
= 2.2 V
VIH
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
90
80
75
95
85
80
mA
mA
mA
Average Supply Current during
STOREc
ICC2
VCC
E
= 5.5 V
6
7
mA
≥ VCC-0.2 V
≥ VCC-0.2 V
≤ 0.2 V
W
VIL
VIH
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1 VCC
E
= 5.5 V
≥ VIH
tc
tc
tc
= 25 ns
= 35 ns
= 45 ns
30
23
20
34
27
23
mA
mA
mA
Average Supply Current
at tcR = 200 nsb
ICC3
VCC
W
= 5.5 V
15
15
mA
≥ VCC-0.2 V
≤ 0.2 V
(Cycling CMOS Input Levels)
VIL
VIH
≥ VCC-0.2 V
Standby Supply Currentd
ICC(SB)
VCC
E
= 5.5 V
1
1
mA
(Stable CMOS Input Levels)
≥ VCC-0.2 V
≤ 0.2 V
VIL
VIH
≥ VCC-0.2 V
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c:
ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
3
April 20, 2004
U631H16
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
8
2.4
8
V
V
0.4
-4
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
1
1
1
µA
µA
=
0 V
-1
-1
-1
-1
Output Leakage Current
V
= 5.5 V
CC
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VOH
VOL
= 5.5 V
µA
µA
=
0 V
SRAM Memory Operations
Symbol
25
35
45
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min. Max. Min. Max. Min. Max.
1
2
3
4
5
6
7
8
9
Read Cycle Timef
Address Access Time to Data Validg
tAVAV
tAVQV
tELQV
tcR
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
25
25
12
13
13
35
35
20
17
17
45
45
25
20
20
Chip Enable Access Time to Data Valid
ta(E)
Output Enable Access Time to Data Valid tGLQV
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
E HIGH to Output in High-Zh
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
tEHQZ
tGHQZ
tELQX
5
0
3
0
5
0
3
0
5
0
3
0
G LOW to Output in Low-Z
Output Hold Time after Addr. Changeg
tGLQX
tAXQX
tELICCH
tEHICCL
19 Chip Enable to Power Activee
11 Chip Disable to Power Standbyd, e
25
35
45
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or at the same time with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
4
April 20, 2004
U631H16
f
=
=
VIL, W = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
tcR
(1)
Address Valid
ta(A)
Ai
(2)
DQi
Output Data Valid
Previous Data Valid
Output
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
(1)
Ai
E
Address Valid
(2)
ta(E) (3)
ta(A)
tPD
(5)
(11)
tdis(E)
ten(E) (7)
G
ta(G)
(4)
tdis(G)
(6)
ten(G)
(8)
DQi
High Impedance
Output Data Valid
Output
t
PU (10)
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
25
35
45
Switching Characteristics
Write Cycle
No.
Unit
IEC
Min. Max. Min. Max. Min. Max.
12 Write Cycle Time
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
25
20
20
0
35
30
30
0
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tAVWL
tAVWH
tELWH
tsu(A-WH)
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
20
20
20
12
0
30
30
30
18
0
35
35
35
20
0
tsu(E)
tw(E)
tsu(D)
th(D)
tELEH
tDVEH
tEHDX
tEHAX
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
th(A)
0
0
0
tdis(W)
ten(W)
10
13
15
5
5
5
5
April 20, 2004
U631H16
Write Cycle #1: W-controlledj
tcW
(12)
Address Valid
tsu(E)
Ai
E
t
(17)
h(A) (21)
tsu(A-WH)
(16)
tw(W)
(13)
W
t
su(A) (15)
tsu(D)
th(D)
(19)
Input Data Valid
ten(W)
(20)
DQi
Input
tdis(W)
(22)
(23)
High Impedance
DQi
Previous Data Valid
Output
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
t
su(A) (15)
tw(E)
th(A)
(18)
(21)
tsu(W)
(14)
W
t
t
h(D) (20)
su(D)(19)
DQi
Input
Input Data Valid
High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
>
VIH during address transitions.
j: E or W must be
6
April 20, 2004
U631H16
Nonvolatile Memory Operations
Symbol
STORE Cycle Inhibit and
No.
Min.
Max.
Unit
Automatic Power Up RECALL
Alt.
tRESTORE
VSWITCH
IEC
24 Power Up RECALL Durationk, e
650
4.5
µs
Low Voltage Trigger Level
4.0
V
k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE Cycle Inhibit and Automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Software Mode Selection
A10 - A0
(hex)
E
W
Mode
I/O
Power
Notes
L
H
000
555
2AA
7FF
0F0
70F
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
ICC2
L
H
000
555
2AA
7FF
0F0
70E
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
l: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA,
7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C.
m: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
7
April 20, 2004
U631H16
25
35
45
Symbol
Unit
No. Software Controlled STORE/RECALL
Cyclel, n
Alt.
tAVAV
IEC
Min. Max. Min. Max. Min. Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactiveo
27 STORE Cycle Timep
tcR
25
35
45
ns
ns
ms
µs
ns
ns
ns
tELQZ tdis(E)SR
tELQXS td(E)S
tELQXR td(E)R
tAVELN tsu(A)SR
tELEHN tw(E)SR
tEHAXN th(A)SR
600
10
600
10
600
10
28 RECALL Cycle Timeq
20
20
20
29 Address Setup to Chip Enabler
30 Chip Enable Pulse Widthr, s
31 Chip Disable to Address Changer
0
20
0
0
25
0
0
35
0
n: The software sequence is clocked with E controlled READs.
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cycler, s, t, u (E = HIGH after STORE initiation)
tcR
(25)
tcR
(25)
ADDRESS 6
ADDRESS 1
Ai
E
th(A)SR
(31)
tw(E)SR
(30)
tw(E)SR
(30)
t
dis(E)(5)
(31)
th(A)SR
tsu(A)SR
(29)
(29)
td(E)R
td(E)S
tsu(A)SR
(28)
(27)
DQi
High Impedance
VALID
tdis(E)SR
Output
VALID
(26)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tcR
(25)
ADDRESS 1
tw(E)SR
ADDRESS 6
Ai
E
th(A)SR
(31)
(30)
(29)
(31)
(29)
tsu(A)SR
High Impedance
th(A)SR
td(E)S
td(E)R (28)
tsu(A)SR
(27)
DQi
VALID
Output
VALID
tdis(E)SR
(26)
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H16 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
8
April 20, 2004
U631H16
Test Configuration for Functional Check
5 V
w
VCC
A0
A1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A2
480
A3
A4
VIH
VIL
A5
A6
A7
A8
A9
A10
VO
30 pF v
E
W
G
255
VSS
v: In measurement of tdis-times and ten-times the capacitance is 5 pF.
w: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC = 5.0 V
Input Capacitance
CI
8
pF
VI
f
= VSS
= 1 MHz
= 25 °C
Output Capacitance
CO
7
pF
Ta
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
U631H16
S
C
25
Type
Leadfree Option
blank= Standard Package
ESD Class
G1 = Leadfree Green Package x
blank > 2000 V
B
> 1000 V
Access Time
25 = 25 ns
Package
35 = 35 ns x
45 = 45 ns x
D = PDIP28 (300 mil)
D1= PDIP28 (600 mil)
S = SOP28 (300 mil)
S1 = SOP24 (300 mil)
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
x: on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
U631H16SC
25 Z 0425
G1
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Internal Code
April 20, 2004
Leadfree Green Package
9
U631H16
Device Operation
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
The U631H16 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted and no STORE or RECALL will take
place.
To initiate the STORE cycle the following READ
sequence must be performed:
SRAM READ
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
000
555
(hex) Valid READ
(hex) Valid READ
The U631H16 performs a READ cycle whenever E and
G are LOW while W is HIGH. The address specified on
pins A0 - A10 determines which of the 2048 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of tcR. If the READ is initiated by E or G, the outputs will
be valid at ta(E) or at ta(G), whichever is later. The data
outputs will repeatedly respond to address changes
within the tcR access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
2AA (hex) Valid READ
7FF
0F0
70F
(hex) Valid READ
(hex) Valid READ
(hex) Initiate STORE
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence. It is not
necessary that G is LOW for the sequence to be valid.
After the tSTORE cycle time has been fulfilled, the SRAM
will again be activated for READ and WRITE operation.
SRAM WRITE
Software Nonvolatile RECALL
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
ei-ther E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
t
su(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
000
555
(hex) Valid READ
(hex) Valid READ
2AA (hex) Valid READ
7FF
0F0
70E
(hex) Valid READ
(hex) Valid READ
(hex) Initiate RECALL
Noise Consideration
The U631H16 is a high speed memory and therefore it
must have a high frequency bypass capacitor of appro-
ximately 0.1 µF connected between VCC and VSS using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise pro-
blems.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Automatic Power Up RECALL
Software Nonvolatile STORE
On power up, once VCC exceeds the sense voltage of
The U631H16 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U631H16 implements nonvolatile operation
while remaining compatible with standard 2K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is first performed, followed by
VSWITCH, a RECALL cycle is automatically initiated. The
voltage on the VCC pin must not frop belwo VSWITCH
once it has risen above it in order for the RECALL to
operate properly. Due to this automatic RECALL,
SRAM operation cannot commence until tRESTORE after
V
CC exceeds VSWITCH.
10
April 20, 2004
U631H16
If the U631H16 is in a WRITE state at the end of power
up RECALL, the SRAM data will be corrupted.
Low Average Active Power
To help avoid this situation, a 10 KΩ resistor should be
The U631H16 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
connected between W and VCC
.
Hardware Protection
The U631H16 offers hardware protection against inad-
vertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE opera-
tion will be inhibited.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
11
April 20, 2004
U631H16
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon
it. The information in this document describes the type of component and shall not be considered as assured cha-
racteristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms
and conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
April 20, 2004
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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