U631H256BSM35 [CYPRESS]
32KX8 NON-VOLATILE SRAM, 35ns, PDSO28, 0.330 INCH, SOP-28;
| 型号： | U631H256BSM35 |
| 厂家： | 
CYPRESS |
| 描述： | 32KX8 NON-VOLATILE SRAM, 35ns, PDSO28, 0.330 INCH, SOP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U631H256xSM
SoftStore 32K x 8 nvSRAM
Features
Description
F High-performance CMOS non-
The U631H256SM has two sepa- Once a STORE cycle is initiated,
volatile static RAM 32768 x 8 bits rate modes of operation: SRAM further input or output are disabled
F 35 ns Access Time mode and nonvolatile mode. In until the cycle is completed.
F 15 ns Output Enable Access Time SRAM mode, the memory operates Because a sequence of addresses
F Software STORE Initiation
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
as an ordinary static RAM. In non- is used for STORE initiation, it is
volatile operation, data is transfer- important that no other read or
red in parallel from SRAM to write accesses intervene in the
EEPROM or from EEPROM to sequence or the sequence will be
SRAM. In this mode SRAM aborted.
F Automatic RECALL on Power Up functions are disabled.
Internally, RECALL is a two step
F Software RECALL Initiation
F Unlimited RECALL cycles from
EEPROM
F Unlimited Read and Write to
SRAM
F Single 5 V ± 10 % Operation
F Operating temperature range
-55 to 125 °C
F CECC 90000 Quality Standard
F ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code Num-
bers)
The U631H256SM is a fast static procedure. First, the SRAM data is
RAM (35 ns Access Time), with a cleared and second, the nonvola-
nonvolatile electrically erasable tile information is transferred into
PROM (EEPROM) element incor- the SRAM cells.
porated in each static memory cell. The RECALL operation in no way
The SRAM can be read and written alters the data in the EEPROM
an unlimited number of times, while cells. The nonvolatile data can be
independent nonvolatile data resi- recalled an unlimited number of
des in EEPROM. Data transfers times.
from the SRAM to the EEPROM The U631H256SM is pin compati-
(the STORE operation), or from the ble with standard SRAMs.
EEPROM to the SRAM (the
RECALL operation) are initiated
F Package: SOP28 (330 mil)
F Latch-up-immunity according
JEDEC 17 (trigger current ± 200
mA at 125 °C)
through software sequences.
The U631H256SM combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
Pin Description
Pin Configuration
1
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
28
27
26
25
24
23
22
21
20
19
18
VCC
2
W
3
A13
A8
A9
A11
G
Signal Name Signal Description
4
A0 - A14
Address Inputs
Data In/Out
5
DQ0 - DQ7
6
7
Chip Enable
E
SOP
8
A10
Output Enable
Write Enable
Power Supply Voltage
Ground
G
9
E
W
10
11
DQ7
DQ6
DQ5
VCC
VSS
DQ0
DQ1
DQ2
VSS
12
13
14
17
16
15
DQ4
DQ3
Top View
1
September 25, 2002
U631H256xSM
Block Diagram
EEPROM Array
512 x (64 x 8)
VCC
VSS
A5
A6
A7
A8
STORE
RECALL
SRAM
Array
A9
A11
512 Rows x
A12
A13
A14
64 x 8 Columns
Store/
Recall
Control
VCC
DQ0
DQ1
Column I/O
DQ2
DQ3
Software
Detect
Column Decoder
A0 - A13
DQ4
DQ5
DQ6
G
A0 A1 A2 A3 A4A10
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
L
L
L
High-Z
High-Z
*
*
Internal Read
H
H
L
Read
Write
H
L
Data Outputs Low-Z
Data Inputs High-Z
*
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of
VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
VCC+0.5
VCC+0.5
1
V
V
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
Storage Temperature
W
°C
°C
-55
-65
125
Tstg
150
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
September 25, 2002
U631H256xSM
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
Input Low Voltage
Input High Voltage
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
VIH
VCC+0.3
DC Characteristics
Symbol
Conditions
Min.
Max.
Unit
Operating Supply Currentb
ICC1
VCC
VIL
VIH
= 5.5 V
= 0.8 V
= 2.2 V
tc
= 35 ns
80
7
mA
mA
Average Supply Current during
STOREc
ICC2
VCC
E
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Average Supply Current
at tcR = 200 nsb
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
15
mA
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1
VCC
E
= 5.5 V
≥ VIH
tc
= 35 ns
38
2
mA
mA
Standby Supply Curentd
ICC(SB)
VCC
E
VIL
VIH
= 5.5 V
≥ VCC-0.2 V
≤ 0.2 V
(Stable CMOS Input Levels)
≥ VCC-0.2 V
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c:
ICC2 is the average current required for the duration of the STORE cycle (tSTORE).
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
3
September 25, 2002
U631H256xSM
DC Characteristics
Symbol
Conditions
Min.
Max.
Unit
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
V
V
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
8
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
µA
µA
=
0 V
-1
-1
Output Leakage Current
VCC
E or G ≥ VIH
VOH
VOL
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
= 5.5 V
1
µA
µA
=
0 V
SRAM Memory Operations
Symbol
35
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min.
Max.
1
2
3
4
5
6
7
8
9
Read Cycle Timef
tAVAV
tAVQV
tELQV
tcR
ta(A)
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Zh
35
35
15
13
13
tGLQV
tEHQZ
tGHQZ
tELQX
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
5
0
3
0
G LOW to Output in Low-Z
tGLQX
tAXQX
tELICCH
tEHICCL
Output Hold Time after Addr. Changeg
10 Chip Enable to Power Activee
tPU
11 Chip Disable to Power Standbyd, e
tPD
35
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both Low.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
4
September 25, 2002
U631H256xSM
f
=
=
VIL, W = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
tcR
(1)
Ai
Address Valid
ta(A)
(2)
DQi
Output
Output Data Valid
Previous Data Valid
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
(1)
Ai
E
Address Valid
ta(A)
(2)
ta(E)
(3)
t
dis(E) (5)
t
PD (11)
ten(E)
(7)
G
ta(G)
(4)
tdis(G)
(6)
ten(G)
(10)
(8)
DQi
Output
High Impedance
Output Data Valid
tPU
ACTIVE
ICC
STANDBY
Symbol
Alt. #1 Alt. #2
35
Switching Characteristics
Write Cycle
No.
Unit
IEC
Min.
Max.
12 Write Cycle Time
t
t
t
cW
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
13 Write Pulse Width
t
t
w(W)
WLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
t
t
su(W)
WLEH
t
t
t
su(A)
AVWL
AVEL
AVEH
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
t
t
t
25
25
25
12
0
AVWH
su(A-WH)
t
t
su(E)
ELWH
t
t
w(E)
ELEH
DVEH
EHDX
EHAX
t
t
t
t
t
t
t
su(D)
DVWH
WHDX
WHAX
t
h(D)
h(A)
t
0
h, i
22 W LOW to Output in High-Z
t
t
13
WLQZ
dis(W)
23 W HIGH to Output in Low-Z
t
t
5
WHQX
en(W)
5
September 25, 2002
U631H256xSM
Write Cycle #1: W-controlledj
tcW (12)
Ai
Address Valid
(17)
tsu(E)
th(A)
(21)
E
tsu(A-WH)
(16)
tw(W)
W
(13)
tsu(A)
(15)
tsu(D) (19)
Input Data Valid
ten(W)
th(D)
(20)
DQi
Input
t
dis(W) (22)
(23)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
tw(E)
(18)
tsu(A)
(15)
th(A)
(21)
tsu(W)
(14)
W
t
th(D)
su(D) (19)
(20)
DQi
Input Data Valid
High Impedance
Input
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
>
j: E or W must be
VIH during address transitions.
6
September 25, 2002
U631H256xSM
Nonvolatile Memory Operations
Symbol
Alt. IEC
STORE Cycle Inhibit and
No.
Min.
Max.
Unit
Automatic Power Up RECALL
24 Power Up RECALL Durationk
Low Voltage Trigger Level
tRESTORE
VSWITCH
650
4.5
µs
4.0
V
k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE Cycle Inhibit and Automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Software Mode Selection
A13 - A0
E
W
Mode
I/O
Power
Notes
(hex)
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
Nonvolatile STORE
ICC2
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
Nonvolatile RECALL
l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
m: While there are 15 addresses on the U631H256SM, only the lower 14 are used to control software modes.
7
September 25, 2002
U631H256xSM
35
Symbol
No.
Unit
Software Controlled STORE/RECALL Cyclel, n
Alt.
tAVAV
tELQZ
IEC
tcR
Min.
Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactiveo
27 STORE Cycle Timep
35
ns
ns
ms
µs
ns
ns
ns
tdis(E)SR
td(E)S
600
10
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
28 RECALL Cycle Timeq
td(E)R
20
29 Address Setup to Chip Enabler
30 Chip Enable Pulse Widthr, s
31 Chip Disable to Address Changer
tsu(A)SR
tw(E)SR
th(A)SR
0
25
0
n: The software sequence is clocked with E controlled READs
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
SWITCH once it has been exceeded for the RECALL to function properly.
V
r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cyclet, u (E = HIGH after STORE initiation)
tcR
tcR
(25)
(25)
ADDRESS 1
Ai
E
ADDRESS 6
tw(E)SR
(30)
tsu(A)SR
(29)
th(A)SR
(31)
t
td(E)R
d(E)S (27)
(28)
High Impedance
DQi
Output
VALID
tdis(E)SR
VALID
(26)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tcR
(25)
ADDRESS 6
th(A)SR
ADDRESS 1
Ai
E
(31)
tw(E)SR
(30)
tsu(A)SR
(29)
tsu(A)SR
(29)
th(A)SR
(31)
td(E)S
td(E)R (28)
(27)
DQi
Output
High Impedance
VALID
VALID
tdis(E)SR
(26)
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the U631H256SM performs a
STORE or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
8
September 25, 2002
U631H256xSM
Test Configuration for Functional Check
5 V
w
A0
A1
VCC
A2
A3
A4
A5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
480
A6
A7
VIH
A8
A9
A10
A11
A12
VIL
VO
A13
A14
30 pF v
E
W
G
255
VSS
v: In measurement of tdis-times and ten-times the capacitance is 5 pF.
w: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC
VI
f
= 5.0 V
= VSS
= 1 MHz
= 25 °C
Input Capacitance
CI
8
pF
Output Capacitance
CO
7
pF
Ta
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U631H256
S
M
35
C
Type
ESD Class
blank > 2000 Vx
B > 1000 V
C > 500 V
Package
Access Time
35 = 35 ns
S = SOP28 (330 mil) Type 1
Operating Temperature Range
M = -55 to 125 °C
x:
ESD protection > 2000 V under development
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
9
September 25, 2002
U631H256xSM
Device Operation
program of the nonvolatile elements. Once a STORE
cycle is initiated, further inputs and outputs are disabled
until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted and no STORE or RECALL will take
place.
The U631H256SM has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. The memory
operates in SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM shadow (the STORE operation) or from
EEPROM to SRAM (the RECALL operation). In this
mode SRAM functions are disabled.
To initiate the STORE cycle the following READ
sequence must be performed:
SRAM READ
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0FC0 (hex) Initiate STORE
Cycle
The U631H256SM performs a READ cycle whenever E
and G are LOW while W is HIGH. The address speci-
fied on pins A0 - A14 determines which of the 32768
data bytes will be accessed. When the READ is initia-
ted by an address transition, the outputs will be valid
after a delay of tcR. If the READ is initiated by E or G,
the outputs will be valid at ta(E) or at ta(G), whichever is
later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W is brought LOW.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
t
su(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0C63 (hex) Initiate RECALL
Cycle
Noise Consideration
The U631H256SM is a high speed memory and there-
fore must have a high frequency bypass capacitor of
approximately 0.1 µF connected between VCC and VSS
using leads and traces that are as short as possible. As
with all high speed CMOS ICs, normal carefull routing
of power, ground and signals will help prevent noise
problems.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Software Nonvolatile STORE
The U631H256SM software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U631H256SM implements nonvolatile opera-
tion while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is first performed, followed by a
Automatic Power Up RECALL
On power up, once VCC exceeds the sense voltage of
VSWITCH, a RECALL cycle is automatically initiated. The
voltage on the VCC pin must not drop below VSWITCH
once it has risen above it in order for the RECALL to
operate properly. Due to this automatic RECALL,
10
September 25, 2002
U631H256xSM
SRAM operation cannot commence until tRESTORE after
CC exceeds VSWITCH
Low Average Active Power
V
.
If the U631H256SM is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
The U631H256SM has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but
the access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
connected between W and VCC
.
Hardware Protection
The overall average current drawn by the part depends
on the following items:
The U631H256SM offers hardware protection against
inadvertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE opera-
tion will be inhibited.
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
11
September 25, 2002
U631H256xSM
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
September 25, 2002
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