U631H256 [SIMTEK]
SoftStore 32K x 8 nvSRAM; SoftStore 32K ×8的nvSRAM
| 型号： | U631H256 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | SoftStore 32K x 8 nvSRAM |
| 文件： | 总13页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U631H256
SoftStore 32K x 8 nvSRAM
Not Recommended For New Designs
Features
Description
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
25 ns Access Times
10 ns Output Enable Access
Times
Software STORE Initiation
Automatic STORE Timing
106 STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
The U631H256 has two separate Once a STORE cycle is initiated,
modes of operation: SRAM mode further input or output are disabled
and nonvolatile mode. In SRAM until the cycle is completed.
mode, the memory operates as an Because a sequence of addresses
ordinary static RAM. In nonvolatile is used for STORE initiation, it is
operation, data is transferred in important that no other read or
parallel from SRAM to EEPROM or write accesses intervene in the
from EEPROM to SRAM. In this sequence or the sequence will be
mode SRAM functions are disab- aborted.
led.
Internally, RECALL is a two step
procedure. First, the SRAM data is
The U631H256 is a fast static RAM
(25 ns), with a nonvolatile electri- cleared and second, the nonvola-
cally erasable PROM (EEPROM) tile information is transferred into
element incorporated in each static the SRAM cells.
Unlimited Read and Write to
SRAM
memory cell. The SRAM can be The RECALL operation in no way
read and written an unlimited num- alters the data in the EEPROM
ber of times, while independent cells. The nonvolatile data can be
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70 °C
nonvolatile
data
resides
in recalled an unlimited number of
EEPROM. Data transfers from the times.
SRAM to the EEPROM (the The U631H256 is pin compatible
STORE operation), or from the with standard SRAMs.
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Package: SOP28 (330 mil)
The U631H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Pin Description
Pin Configuration
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
2
3
A13
A8
Signal Name Signal Description
4
A6
A0 - A14
Address Inputs
Data In/Out
A5
5
A9
DQ0 - DQ7
A4
6
A11
G
A3
7
Chip Enable
E
SOP
A2
8
A10
E
Output Enable
Write Enable
Power Supply Voltage
Ground
G
A1
9
W
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
VCC
VSS
DQ0
DQ1
DQ2
VSS
Top View
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STK Control #ML0043
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Rev 1.1
U631H256
Block Diagram
EEPROM Array
512 x (64 x 8)
VCC
VSS
A5
A6
A7
A8
STORE
RECALL
SRAM
Array
A9
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
Store/
Recall
Control
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
Column I/O
Column Decoder
Software
Detect
A0 - A13
A0 A1 A2 A3 A4A10
G
DQ7
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
High-Z
High-Z
*
*
H
H
H
L
L
Data Outputs Low-Z
Data Inputs High-Z
Write
*
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± ±200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.5
-0.3
-0.3
7
V
V
VCC+0.5
VCC+0.5
1
Output Voltage
VO
PD
V
Power Dissipation
W
Operating Temperature
C-Type
K-Type
0
-40
70
85
°C
°C
Ta
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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U631H256
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
Input Low Voltage
Input High Voltage
VCC
VIL
4.5
-0.3
2.2
5.5
0.8
V
V
V
-2 V at Pulse Width
10 ns permitted
VIH
VCC+0.3
C-Type
K-Type
DC Characteristics
Symbol
Conditions
Unit
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
VCC = 5.5 V
VIL
VIH
= 0.8 V
= 2.2 V
tc
= 25 ns
95
6
100 mA
Average Supply Current during
STOREc
ICC2
VCC = 5.5 V
E
W
VIL
VIH
7
mA
mA
≥ VCC-0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Average Supply Current
at tcR = 200 nsb
(Cycling CMOS Input Levels)
ICC3
VCC = 5.5 V
20
20
W
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1 VCC = 5.5 V
E
≥±VIH
tc
= 25 ns
40
1
42
2
mA
mA
Standby Supply Curentd
ICC(SB) VCC = 5.5 V
(Stable CMOS Input Levels)
E
VIL
VIH
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c:
ICC2 is the average current required for the duration of the STORE cycle (tSTORE).
d: Bringing E±≥±VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
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U631H256
Symbol
Conditions
Min.
Max.
Unit
DC Characteristics
VCC
IOH
IOL
= 4.5 V
=-4 mA
= 8 mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
V
V
0.4
-4
VCC
VOH
VOL
= 4.5 V
= 2.4 V
= 0.4 V
Output High Current
Output Low Current
IOH
IOL
mA
mA
8
Input Leakage Current
VCC
= 5.5 V
High
Low
IIH
IIL
VIH
VIL
= 5.5 V
1
μA
μA
=
0 V
-1
-1
Output Leakage Current
VCC
E or G ≥ VIH
VOH
VOL
= 5.5 V
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
= 5.5 V
1
μA
μA
=
0 V
SRAM Memory Operation
Symbol
Switching Characteristics
No.
Unit
Read Cycle
Alt.
IEC
Min. Max.
1
2
3
4
Read Cycle Timef
tAVAV
tAVQV
tELQV
tcR
25
25
25
ns
ns
ns
Address Access Time to Data Validg
Chip Enable Access Time to Data Valid
ta(A)
ta(E)
Output Enable Access Time to Data
Valid
tGLQV
ta(G)
10
ns
5
6
7
8
9
E HIGH to Output in High-Zh
G HIGH to Output in High-Zh
E LOW to Output in Low-Z
tEHQZ
tGHQZ
tELQX
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
10
ns
ns
ns
ns
ns
ns
ns
10
5
G LOW to Output in Low-Z
tGLQX
0
Output Hold Time after Addr. Changeg
tAXQX
3
10 Chip Enable to Power Activee
tELICCH
tEHICCL
tPU
0
11 Chip Disable to Power Standbyd, e
tPD
25
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both Low.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± ±200 mV from steady state output voltage.
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August 15, 2006
STK Control #ML0043
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U631H256
f
=
=
VIL, W = VIH)
Read Cycle 1: Ai-controlled (during Read cycle: E
G
tcR
(1)
Ai
Address Valid
ta(A)
(2)
Output Data Valid
Previous Data Valid
DQi
Output
tv(A)
(9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR
Address Valid
(1)
Ai
E
ta(A)
ta(E)
(2)
(3)
tdis(E)
(5)
tPD
ten(E)
(11)
(7)
G
ta(G)
(4)
tdis(G)
(6)
ten(G)
(8)
DQi
Output
High Impedance
Output Data Valid
t
PU (10)
ACTIVE
ICC
STANDBY
Symbol
Switching Characteristics
Write Cycle
Unit
No.
Alt. #1
Alt. #2
IEC
Min. Max.
12 Write Cycle Time
13 Write Pulse Width
tAVAV
tAVAV
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
14 Write Pulse Width Setup Time
15 Address Setup Time
tWLEH
tAVEL
tAVEH
tAVWL
tAVWH
tELWH
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
20
20
20
10
0
tELEH
tDVEH
tEHDX
19 Data Setup Time to End of Write tDVWH
tsu(D)
th(D)
20 Data Hold Time after End of
Write
tWHDX
21 Address Hold after End of Write tWHAX
tEHAX
th(A)
0
5
ns
ns
ns
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
tWLQZ
tWHQX
tdis(W)
ten(W)
10
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STK Control #ML0043
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Rev 1.1
U631H256
Write Cycle #1: W-controlledj
tcW
(12)
Ai
Address Valid
(17)
tsu(E)
th(A)
(21)
E
tsu(A-WH)
tw(W)
(16)
(13)
W
tsu(A)
(15)
th(D)
tsu(D)
(20)
(19)
DQi
Input
Input Data Valid
tdis(W)
ten(W)
(22)
(23)
DQi
Output
High Impedance
Previous Data
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
tw(E)
th(A)
(18)
(21)
tsu(A)
(15)
tsu(W)
(14)
tsu(D)
W
th(D)
Input Data Valid
(19)
(20)
DQi
Input
DQi
High Impedance
Output
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
>
j: E or W must be
VIH during address transitions.
Rev 1.1
August 15, 2006
STK Control #ML0043
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U631H256
Nonvolatile Memory Operations
Symbol
STORE Cycle Inhibit and
No.
Min.
Max.
Unit
Automatic Power Up RECALL
Alt.
IEC
24 Power Up RECALL Durationk
Low Voltage Trigger Level
tRESTORE
VSWITCH
650
4.5
μs
4.0
V
k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE Cycle Inhibit and Automatic Power Up RECALL
V
CC
5.0 V
V
SWITCH
t
STORE inhibit
Power Up
RECALL
(24)
t
RESTORE
Software Mode Selection
A13 - A0
(hex)
E
W
Mode
I/O
Power
Notes
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
Nonvolatile STORE
ICC2
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
Nonvolatile RECALL
l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
m: While there are 15 addresses on the U631H256, only the lower 14 are used to control software modes.
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U631H256
Symbol
Alt.
tAVAV
tELQZ
No. Software Controlled STORE/RECALL
Unit
Cyclel, n
IEC
tcR
Min. Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactiveo
27 STORE Cycle Timep
25
600
10
20
0
ns
ns
ms
μs
ns
ns
ns
tdis(E)SR
td(E)S
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
28 RECALL Cycle Timeq
td(E)R
29 Address Setup to Chip Enabler
30 Chip Enable Pulse Widthr, s
31 Chip Disable to Address Changer
tsu(A)SR
tw(E)SR
th(A)SR
20
0
n: The software sequence is clocked with E controlled READs
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
SWITCH once it has been exceeded for the RECALL to function properly.
V
r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cyclet, u (E = HIGH after STORE initiation)
tcR
ADDREESS 1
tcR
(25)
(25)
Ai
E
ADDRESS 6
t
(30)
w(E)SR
tsu(A)SR
(31)
th(A)SR
(29)
td(E)S (27) td(E)R
(28)
High Impedance
DQi
Output
VALID
VALID
tdis(E)SR
(26)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tcR
(25)
Ai
E
ADDRESS 6
tsu(A)SR (29)
ADDRESS 1
th(A)SR
(31)
tw(E)SR
(30)
th(A)SR
(31)
VALID
tsu(A)SR (29)
td(E)R
td(E)S
(27)
(28)
DQi
Output
High Impedance
VALID
tdis(E)SR
(26)
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the U631H256 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
Rev 1.1
August 15, 2006
STK Control #ML0043
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U631H256
Test Configuration for Functional Check
5 V
w
A0
A1
VCC
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
480
VIH
VIL
VO
v
30 pF
E
W
G
255
VSS
v: In measurement of tdis-times and ten-times the capacitance is 5 pF.
w: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Unit
VCC
VI
f
= 5.0 V
= VSS
= 1 MHz
= 25 °C
Input Capacitance
CI
8
pF
Output Capacitance
CO
7
pF
Ta
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
Type
U631H256
S
C
25 G1
Leadfree Option
G1 = Leadfree Green Package
Package
S2 = SOP28 (330mil) Type 2
Access Time
25 = 25 ns
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
Device Marking (example)
ZMD
Product specification
Date of manufacture
U631H256SC
25 Z 0425
G1
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Internal Code
Leadfree Green Package
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U631H256
Device Operation
vious nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE
cycle is initiated, further inputs and outputs are disabled
until the cycle is completed .Because a sequence of
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence or the sequence
The U631H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM shadow (the STORE operation) or from
EEPROM to SRAM (the RECALL operation). In this
mode SRAM functions are disabled.
will be aborted and no STORE or RECALL will take
place.
To initiate the STORE cycle the following READ
sequence must be performed:
SRAM READ
The U631H256 performs a READ cycle whenever E
and G are LOW while W is HIGH. The address speci-
fied on pins A0 - A14 determines which of the 32768
data bytes will be accessed. When the READ is initia-
ted by an address transition, the outputs will be valid
after a delay of tcR. If the READ is initiated by E or G,
the outputs will be valid at ta(E) or at ta(G), whichever is
later. The data outputs will repeatedly respond to
address changes within the tcR access time without the
need for transition on any control input pins, and will
remain valid until another address change or until E or
G is brought HIGH or W is brought LOW.
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0FC0 (hex) Initiate STORE
Cycle
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE
or tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1.
2.
3.
4.
5.
6.
Read addresses 0E38 (hex) Valid READ
Read addresses 31C7 (hex) Valid READ
Read addresses 03E0 (hex) Valid READ
Read addresses 3C1F (hex) Valid READ
Read addresses 303F (hex) Valid READ
Read addresses 0C63 (hex) Initiate RECALL
Cycle
Noise Consideration
The U631H256 is a high speed memory and therefore
must have a high frequency bypass capacitor of appro-
ximately 0.1 μF connected between VCC and VSS using
leads and traces that are as short as possible. As with
all high speed CMOS ICs, normal carefull routing of
power, ground and signals will help prevent noise pro-
blems.
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
Software Nonvolatile STORE
The U631H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U631H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
Automatic Power Up RECALL
On power up, once VCC exceeds the sense voltage of
V
SWITCH, a RECALL cycle is automatically initiated.
The voltage on the VCC pin must not drop below
Rev 1.1
August 15, 2006
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U631H256
Low Average Active Power
RECALL; SRAM operation cannot commence until
RESTORE after VCC exceeds VSWITCH
t
.
The U631H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
If the U631H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and VCC.
The overall average current drawn by the part depends
on the following items:
Hardware Protection
1. CMOS or TTL input levels
The U631H256 offers hardware protection against
inadvertent STORE operation through VCC sense.
For VCC < VSWITCH the software initiated STORE ope-
ration will be inhibited.
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
August 15, 2006
STK Control #ML0043
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U631H256
LIFE SUPPORT POLICY
SIMTEK products are not designed, intended, or authorized for use as components in systems intended for sur-
gical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SIMTEK product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by SIMTEK for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However SIMTEK
Corporation (SIMTEK) makes no guarantee or warranty concerning the accuracy of said information and shall
not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The
information in this document describes the type of component and shall not be considered as assured characte-
ristics.
SIMTEK does not guarantee that the use of any information contained herein will not infringe upon the patent,
trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby.
This document does not in any way extent SIMTEK’s warranty on any product beyond that set forth in its stan-
dard terms and conditions of sale.
SIMTEK reserves terms of delivery and reserves the right to make changes in the products or specifications, or
both, presented in this publication at any time and without notice.
August 15, 2006
Simtek Corporation
4250 Buckingham Drive suite 100±• Colorado Springs, CO 80907 • USA
Phone: +(800)637-1667 • Fax: +(719)531-9481 • Email: information@simtek.com • http://www.simtek.com
Change record
Date/Rev
Name
Change
01.08.2001
Steffen Buschbeck
changed limit for CMOS standby current
Page 3: ICC(SB) = 2 mA for K-Type
01.11.2001
25.09.2002
30.10.2002
04.12.2003
21.04.2004
Ivonne Steffens
format revision and release for “Memory CD 2002“
adding “Type 1“ to SOP28 (330 mil)
Matthias Schniebel
Matthias Schniebel
Matthias Schniebel
Matthias Schniebel
combining U631H256 and U631H256SM in one datasheet
Operating Supply Current at tcR = 200 ns: ICC3 = 20 mA
adding “Leadfree Green Package“ to ordering information
adding “Device Marking“
6
7.4.2005
Stefan Günther
Stefan Günther
changing 10 endurance cycles and 100a dataretention, mil.
temperature range and PDIP28 (300mil) deleted, G1 no more on
special request, add S2 = SOP28 (330mil) Type 2 (chip pack)
12.10.2005
change -55°C to -40°C and M- to A- type in DC characteristics,
absolute ratings, ordering code
31.03.2006
15.08.2006
Simtek
Simtek
Assigned Simtek Document Control Number
Moved Product To End of Life Status
相关型号：
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