IMISG742AYB [CYPRESS]
Clock Generator, PDSO48,;
| 型号： | IMISG742AYB |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, PDSO48, 光电二极管 |
| 文件： | 总10页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
FREQUENCY TABLE (MHz)
PRODUCT FEATURES
S2
S1
S0
CPU
PCI
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
75
25
Supports Pentium , Pentium II, M2 and K6.
Supports 430TX and 440LX chipset requirements.
4 CPU clocks
Up to 12 SDRAM clocks for 3 DIMMs.
7 PCI synchronous clocks.
Optional common or mixed supply mode:
(Vdd = Vddq3 = Vddq2 = 3.3V) or
(Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V)
< 250ps skew among CPU or SDRAM clocks.
< 250ps skew among PCI clocks.
Power Management Capability.
30
83.3
100
55
33.3
33.3
27.5
37.5
30
75
60
.8
33.4
CONNCTION DIAGRAM
IOAPIC clocks for multiprocessor support.
48 MHz for USB support
48-pin SSOP package
Integrates EMI reduction SSCG technology for
upto 15dB attenuation.
DD
REFSEL47
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDI
IOAPIC/REFOFF#
REF1 / CS#
VSS
CPU0
CPU1
VDDC
CPU2
CPU3
VSS
SDR0
SDR1
VDDS
SDR2
SDR3
VSS
SDR4
SDR5
VDDS
SDR6
SDR7
VSS
XIN
XOUT
VDDP
BLOCK DIAGRAM
PCI_F/ S1
PCI0 / S2
VSS
SW/PCI1
TEST/PCI2
PCI3
PCI4
VDDP
PCI5 / PS#
VSS
REF
XIN
R0/Sel47
REF1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
XOUT
IOAP/Ref0ff#
VD
CS# EM
PS#
CPU (0:3)
B
B
4
PCI (0:5)
PCI_F
SDR11
SDR10
VDDS
SDR9
SDR8
Vss
SDEN0
SDEN1
d
6
2
1
PLL1
SDEN0
SDEN1
SDR(0:11)
B
12
48MHz / S0
24 MHz / Mode
S0
MODE
NOTE : Purchase of I2C components of International Microcircuits, Inc. or one of its
sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to
use these components in an I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Phillips.
48 MHz
24 MHz
PLL2
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 1 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
PIN DESCRIPTION
PIN
No.
4
Pin
Name
Xin
PWR
VDD
I/O
I
TYPE
Description
OSC1
On-chip reference oscillator input pin. Requires either an external
crystal (nominally 14.318 MHz) or externally generated reference
signal
5
VDD
O
OSC1
BUF
O-chip reference oscillator output p. Drives an external crystal
When an externally generated reerence signal is used, is left
unconnected
This pin is bidirectional. If pin 5, MOE = 1 (default), then this
pin is a REF1 buffered ouput of e crystal. If in 25, MODE = 0
Xout
46
VDD
-
O
I
REF1
CS#
PADI4 then this pin is CS# anis used in ower mnagement mode for
PU
synchronously stopnall CPU clock(e page 4).
This pin is bidirectional. If s pulled low with a programming
resistor at powrup then pin 7 is configured as an input pin which
will act as a eference enable pfor pin 2 (this pin). If this pin is
high (no ogramming resistor) at power up, then this pin is a
REF1 bfered oput of the crystal.
2
REF0
SEL47
CPU(0:3)
IOAPIC
44, 43, 41, 40
47
VDDC
VDDI
O
O
BUF1
BUF2
Clock outpsCPU freqncy table specified on page 1.
IOAPIC clock r multprocessor support. Fixed frequency at
14.31818 Mhz. is s a bidirectional pin. If Sel47 = 1, becomes
APIC output powered by VDDq2. If Sel47 = 0, becomes input
pin with internpull-up. When Refoff# = 1 (default), then REF0 is
enabld, if efoff# is 0, then REF0 is disabled.
I bus ocks. See frequency select table on page 1.
Loskew (<250pS) PCI clock outputs. This pin is bidirectional.
Ding power-up, It is an input ( TEST) and is used for configure
te output frequency of CPU, SDRAM and PCI clocks into the
TEST mode. When the power reaches the VDD rail (See Fig.1),
the selected data is latched internally to the IC
-
I
O
O
PAD
BUF4
BUF4
REFOFF#
PCICLK(3:4)
PCI2
12, 13
11
VDDP
VDDP
-
AD
O
and this pins become PCI_F clock output.
TEST
PCI_F
7
VDDP
BUF4
BUF4
Low skew (<250pS) PCI clock outputs. This pin is bidirectional.
During power-up, It is an input ( S1) and is used for HARD
selecting the output frequency of CPU, SDRAM and PCI clocks,
see Frequency table page1. When the power reaches the VDD
rail (See Fig.1), the selected data is latched internally to the IC
and this pins become PCI_F clock output.
Low skew (<250pS) PCI clock outputs. This pin is bidirectional.
During power-up, It is an input ( SW) and is used for HARD
selecting the spreading width of the EMI reducing modulation.
When the power reaches the VDD rail (See Fig.1), the data bit is
latched internally in the IC and this pin becomes PCI1 clock
output.
-
I
O
S1
PCI1
10
VP
-
-
I
1
PAD
PAD
SW
sden [0:1]
23,24
SDRAM clock enable pins. When these pins are brought to a
Loigc 0 (low) level, they tri-state the SDRAM buffers they control.
SDEN0 Controls SDRAM 4:7, SDEN1 controls SDRAM 8:11.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 2 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
PIN DESCRIPTION (Cont.)
PIN
No.
8
Pin
Name
PCI0
PWR
VDDP
I/O
TYPE
Description
O
BUF4
Low skew (<250pS) PCI clock outputs. This pin is bidirectional.
During power-up, it is an input ( S2) and is used for HARD
selecting the output frequency of CPU, SDRAM and PCI clocks,
see Frequency table page 1. When the power reaches the VDD
rail (See Fig.1), the selected data is latched internally to the IC
and this pin become PCI0 clock outpu
-
I
PAD
S2
15
VDD
0
BUF4
Low skew (<250pS) PCICLK outputIf mode is set to a 1 logic
(high state). If mode is set to a loic 0 (low tate), this pin acts as
a PCI_STOP control for power magement. As such, it will
disable all PCI clocks when brough 0 logic (lw state) level.
Synchronous DRAM clo, SDRAM cck freuency = CPU clock
frequency.
PCI5
I
I
PAD
PAD
PS#
17, 18, 20,
21,
VDDS
-
SDR[0:11]
28,29,31,32,
34,35,37,38
3, 9, 16, 22,
27, 33, 39, 45
6, 14
P
-
Ground pins fr the device.
VSS
-
-
-
P
P
P
-
-
3.3 Volt poer suply pin for PCI and PCI_F clock output buffers.
3.3 or 2.5 V por supply fCPU and IOAPIC clock buffers.
Power supply pinfor anlog circuits and core logic
VDDP
VDDC
VDD
42, 48
1
25
Ts is a bidirectionain. During power-up, this pin is an input and
is ud for enabling (0) or disabling (1, default) the power
managment pin15 and 46. When power reaches the VDD rail
(Se Fig.pe3), the selected data is latched internally to the
devie this pin becomes a 24 Mhz output clock.
24 Mhz
MODE
26
Low ew (<250pS) PCI clock outputs. This pin is bidirectional.
Durinpower-up, It is an input ( S0) and is used for HARD
seleting the output frequency of CPU, SDRAM and PCI clocks,
ee Frequency table page1. When the power reaches the VDD
rail (See Fig.1), the selected data is latched internally to the IC
and this pins become 48 MHz clock output.
48 Mhz
S0
19, 36, 30
-
P
Power for SDRAM buffers.
VDDS
A bypass capacitor (0.1µF) should be placed as close as
possible to each Vdd, Vddq2, and Vddq3 pin. If these
bypass capacitors are not close to the pins their high
frequency filtering characteristic will be cancelled by the
lead inductances of the traces.
SDen1
Sden0
SDRAM(7
SDAM(8:11)
0
0
1
1
0
1
0
1
OF
OFF
ON
OF
ON
OFF
ON
ON
VDD
Power Supply
Fig.1
PCI_F / S1, PCI0 / S2,
48 MHz / S0,24 MHz / MODE,
PCI1 / FTS, REF0/Sel47
toggle , outputs
Hi-Z (tristate), inputs
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 3 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
POWER MANAGEMENT FUNCTIONS
When MODE=0, pins 15 and 46 are inputs PS# (PCI_STOP#), and CS# (CPU_STOP#), respectively (when MODE=1,
these functions are not available). The IMISG742 clocks may be disabled according to the following table in order to
reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions
from running to stopped. The CPU/AGP and PCI clocks transition between running and stopped by waiting for one
positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are
either enabled or disabled.
CPU_STOP#
PCI_STOP#
CPU
PCI
OTHR CLK
XTAL & VCOs
0
0
1
1
0
1
0
1
LOW
LOW
RUNNG
RUNNIN
UNNING
RUNING
RUNNING
RUNNING
RUNNING
RUNNING
See Frequency Table
LOW
See Frequency Table
See Frequency Table
LOW
See Frequency Table
All clocks are stopped in the low state.
POWER MANAGEMENT TIMING
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
Fig. 2
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 4 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
SPECTRUM SPREAD CLOCKING
Center Spread
Amplitude
Fcenter
(dB)
Fmin
Fmax
With Spectrum Spread
Without Spectrum Spread
Frquency(Mz)
Center
Spectrum Analysis
SPECTRUM SPREADING SELECION ABLE (CONT)
Unspread
CPU
Center Spreding
frequency
in MHz
SWI=0
SW=1 (default)
Unspread
(MHz)
F Min
(MHz)
F Center F M
Sread Unspread
F Min
(MHz)
F Center
(MHz)
F Max
(MHz)
Spread
(total
%)
desired
(MHz)
(MHz)
(toal %)
(MHz)
50
75
83.3
100
55
75
60
66.8
50.11
74.99
83.18
100.22
55.23
74.99
59.99
66.82
49.97
5.1
83.1
99.94
5.21
712
60.10
66.74
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
50.11
74.99
83.18
100.22
55.23
74.99
59.99
66.82
49.97
75.13
83.51
99.94
55.21
75.12
60.10
66.74
1
1
1
1
1
1
1
1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 5 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
MAXIMUM RATINGS
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
field; however, precautions shuld be taken to avoid
application of any voltage hgher than the maximum
rated voltages to this circt. For poper operation, Vin
and Vout should be constraeto the rage:
VS<(Vin or Vut)<VDD
0ºC to + 125ºC
0ºC to +70ºC
5V
Unused inputs musalways be tid to an appropriate
logic voltage level (eiter VSS or VDD).
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Min
Typ
Max
0.8
Unit
Conditions
Input Low Voltage
VIL
VIH
IIL
-
-
-
Vdc
Vdc
µA
-
-
Input High Voltage
2.0
-
Input Low Current
-66
5
Input High Current
IIH
Ioz
Idd
µA
Tri-State leakage Current
Dynamic Supply Current
-
-
10
116
µA
mA
CPU = 66.6 MHz, PCI = 33.3 Mhz
Unloaded
Static Supply Current
Short Circuit Current
Isdd
ISC
-
-
-
13
-
µA
-
mA
1 output at a time - 30 seconds
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5 + 5%, TA = 0ºC to +70ºC
SWTCHING CHARACTERISTICS
Characteristic
ymbo
Min
Typ
Max
Units
Conditions
Measured at 1.5V
Output Duty Cycle
-
45
1
50
-
55
4
%
ns
ps
CPU/SDRAM to PCI ffset
tOFF
15 pf Load Measured at 1.5V
15 pf Load Measured at 1.5V
Skew (CPU-CPU),
(SDRAM-SDRAM)
tSKEW1
-
-
250
Skew (CPU-SDRAM), (PCI-
PCI)
tSKEW2
-
-
-
-
500
ps
15 pf Load Measured at 1.5V
-
+250
500
ps
∆Period Adjacent Cycles
∆P
Jitter Spectrum 20 dB
Bandwidth from Center
BWJ
KHz
Overshoot/Undershoot
Beyond Power Rails
Vover
-
-
1.5
V
22 ohms @ source of 8 inch PCB run
to 15 pf load
VDD = VDDQ3 =3.3V ±5%, VDDQ2 =2.5 + 5%, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 6 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
TYPE 1 BUFFER CHARACTERISTICS FOR CPU (0:3)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TRFmin
-27
-
-
-
-
-
-
-
mA
mA
mA
mA
nS
Vout 1.0 V
Vut = 2.6 V
Vot = 12 V
Vout = 0.3 V
10 pF Load
-27
-27
-
-
27
-
Rise/Fall Time Min
0.4
Between 0.4 V and 2.0 V
Rise/Fall Time Max
TRFmax
-
-
1.6
nS
20 pF Load
Between 0.4 V and 2.0 V
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5 + 5%, TA = 0ºto +70ºC
TYPE 2 BUFFER CHARACTERISTIS FOR IOAPIC, REF1
Characteristic
Symbol
Min
Tp
Max
Uits
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TRFmi
-28
-
-
-
-
-
-
-
mA
mA
mA
mA
nS
Vout = 1.4 V
Vout = 2.7 V
Vout = 1.0 V
Vout = 0.2 V
10 pF Load
-29
-28
-
-
28
-
Rise/Fall Time Min
0.4
Between 0.4 V and 2.0 V
Rise/Fall Time Max
RFmx
-
-
1.6
nS
20 pF Load
Between 0.4 V and 2.0 V
VDD VDD3 3.3V ±5%, VDDQ2 = 2.5 + 5%, TA = 0ºC to +70ºC
TYPE 4 BUFFER CHARACTERISTICS FOR REF0 and SDRAM(0:11)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TRFmin
-46
-
-
-
-
-
-
-
mA
mA
mA
mA
nS
Vout = 1.65 V
Vout = 3.135 V
Vout = 1.65 V
Vout = 0.4 V
20 pF Load
-46
-46
-
-
53
-
Rise/Fall Time Min
0.5
Between 0.4 V and 2.4 V
Rise/Fall Time Max
TRFmax
-
-
1.3
nS
30 pF Load
Between 0.4 V and 2.4 V
VDD = VDDQ3 =3.3V ±5%, VDDQ2 = 2.5 + 5%, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 7 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
TYPE 5 BUFFER CHARACTERISTICS FOR PCI_F AND PCI(0:5)
Characteristic
Symbol
Min
Typ
Max
Units
Condition
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TRFmin
-33
-
-
-
-
-
-
-
mA
mA
mA
mA
n
Vo= 1.0 V
Vt = 3.135 V
Vout = 1.95 V
Vout = 0.4 V
15 pF Load
-33
30
-
-
38
-
Rise/Fall Time Min
0.5
Between 0.4 V and 2.4 V
Rise/Fall Time Max
TRFmax
-
-
2
S
30 pF Load
Between 0.4 V and 2.4 V
VDD = VDDQ3 =3.3V ±5%, VDDQ2 2.5 + 5%, TA ºC to +70ºC
TYPE 6 BUFFER CHARACTERISTICS FOR 24 MHZ AND 48 MHZ
Characteristic
Symbol
Min
Tp
Max
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLm
TRFmin
-
-
-
-
-
-
-
mA
mA
mA
mA
nS
Vout = 1.0 V
Vout = 3.135 V
Vout = 1.95 V
Vout = 0.4 V
15 pF Load
-46
-
-
53
-
-
Rise/Fall Time Min
0.5
Between 0.4 V and 2.4 V
Rise/Fall Time Max
TRmax
-
-
2
nS
50 pF Load
Between 0.4 V and 24 V
VDD = DDQ3 =3.3V ±5%, VDDQ2 = 2.5 + 5%, TA = 0ºC to +70ºC
Application Note for Selection on Bidirectional Pins
Pins 2, 7, 8, 10, 25, and 26 are bidirectional pins and are used for selecting different functions in this device (see Pin description,
Pages 2&3). During power-up of the SG742, these pins are in input mode (see Fig1, page3), therefore, they are considered input
select pins. Internal to the IC, these pins have a large value pull-up each (100KΩ), therefore, a selection “1” is the default. If a
selection “0” is desired, then a direct connection to ground through a 10KΩ resistor should be implemented as shown in Fig.3.
Please note the selection resistor (10KΩ) is placed before the Damping resistor (Rd) close to the pin.
IMISG742
Rd
Pins 2, 7, 8, 10, 15, 25, and 26
To load
10KΩ
Fig. 3
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 8 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
PCB LAYOUT SUGGESTION
IMISG742
Via to VDD Island
VCC1
Via to GND plane
FB1
Via to VCC plane
C3
1
2
3
4
48
47
46
45
44
43
C35
C36
C34
22µF
5
6
7
8
9
FB2
VCC2
42
41
C4
40
39
38
10
11
C5
22µF
12
13
14
15
16
37
36
35
3
33
2
C40
C37
C38
17
18
3
30
C39
19
20
21
2
3
24
29
8
27
26
25
VCC1
FB3
C41
22µF
This is only a layout recommendation for best performance and lower EMI. The designer may choose a different approach
but C3, C4, C35, C36, C37, C38, C39and C40 (all are 0.1µf) should always be used and placed as close as possible to
their VDD pins.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
Page 9 of 10
SG742
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs
Preliminary
PACKAGE DRAWING AND DIMENSIONS
48 PIN SSOP OUTLINE DIMENSIONS
INCHES
NOM
MILLIMETERS
C
SYMBOL
MIN
MX
MIN
NOM
MAX
L
A
A1
A2
b
-
-
0.110
0.01
095
0.01
0.010
0.637
0.299
0
0
2.79
0.41
2.41
0.33
0.25
0.008
0.085
0.008
0.06
0.012
.090
0.010
008
0.625
0.295
0.025 BSC
008
0.030
5º
0.20
2.1
.20
0.15
-
0.30
2.29
0.25
0.20
H
E
C
D
E
15.88 16.18
D
a
0.291
7.39
7.49
7.59
e
0.64 BSC
A2
A
H
L
.395
0.025
0º
0.420
0.040
8º
10.03 10.36 10.67
0.64
0º
0.76
5º
1.02
8º
A1
a
e
B
ORDERING INFORMATION
Part Number
Package Type
Production Flow
Commercial, 0ºC to +70ºC
IMISG742AYB
48 PIN SSOP
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown blow.
Marking:
Example:
IMI
SG742AY
Date Code, L#
IMISG742AY
Flow
B = Commercial, 0ºC to + 70ºC
Package
Y = SSOP
Revision
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.3
1/12/98
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