GVT71256E18B-9 [CYPRESS]
Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119;
| 型号： | GVT71256E18B-9 |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 静态存储器 |
| 文件： | 总16页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
325A
CY7C1325A/GVT71256E18
256K x 18 Synchronous Flow-Through Burst SRAM
The
CY7C1325A/GVT71256E18
SRAM
integrates
Features
262,144x18 SRAM cells with advanced synchronous periph-
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), and Global Write (GW).
• Fast access times: 7.5 and 8 ns
• Fast clock speed: 117 and 100 MHz
• Provide high-performance 2-1-1-1 access rate
• Fast OE access times: 4.0 ns
• 3.3V –5% and +10% power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE), and Sleep Mode Control (ZZ).
The data outputs (DQ), enabled by OE, are also asynchro-
nous.
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
• Three chip enables for depth expansion and address
pipeline
• Address, data and control registers
• Internally self-timed Write Cycle
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written.
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The CY7C1325A/GVT71256E18 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PC™ systems and for systems that benefit from a wide syn-
chronous data bus.
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
Selection Guide
7C1325A-117
71256E18-7
7C1325A-100
71256E18-8
7C1325A-100
71256E18-9
7C1325A-100
71256E18-10
Maximum Access Time (ns)
7.5
370
10
8
8
8
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
320
10
320
10
320
10
Cypress Semiconductor Corporation
Document #: 38-05118 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised November 12, 2002
CY7C1325A/GVT71256E18
256K x 18 (CY7C1325A/GVT71256E18) Functional Block Diagram[1]
UPPER BYTE
WRITE
WEH#
BWE#
D
Q
CLK
LOWER BYTE
WRITE
WEL#
GW#
D
Q
ENABLE
CE#
CE2
D
Q
CE2#
Power Down Logic
ZZ
OE#
ADSP#
Input
Register
A17-A2
Address
Register
ADSC#
DQ1-DQ16
DQP1
CLR
DQP2
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05118 Rev. *A
Page 2 of 16
CY7C1325A/GVT71256E18
Pin Configurations
100-Pin TQFP
Top View
NC
NC
NC
VCCQ
VSSQ
NC
A10
NC
NC
VCCQ
VSSQ
NC
DQP1
DQ8
DQ7
VSSQ
VCCQ
DQ6
DQ5
VSS
NC
VCC
ZZ
DQ4
DQ3
VCCQ
VSSQ
DQ2
DQ1
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ9
DQ10
VSSQ
VCCQ
DQ11
DQ12
NC
VCC
NC
VSS
DQ13
DQ14
VCCQ
VSSQ
DQ15
DQ16
DQP2
NC
VSSQ
VCCQ
NC
NC
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1325A
(256K X 18)
NC
VSSQ
VCCQ
NC
NC
NC
Document #: 38-05118 Rev. *A
Page 3 of 16
CY7C1325A/GVT71256E18
Pin Configurations (continued)
119-Ball Bump BGA
256Kx18—CY7C1325A/GVT71256E18
Top View
1
2
3
A4
4
ADSP
ADSC
VCC
NC
5
6
A16
CE2
A15
DQ”P1
NC
7
A
B
C
D
E
F
VCCQ
A6
A8
VCCQ
NC
NC
NC
CE2
A7
A3
A9
A2
A12
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ9
NC
NC
VSS
VSS
VSS
BWH
VSS
NC
NC
DQ10
NC
CE
DQ8
VCCQ
DQ6
NC
VCCQ
NC
OE
DQ7
NC
G
H
J
DQ11
NC
ADV
GW
VCC
CLK
NC
DQ12
VCCQ
NC
DQ5
VCC
NC
VCC
DQ13
NC
VCCQ
DQ4
NC
K
L
VSS
VSS
VSS
VSS
VSS
MODE
A11
NC
VSS
BWL
VSS
VSS
VSS
NC
DQ14
VCCQ
DQ18
NC
DQ3
NC
M
N
P
R
T
DQ15
NC
BWE
A1
VCCQ
NC
DQ2
NC
DQP2
A5
A0
DQ1
NC
NC
VCC
NC
A13
A17
NC
NC
A10
NC
A14
NC
ZZ
U
VCCQ
NC
VCCQ
Pin Descriptions
Pin
Name
BGA Pins
QFP Pins
Type
Input-
Description
Addresses: These inputs are registered and must meet the set-up
4P, 4N, 2A, 3A, 37, 36, 35, 34, A0–A17
5A, 6A, 3B, 5B, 33, 32, 100, 99,
2C, 3C, 5C, 6C, 82, 81, 80, 48,
2R, 6R, 2T, 3T, 47, 46, 45, 44,
Synchronous and hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
5T, 6T
49, 50
5L, 3G
93, 94
WEL,
Input-
Byte Write Enables: A byte write enable is LOW for a Write cycle
WEH Synchronous and HIGH for a Read cycle. WEL controls DQ1–DQ8 and DQP1.
WEH controls DQ9–DQ16 and DQP2. Data I/O are high-imped-
ance if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
4K
87
88
89
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge of
CLK.
GW
Input-
Global Write: This active LOW input allows a full 18-bit Write to
Synchronous occur independent of the BWE and WEn lines and must meet the
set-up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers theaddresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet set-up and hold times around the clock’s rising
edge.
Document #: 38-05118 Rev. *A
Page 4 of 16
CY7C1325A/GVT71256E18
Pin Descriptions (continued)
Pin
Name
BGA Pins
QFP Pins
Type
Description
4E
98
CE
CE2
CE2
OE
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
6B
2B
4F
4G
92
97
86
83
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device.
input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle (no
address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with CE
Synchronous being LOW, causes a new external address to be registered and a
Read cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device to
Synchronous be deselected or selected along with new external address to be
registered. A Read or Write cycle is initiated depending upon write
control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin
selects Linear Burst. A NC or HIGH on this pin selects Interleaved
Burst.
Input-
Snooze: This active HIGH input puts the device in low power con-
Asynchro- sumption standby mode. For normal operation, this input has to be
nous
either LOW or NC (No Connect).
7P, 6N, 6L, 7K, 58, 59, 62, 63,
6H, 7G, 6F, 7E, 68,69,72,73,8, DQ16
1D, 2E, 2G, 1H, 9, 12, 13, 18, 19,
DQ1-
Input/
Output
Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9-
DQ16. Input data must meet setup and hold times around the rising
edge of CLK.
2K, 1L, 2M, 1N
6D, 2P
22, 23
74, 24
DQP1,
DQP2
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2
is parity bit for DQ9-DQ16.
4C, 2J, 4J, 6J,
4R
15, 41,65, 91
VCC
Supply
Power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 17, 40, 67, 90
3F, 5F, 5G, 3H,
VSS
Ground
Ground: GND
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
1A, 7A, 1F, 7F, 4, 11, 20, 27, 54, VCCQ
I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC
)
1J, 7J, 1M, 7M,
1U, 7U
61, 70, 77
5, 10, 21, 26, 55, VSSQ
60, 71, 76
I/O Ground Output Buffer Ground: GND
1B, 7B, 1C, 7C, 1–3,6,7,14,16,
2D, 4D, 7D, 1E, 25, 28-30, 38,
6E, 2F, 1G, 6G, 39, 42, 43, 51-
2H, 7H, 3J, 5J, 53, 56, 57, 66,
1K, 6K, 2L, 4L, 75, 78, 79, 80,
NC
-
No Connect: These signals are not internally connected.
7L, 6M, 2N, 7N,
1P, 6P, 1R, 5R,
7R, 1T, 4T, 2U,
3U, 4U, 5U, 6U
95, 96
Document #: 38-05118 Rev. *A
Page 5 of 16
CY7C1325A/GVT71256E18
Burst Address Table (MODE = NC/V
)
Burst Address Table (MODE = GND)
CC
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
CE
H
L
CE2 CE2 ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
None
None
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
L-H
Q
READ Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
L-H
L-H
D
D
H
X
L
X
WRITE Cycle, Suspend Burst
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH.
3. WEL enables write to DQ1–DQ8 and DQP1. WEH enables write to DQ9–DQ16 and DQP2.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification
Document #: 38-05118 Rev. *A
Page 6 of 16
CY7C1325A/GVT71256E18
Maximum Ratings
Partial Truth Table for Read/Write
(Above which the useful life may be impaired. For user guide-
lines only, not tested.)
FUNCTION
READ
GW
H
BWE
WEH
WEL
X
H
L
L
L
X
X
H
L
Voltage on VCC Supply Relative to VSS..........–0.5V to +4.6V
VIN ......................................................... –0.5V to +VCC+0.5V
Storage Temperature (plastic) .................... –55°C to +125°C
Junction Temperature ............................................... +125°C
Power Dissipation.......................................................... 1.4W
READ
H
H
WRITE one byte
WRITE all bytes
WRITE all bytes
H
H
H
L
L
L
X
X
Short Circuit Output Current ..................................... 100 mA
.
Operating Range
Range
Ambient Temperature[9]
VCC
Com’l
0°C to +70°C
3.3V –5%/+10%
Electrical Characteristics Over the Operating Range[10]
Parameter
VIHD
VIH
Description
Test Conditions
Min.
1.7
1.7
–0.3
–2
Max.
Unit
Input High (Logic 1) Voltage[11, 12] Data Inputs (DQxx)
VCC+0.3
All other
4.6
0.7
2
V
V
VIl
Input Low (Logic 0) Voltage[11, 12]
ILI
Input Leakage Current[13]
Output Leakage Current
Output High Voltage[11, 14]
Output Low Voltage[11, 14]
Supply Voltage[11]
0V < VIN < VCC
µA
µA
V
ILO
Output(s) disabled, 0V < VOUT < VCC
IOH = –2.0 mA
–2
2
VOH
VOL
1.7
IOL = 2.0 mA
0.7
3.6
V
VCC
3.135
2.375
V
VCCQ
I/O Supply
VCC
V
Parame-
ter
-7
-8
-9
-1
Description
Conditions
Typ. 117 MHz 100 MHz 90 MHz 50 MHz Unit
ICC
Power Supply
Current:
Device selected;
150
370
320
290
200
mA
all inputs < VILor > VIH;
Operating[15, 16, 17] cycle time > tKC Min.; VCC = Max.;
outputs open
ISB2
CMOS
Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or
> VCC – 0.2;
5
10
10
10
10
mA
Standby[16, 17]
all inputs static; CLK frequency = 0
ISB3
TTL Standby[16, 17] Device deselected; all inputs < VIL
or > VIH; all inputs static;
10
40
20
80
20
70
20
60
20
40
mA
mA
VCC = Max.; CLK frequency = 0
ISB4
Clock
Device deselected;
all inputs < VIL or > VIH;
VCC = Max.;
Running[16, 17]
CLK cycle time > tKC Min.
Notes:
9.
TA is the case temperature.
10. Values in table are associated with the operating frequencies listed.
11. All voltages referenced to VSS (GND).
12. Overshoot: VIH < +6.0V for t < tKC /2.
Undershoot: VIL < –2.0V for t < tKC /2.
13. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA.
14. AC I/O curves are available upon request.
15.
ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
16. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
17. Typical values are measured at 3.3V, 25°C and 20-ns cycle time.
Document #: 38-05118 Rev. *A
Page 7 of 16
CY7C1325A/GVT71256E18
Thermal Consideration
Parameter
Description
Conditions
TQFP Typ.
Unit
°C/W
°C/W
ΘJA
ΘJC
Thermal Resistance - Junction to Ambient
Thermal Resistance - Junction to Case
Still air, soldered on 4.25 x 1.125
inch 4-layer PCB
25
9
Capacitance
Parameter
Description
Input Capacitance[18]
Input/Output Capacitance (DQ)[18]
Test Conditions
Typ.
4
Max.
Unit
CI
TA = 25°C, f = 1 MHz,
VCC= 3.3V
5
8
pF
pF
CO
7
Typical Output Buffer Characteristics
Output High Voltage
Pull-up Current
Output Low Voltage
Pull-down Current
VOH (V)
–0.5
0
I
OH (mA) Min.
IOH (mA) Max.
VOL (V)
–0.5
0
IOL (mA) Min.
I
ΟL (mA) Max.
–38
–38
–38
–26
–20
0
–105
–105
–105
–83
–70
–30
–10
0
0
0
0
0
0.8
0.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
1.25
1.5
0.8
1.25
1.6
2.3
2.7
0
2.8
2.9
0
3.2
3.4
0
0
3.4
AC Test Loads and Waveforms
DQ
ALL INPUT PULSES
90%
2.5V
0V
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
V = 1.25V
t
Rise Time:
1 V/ns
Fall Time:
1 V/ns
Note:
18. This parameter is sampled.
Document #: 38-05118 Rev. *A
Page 8 of 16
CY7C1325A/GVT71256E18
Switching Characteristics Over the Operating Range[19]
-7
-8
-9
-10
100 MHz
117 MHz
100 MHz
100 MHz
Parameter
Clock
tKC
Description
Min. Max. Min. Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
8.5
3
10
4
11
4.5
4.5
20
4.5
4.5
ns
ns
ns
tKH
Clock HIGH Time
Clock LOW Time
tKL
3
4
Output Times
tKQ
Clock to Output Valid
7.5
8
8.5
10
ns
ns
ns
ns
ns
ns
ns
tKQX
Clock to Output Invalid
2
0
2
2
0
2
2
0
2
2
0
2
tKQLZ
Clock to Output in Low-Z[18, 20, 21]
Clock to Output in High-Z[18, 20, 21]
OE to Output Valid[22]
tKQHZ
3.5
4.0
3.5
4.0
3.5
4.0
3.5
4.0
tOEQ
tOELZ
OE to Output in Low-Z[18, 20, 21]
OE to Output in High-Z[18, 20, 21]
0
0
0
0
tOEHZ
3.5
3.5
3.5
3.5
Set-Up Times
tS
Address, Controls and Data In[23]
Address, Controls and Data In[23]
1.5
0.5
2.0
0.5
2.0
0.5
2.0
0.5
ns
ns
Hold Times
tH
Notes:
19. Test conditions as specified with the output loading as shown in AC Test Loads unless otherwise noted. Values in table are associated with the operating
frequencies listed.
20. Output loading is specified with CL=5 pF as in AC Test Loads.
21. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
.
22. OE is a “Don’t Care” when a byte write enable is sampled LOW.
23. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table.
Document #: 38-05118 Rev. *A
Page 9 of 16
CY7C1325A/GVT71256E18
Timing Diagrams
Read Timing[24]
t
KC
t
KL
CLK
ADSP#
t
t
S
KH
t
H
ADSC#
t
S
ADDRESS
A1
A2
t
H
WEH#, WEL#,
BWE#, GW#
CE#
(See Note)
t
S
ADV#
OE#
DQ
t
H
t
t
t
KQ
KQ
OEQ
t
t
KQLZ
OELZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A2+2)
SINGLE READ
BURST READ
Note:
24. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active.
Document #: 38-05118 Rev. *A
Page 10 of 16
CY7C1325A/GVT71256E18
Timing Diagrams (continued)
Write Timing[24]
CLK
t
S
ADSP#
ADSC#
t
H
t
S
ADDRESS
A1
A2
A3
t
H
WEH#, WEL#,
BWE#
GW#
CE#
(See Note)
t
S
ADV#
OE#
DQ
t
H
t
OEHZ
t
KQX
Q
D(A1)
D(A2)
D(A2+2)
D(A2+2)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05118 Rev. *A
Page 11 of 16
CY7C1325A/GVT71256E18
Timing Diagrams (continued)
Read/Write Timing[24]
CLK
t
S
ADSP#
ADSC#
t
H
t
S
ADDRESS
A2
A3
A4
A5
A1
t
H
WEH#, WEL#,
BWE#, GW#
CE#
(See Note)
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single Reads
Single Write
Burst Read
Burst Write
Document #: 38-05118 Rev. *A
Page 12 of 16
CY7C1325A/GVT71256E18
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
117
CY7C1325A-117AC
GVT71256E18T-7
CY7C1325A-117BGC
GVT71256E18B-7
CY7C1325A-100AC
GVT71256E18T-8
CY7C1325A-100BGC
GVT71256E18B-8
CY7C1325A-100AC
GVT71256E18T-9
CY7C1325A-100BGC
GVT71256E18B-9
CY7C1325A-100AC
GVT71256E18T-10
CY7C1325A-100BGC
GVT71256E18B-10
A101
BG119
A101
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
Commercial
100
100
100
Commercial
Commercial
Commercial
BG119
A101
BG119
A101
BG119
Document #: 38-05118 Rev. *A
Page 13 of 16
CY7C1325A/GVT71256E18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05118 Rev. *A
Page 14 of 16
CY7C1325A/GVT71256E18
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05118 Rev. *A
Page 15 of 16
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1325A/GVT71256E18
Document History Page
Document Title: CY7C1325A/GVT71256E18 256K x 18 Synchronous Flow-Through Burst SRAM
Document Number: 38-05118
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
108298
121068
Description of Change
New Cypress spec--converted from Galvantech format
Updated package drawing 51-85115 (BG119) to rev. *B
09/25/01
11/13/02
BRI
*A
DSG
Document #: 38-05118 Rev. *A
Page 16 of 16
相关型号：
GVT71256E18T-7
Standard SRAM, 256KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256F18T-3
Cache SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256F18T-4
Cache SRAM, 256KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256F18T-6
Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256G18B-6
Standard SRAM, 256KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
GVT71256G18T-5
Standard SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256T18T-7.5
Cache Tag SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
©2020 ICPDF网 联系我们和版权申明