GVT71256T18T-75 [CYPRESS]
256K x 18 Synchronous-Pipelined Cache Tag RAM; 256K ×18的同步流水线高速缓存RAM标签
| 型号： | GVT71256T18T-75 |
| 厂家： | 
CYPRESS |
| 描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 文件： | 总24页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
327
CY7C1359A/GVT71256T18
256K x 18 Synchronous-Pipelined Cache Tag RAM
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
Features
• Fast match times: 3.5, 3.8, 4.0 and 4.5 ns
• Fast clock speed: 166, 150, 133, and 100 MHz
• Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns
• Pipelined data comparator
• Data input register load control by DEN
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% core power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• JTAG boundary scan
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), Global Write (GW), and Data
Input Enable (DEN).
Asynchronous inputs include the Burst Mode Control (MODE),
the Output Enable (OE) and the Match Output Enable (MOE).
The data outputs (Q) and Match Output (MATCH), enabled by
OE and MOE respectively, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Data inputs are registered with Data Input Enable (DEN) and
chip enable pins (CE, CE2, and CE2). The outputs of the data
input registers are compared with data in the memory array
and a match signal is generated. The match output is gated
into a pipeline register and released to the match output pin at
the next rising edge of Clock (CLK).
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to two bytes wide as controlled by the write control inputs. In-
dividual byte write allows individual byte to be written. WEL
controls DQ1–DQ9. WEH controls DQ10–DQ18. WEL and
WEH can be active only with BWE being LOW. GW being LOW
causes all bytes to be written.
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low-profile JEDEC standard 100-pin TQFP package
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The CY7C1359C/GVT71256T18 operates from a +3.3V pow-
er supply with output power supply being +2.5V or +3.3V. All
inputs and outputs are LVTTL compatible. The device is ideally
suited for address tag RAM for up to 8 MB secondary cache.
Selection Guide
7C1359A-166
71256T36-6
7C1359A-150
71256T36-6.7
7C1359A-133
71256T36-7.5
7C1359A-100
71256T36-10
Maximum Access Time (ns)
3.5
310
20
3.8
275
20
4.0
250
20
4.5
190
20
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05120 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised September 13, 2001
CY7C1359A/GVT71256T18
Functional Block Diagram—256Kx18[1]
HIGHER BYTE
WRITE
WEH#
BWE#
D
Q
D
Q
LOWER BYTE
WRITE
WEL#
GW#
D
Q
ENABLE
CE#
CE2
D
Q
D
Q
Latch
CE2#
ZZ
Power Down Logic
OE#
MATCH
D
Q
ADSP#
MOE#
Compare
Input
Register
DEN#
Latch
CLK
16
A
Address
Register
OUTPUT
REGISTER
ADSC#
DQ1-
DQ18
D
Q
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05120 Rev. **
Page 2 of 24
CY7C1359A/GVT71256T18
Pin Configurations
100-Pin TQFP
Top View
NC
NC
NC
VCCQ
VSSQ
NC
A
NC
NC
VCCQ
VSSQ
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ9
DQ8
DQ7
VSSQ
VCCQ
DQ6
DQ5
VSS
NC
VCC
ZZ
DQ4
DQ3
VCCQ
VSSQ
DQ2
DQ1
NC
DQ10
DQ11
VSSQ
VCCQ
DQ12
DQ13
NC
VCC
NC
VSS
DQ14
DQ15
VCCQ
VSSQ
DQ16
DQ17
DQ18
NC
VSSQ
VCCQ
NC
NC
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1359A/GVT71256T18
NC
VSSQ
VCCQ
MATCH
DEN
MOE
119-Lead BGA
Top View
1
2
A
3
A
4
ADSP
ADSC
VCC
NC
5
A
6
7
A
VCCQ
NC
A
VCCQ
NC
B
C
D
E
F
CE2
A
A
A
CE2
NC
A
A
A
DQ9
NC
NC
DQ10
NC
NC
VSS
VSS
VSS
WEH
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
WEL
VSS
VSS
VSS
NC
A
NC
DQ11
NC
CE
DQ8
VCCQ
DQ6
NC
VCCQ
NC
OE
DQ7
NC
G
H
J
DQ12
NC
ADV
GW
VCC
CLK
NC
DQ13
VCCQ
NC
DQ5
VCC
NC
VCC
DQ14
NC
VCCQ
DQ4
NC
K
L
DQ15
VCCQ
DQ17
NC
DQ3
MATCH
DQ2
MOE
A
M
N
P
R
T
DQ16
NC
BWE
A1
VCCQ
DEN
DQ1
NC
DQ18
A
A0
NC
VCC
NC
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05120 Rev. **
Page 3 of 24
CY7C1359A/GVT71256T18
Pin Descriptions
BGA Pins
TQFP Pins
Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the
Synchronous set-up and hold times around the rising edge of CLK. The
burst counter generates internal addresses associated with
A0 and A1, during burst cycle and wait cycle.
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
35, 34, 33, 32,
100, 99, 82, 81,
5C, 6C, 2R, 6R, 80,48, 47, 46, 45,
2T, 3T, 5T, 6T
44, 49, 50
5L
3G
93
94
WEL
WEH
Input-
Byte Write Enables: A byte write enable is LOW for a WRITE
Synchronous cycle and HIGH for a READ cycle. WEL controls DQ1–DQ9.
WEH controls DQ10–DQ18. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
87
88
BWE
GW
Input-
Write Enable: This active LOW input gates byte write opera-
Synchronous tions and must meet the set-up and hold times around the
rising edge of CLK.
Input-
Global Write: This active LOW input allows a full 18-bit
Synchronous WRITE to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising edge
of CLK.
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip en-
Synchronous ables, write control, and data input enable control input on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
4E
6B
2B
4F
4G
98
92
97
86
83
CE
CE2
CE2
OE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
Input-
Synchronous device.
Chip Enable: This active LOW input is used to enable the
input-
Chip Enable: This active HIGH input is used to enable the
Synchronous device.
Input
Output Enable: This activeLOW asynchronousinput enables
the data output drivers.
ADV
Input-
Address Advance: This active LOW input is used to control
Synchronous the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes de-
Synchronous vice to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated
depending upon write control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
Input-
Snooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
7N
6M
52
53
DEN
Input-
Data Input Enable: This active LOW input is used to control
Synchronous the update of data input registers.
MATCH
Output Match Output: MATCH will be HIGH if data in the data input
registers match the data stored in the memory array, assum-
ing MOE being LOW. MATCH will be LOW if data do not
match.
Document #: 38-05120 Rev. **
Page 4 of 24
CY7C1359A/GVT71256T18
Pin Descriptions (continued)
BGA Pins
TQFP Pins
Name
Type
Description
6P
51
MOE
Input
Match Output Enable: This active LOW asynchronous input
enables the MATCH output drivers.
7P, 6N, 6L, 7K, 58,59, 62, 63, 68, DQ1–
Input/
Output
Data Inputs/Outputs: Input data must meet setup and hold
times around the rising edge of CLK.
6H, 7G, 6F, 7E, 69, 72, 73, 74, 8,
6D, 1D, 2E, 2G, 9, 12, 13, 18, 19,
DQ18
1H, 2K, 1L, 2M,
22, 23, 24
1N, 2P
5U
42
TDO
Output
Input
IEEE 1149.1 test output. LVTTL-level output.
IEEE 1149.1 test inputs. LVTTL-level inputs.
2U
3U
4U
38
39
43
TMS
TDI
TCK
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
VCC
VSS
Supply
Ground
Power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 5, 10, 17, 21, 26,
3F, 5F, 5G, 3H, 40,55, 60, 67, 71,
Ground: GND
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
76, 90
1A,7A,1F,7F,1J, 4, 11, 20, 27, 54,
VCCQ
I/O Supply
-
Output Buffer Supply: +2.5V (from 2.375V to VCC)
7J, 1M, 7M, 1U,
7U
61, 70, 77
1B, 7B, 1C, 7C,
1-3, 6, 7, 14, 16,
NC
No Connect: These signals are not internally connected.
2D, 4D, 7D, 1E, 25, 28-30, 56, 57,
6E, 2F, 1G, 6G, 66,75, 78, 79, 95,
2H, 7H, 3J, 5J,
1K, 6K, 2L, 4L,
7L, 2N, 1P, 1R,
5R, 7R, 1T, 4T, 6U
96
Burst Address Table (MODE = GND)
Burst Address Table (MODE = NC/V
)
CC
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Partial Truth Table for MATCH[2, 3, 4, 5, 6]
Operation
READ Cycle
E
L
WE
H
L
DEN
MOE
OE
MATCH
DQ
Q
X
L
X
X
X
L
L
H
H
H
X
X
-
WRITE Cycle
L
-
-
D
Fill WRITE Cycle
L
L
H
L
High-Z
D
COMPARE Cycle
L
H
X
Output
H
Deselected Cycle (MATCH Out)
H
H
X
X
L
High-Z
High-Z
Deselected Cycle
X
H
High-Z
Notes:
2. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW.
3. E=L is defined as CE=LOW and CE2=LOW and CE2=HIGH. E =H is defined as CE=HIGH or CE2=HIGH or CE2=LOW. WE is defined as [BWE + WEL*WEH]*GW.
4. All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
Document #: 38-05120 Rev. **
Page 5 of 24
CY7C1359A/GVT71256T18
Truth Table[5, 6, 7, 8, 9, 10, 11]
Address
Used
Operation
CE CE2 CE2 ADSP ADSC
ADV WRITE OE
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
READ Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
Partial Truth Table for READ/WRITE[12]
Function
READ
GW
BWE
WEH
WEL
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
READ
WRITE one byte
WRITE all bytes
L
WRITE all bytes
X
X
Notes:
7. X means “Don’t Care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH. It is assumed in this truth table that DEN is LOW.
8. WEL enables write to DQ1–DQ9. WEH enables write to DQ10–DQ18.
9. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
10. Suspending burst generates wait cycle.
11. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
12. X means “don’t care.” H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP is HIGH along with DEN being LOW.
Document #: 38-05120 Rev. **
Page 6 of 24
CY7C1359A/GVT71256T18
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TAP circuitry does not have a Reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction reg-
ister with the IDCODE command. This type of reset does not
affect the operation of the system logic. The reset affects test
logic only.
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been modi-
fied or eliminated because their implementation places extra
delays in the critical speed path of the device. Nevertheless,
the device supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the TAP’s
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE Stan-
dard 1149.1 compliant TAPs. The TAP operates using
LVTTL/LVCMOS logic level signaling.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAP’s registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Instruction Register
The instruction register holds the instructions that are execut-
ed by the TAP controller when it is moved into the run test/idle
or the various data register states. The instructions are three
bits long. The register can be loaded when it is placed between
the TDI and TDO pins. The parallel outputs of the instruction
register are automatically preloaded with the IDCODE instruc-
tion upon power-up or whenever the controller is placed in the
test-logic reset state. When the TAP controller is in the Cap-
ture-IR state, the two least significant bits of the serial instruc-
tion register are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
TCK - Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS - Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS
when the BYPASS instruction is executed.
)
TDI - Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruc-
tion that is currently loaded in the TAP instruction register (re-
fer to Figure 1, TAP Controller State Diagram). It is allowable
to leave this pin unconnected if it is not used in an application.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI is connected to the most significant bit (MSB) of any reg-
ister. (See Figure 2.)
Boundary Scan Register
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for a x36 device and
51 bits for a x18 device. The boundary scan register, under the
control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the con-
troller is moved to Shift-DR state. The EXTEST, SAMPLE/
PRELOAD and SAMPLE-Z instructions can be used to cap-
ture the contents of the I/O ring.
TDO - Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed be-
tween TDI and TDO. TDO is connected to the least significant
bit (LSB) of any register. (See Figure 2.)
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s posi-
tion in the boundary scan register. The MSB of the register is
connected to TDI, and LSB is connected to TDO. The second
column is the signal name and the third column is the bump
number. The third column is the TQFP pin number and the
fourth column is the BGA bump number.
Document #: 38-05120 Rev. **
Page 7 of 24
CY7C1359A/GVT71256T18
Identification (ID) Register
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
TAP Controller Instruction Set
SAMPLE/PRELOAD
Overview
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
There are two classes of instructions defined in the IEEE Stan-
dard 1149.1-1990; the standard (public) instructions and de-
vice specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
When the SAMPLE/PRELOAD instruction is loaded in the in-
struction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture setup plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST, IN-
TEST, or the preload portion of the SAMPLE/PRELOAD com-
mand.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the in-
struction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
Moving the controller to Shift-DR state then places the bound-
ary scan register between the TDI and TDO pins. Because the
PRELOAD portion of the command is not implemented in this
device, moving the controller to the Update-DR state with the
SAMPLE/PRELOAD instruction loaded in the instruction reg-
ister has the same effect as the Pause-DR command.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
BYPASS
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP controller is in the Shift-DR state, the bypass
register is placed between TDI and TDO. This allows the board
level scan path to be shortened to facilitate testing of other
devices in the scan path.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
Reserved
Do not use these instructions. They are reserved for future
use.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Document #: 38-05120 Rev. **
Page 8 of 24
CY7C1359A/GVT71256T18
TEST-LOGIC
RESET
1
0
0
1
1
1
REUN-TEST/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
1
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Figure 1. TAP Controller State Diagram[13]
Note:
13. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05120 Rev. **
Page 9 of 24
CY7C1359A/GVT71256T18
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register [14]
TDI
TDI
TAP Controller
Figure 2. TAP Controller Block Diagram
TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Description
Test Conditions
Min.
2.0
Max.
VCC + 0.3
0.8
Unit
VIH
VIl
Input High (Logic 1) Voltage[15, 16]
Input Low (Logic 0) Voltage[15, 16]
Input Leakage Current
V
V
–0.3
–5.0
–5.0
ILI
0V < VIN < VCC
5.0
µA
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
5.0
VOLC
VOHC
VOLT
LVCMOS Output Low Voltage[15, 17] IOLC = 100 µA
LVCMOS Output High Voltage[15, 17] IOHC = 100 µA
0.2
0.4
V
V
V
V
VCC – 0.2
LVTTL Output Low Voltage[15]
LVTTL Output High Voltage[15]
IOLT = 8.0 mA
IOHT = 8.0 mA
VOHT
2.4
Notes:
14. X = 53 for this device.
15. All Voltage referenced to VSS (GND).
16. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed VCC. Control input signals (such as GW, ADSC, etc.) may not have pulse widths less than tKHKL (min.).
17. This parameter is sampled.
Document #: 38-05120 Rev. **
Page 10 of 24
CY7C1359A/GVT71256T18
TAP AC Switching Characteristics Over the Operating Range[18, 19]
Parameter
Clock
Description
Min.
Max
Unit
tTHTH
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
fTF
50
tTHTL
8
8
tTLTH
ns
Output Times
tTLQX
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
tTLQV
10
tDVTH
5
5
tTHDX
Set-up Times
tMVTH
TMS Set-up
5
5
ns
ns
tCS
Capture Set-up
Hold Times
tTHMX
TMS Hold
5
5
ns
ns
tCH
Capture Hold
Notes:
18. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
19. Test conditions are specified using the load in TAP AC Test Conditions.
Document #: 38-05120 Rev. **
Page 11 of 24
CY7C1359A/GVT71256T18
TAP Timing and Test Conditions
ALL INPUT PULSES
3.0V
1.5V
TDO
Z0 = 50
Ω
50Ω
20 pF
V
SS
1.0 ns
1.0 ns
Vt = 1.5V
(a)
t
t
THTL
TLTH
t
THTH
TEST CLOCK
(TCK)
t
t
MVTH
THMX
TEST MODE SELECT
(TMS)
t
t
DVTH
THDX
TEST DATA IN
(TDI)
t
TLQV
t
TLQX
TEST DATA OUT
(TDO)
Document #: 38-05120 Rev. **
Page 12 of 24
CY7C1359A/GVT71256T18
Identification Register Definitions
Instruction Field
512K x 18
Description
REVISION NUMBER
(31:28)
XXXX
Reserved for revision number.
DEVICE DEPTH
(27:23)
00111
00011
Defines depth of 256K words.
Defines width of x18 bits.
Reserved for future use.
DEVICE WIDTH
(22:18)
RESERVED
(17:12)
XXXXXX
CYPRESS JEDEC ID CODE (11:1)
00011100100
1
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
ID Register Presence
Indicator (0)
Scan Register Sizes
Register Name
Instruction
Bit Size
3
1
Bypass
ID
32
54
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
010
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
100
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
Document #: 38-05120 Rev. **
Page 13 of 24
CY7C1359A/GVT71256T18
Boundary Scan Order (continued)
Boundary Scan Order
Bit#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Signal Name
CE
TQFP
98
99
100
8
Bump ID
4E
Bit#
1
Signal Name
A
TQFP
44
45
46
47
48
49
50
51
52
53
58
59
62
63
64
68
69
72
73
74
80
81
82
83
84
85
86
87
88
89
92
93
94
97
Bump ID
2R
2T
A
3A
2
A
A
2A
3
A
3T
DQ10
DQ11
DQ12
DQ13
NC
ID
4
A
5T
9
2E
5
A
6R
3B
5B
6P
7N
6M
7P
6N
6L
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
2G
1H
5R
2K
6
A
7
A
8
MOE
DEN
MATCH
DQ1
DQ2
DQ3
DQ4
ZZ
DQ14
DQ15
DQ16
DQ17
DQ18
MODE
A
9
1L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
7K
7T
A
DQ5
DQ6
DQ7
DQ8
DQ9
A
6H
7G
6F
A
A
A1
7E
6D
6T
A0
Maximum Ratings
A
6A
5A
4G
4A
4B
4F
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
A
ADV
ADSP
ADSC
OE
Voltage on VCC Supply Relative to VSS..........–0.5V to +4.6V
VIN .......................................................... –0.5V to VCC+0.5V
Storage Temperature (plastic) ................... –55°C to +150°C
Junction Temperature ............................................... +150°C
Power Dissipation.......................................................... 1.0W
Short Circuit Output Current........................................ 50 mA
BWE
GW
CLK
CE2
WEL
WEH
CE2
4M
4H
4K
6B
5L
Operating Range
Ambient
Range
Com’l
Temperature[20]
VCC
3G
2B
0°C to +70°C
3.3V −5%/+10%
Note:
20. TA is the case temperature.
Document #: 38-05120 Rev. **
Page 14 of 24
CY7C1359A/GVT71256T18
Electrical Characteristics Over the Operating Range
Parameter
VIHD
VIH
Description
Input High (Logic 1) Voltage[15, 21]
Test Conditions
Data Inputs (DQxx)
Min.
1.7
1.7
–0.3
–2
Max.
Unit
V
VCC+0.3
All Other Inputs
4.6
0.8
2
V
VIl
Input Low (Logic 0) Voltage[15, 21]
Input Leakage Current[22]
Output Leakage Current
V
ILI
0V < VIN < VCC
µA
µA
V
ILO
Output(s) disabled, 0V < VOUT < VCC
IOH = –4.0 mA at VCCQ = 3.135V
IOH = –4.0 mA at VCCQ = 2.375V
IOL = 8.0 mA
–2
2
VOH
VOH
VOL
Output High Voltage[15, 23]
2.4
1.7
Output Low Voltage[15, 23]
Supply Voltage[15]
I/O Supply Voltage[15]
0.4
3.6
V
V
V
VCC
3.135
2.375
VCCQ
VCC
166
150
133
100
MHz/ MHz/ MHz/ MHz/
Parameter
Description
Conditions
Typ.
-6
-6.7
-7.5
-10
Unit
ICC
Power Supply
Current:
Device selected; all inputs < VILor > VIH;
cycle time > tKC min.; VCC = Max.;
outputs open
100
310
275
250
190
mA
Operating[24, 25, 26]
ISB2
ISB3
ISB4
CMOS Standby[25, 26] Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or > VCC – 0.2;
5
10
20
80
10
20
70
10
20
60
10
20
50
mA
mA
mA
all inputs static; CLK frequency = 0
TTL Standby[25, 26]
Device deselected; all inputs < VIL
or > VIH; all inputs static;
10
40
VCC = Max.; CLK frequency = 0
Clock Running[25, 26] Device deselected;
all inputs < VIL or > VIH; VCC = Max.;
CLK cycle time > tKC min.
Capacitance[17]
Parameter
Description
Test Conditions
Typ.
Max.
Unit
CI
Input Capacitance
Input/Output Capacitance (DQ)
TA = 25°C, f = 1 MHz,
4
7
5
8
pF
pF
VCC = 3.3V
CO
Thermal Resistance
Description
Test Conditions
Symbol BGA Typ. TQFP Typ. Unit
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
ΘJA
ΘJC
19
9
25
9
°C/W
°C/W
4-layer PCB
Thermal Resistance (Junction to Case)
Note:
21. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
Undershoot:VIL ≤ –2.0V for t ≤ tKC /2.
22. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA.
23. AC I/O curves are available upon request.
24. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
25. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
26. Typical values are measured at 3.3V, 25°C, and 8.5-ns cycle time.
Document #: 38-05120 Rev. **
Page 15 of 24
CY7C1359A/GVT71256T18
AC Test Loads and Waveforms
ALL INPUT PULSES
+2.5v
1,667
DQ
2.5V
0V
90%
10%
90%
Z = 50
Ω
50Ω
30 pF
Ω
0
10%
DQ
Vt = 1.25V
(a)
≤ 1.8 ns
≤ 1.8 ns
1,538Ω
5 pF
(c)
(b)
Switching Characteristics Over the Operating Range[27]
-6
-6.7
150 MHz
-7.5
133 MHz
-10
100 MHz
166 MHz
Parameter
Clock
tKC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
6.0
6.7
7.5
8.5
ns
Clock Frequency
Clock HIGH Time
Clock LOW Time
tKF
tKH
2.4
2.4
2.6
2.6
2.8
2.8
3.4
3.4
ns
ns
tKL
Output Times
tKQ
Clock to Output Valid
3.5
3.8
4.0
4.0
ns
ns
tKM
Clock to MATCH Valid
tKQX
Clock to Output Invalid
1.5
1.5
1.5
1.5
tKMX
Clock to MATCH Invalid
tKQLZ
Clock to Output in Low-Z[17, 28, 29]
Clock to Output in High-Z[17, 28, 29]
OE to Output Valid[30]
0
0
0
0
ns
ns
ns
tKQHZ
tOEQ
tMOEM
tOELZ
1.5
6.0
3.5
1.5
6.7
3.5
1.5
7.5
3.8
1.5
8.5
3.8
MOE to MATCH Valid[30]
OE to Output in Low-Z[17, 28, 29]
MOE to MATCH in Low-Z[17, 28, 29]
OE to Output in High-Z[17, 28, 29]
MOE to MATCH in High-Z[17, 28, 29]
0
0
0
0
ns
ns
tMOELZ
tOEHZ
tMOEHZ
Set-up Times
tS
3.5
3.5
3.8
3.8
Address, Controls, and Data In[31]
Address, Controls, and Data In[31]
1.5
0.5
1.5
0.5
1.5
0.5
2.0
0.5
ns
ns
Hold Times
tH
Notes:
27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
28. Output loading is specified with CL = 5 pF as in AC Test Loads.
29. At any given temperature and voltage condition, tKQHZ is less than tKQLZ, tOEHZ is less than tOELZ and tMOEHZ is less than tMOELZ
30. OE is a “Don’t Care” after a write cycle begins To prevent bus contention, OE should be negated prior before the start of write cycle.
31. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table.
.
Document #: 38-05120 Rev. **
Page 16 of 24
CY7C1359A/GVT71256T18
Typical Output Buffer Characteristics
Output High Voltage
Pull-Up Current
Output Low Voltage
Pull-Down Current
VOH (V)
–0.5
0
IOH (mA) Min. IOH (mA) Max.
VOL (V)
–0.5
0
IOL (mA) Min. IOL(mA) Max.
–38
–38
–38
–26
–20
0
–105
–105
–105
–83
–70
–30
–10
0
0
0
0
0
0.8
0.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
1.25
1.5
0.8
1.25
1.6
2.3
2.7
0
2.8
2.9
0
3.2
3.4
0
0
3.4
Document #: 38-05120 Rev. **
Page 17 of 24
CY7C1359A/GVT71256T18
Switching Waveforms
Read Timing with Burst Feature[32, 33]
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
tH
WEL#, WEH#,
BWE#, GW#
tS
CE#
ADV#
OE#
DQ
tS
tH
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Notes:
32. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active.
33. In this timing diagram, it is assumed that DEN is tied to LOW (VSS).
Document #: 38-05120 Rev. **
Page 18 of 24
CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Write Timing with Burst Feature[32, 33]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
A3
tH
WEL#, WEH#,
BWE#
GW#
CE#
tS
ADV#
OE#
DQ
tH
tOEHZ
tKQX
Q
D(A1)
D(A2) D(A2+1) D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1) D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05120 Rev. **
Page 19 of 24
CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Read/Write Timing with Burst Feature[32, 33]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A2
A3
A4
A5
A1
tH
WEL#, WEH#,
BWE#, GW#
CE#
ADV#
OE#
DQ
Q(A1)
Single Reads
Q(A2)
D(A3)
Single Write
Q(A4)
Q(A4+1) Q(A4+2)
D(A5)
D(A5+1)
Burst Read
Burst Write
Document #: 38-05120 Rev. **
Page 20 of 24
CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Read/Write Timing without Burst Feature[32, 34, 35]
tKH
tKC
tKL
CLK
tS
ADDRESS
WE#
A2
A3
A4
A5
A6
A7
A8
A1
tH
CE#
DEN#
OE#
tOEQ
tOEHZ
tKQHZ
tOELZ
tKQLZ
tKQX
tKQ
Q(A1)
Q(A2)
Q(A3)
Q(A4)
D(A5)
D(A6)
D(A7)
D(A8)
DQ
Reads
Writes
Notes:
34. In this timing diagram, it is assumed that burst feature is not used and therefore ADSP is tied to HIGH (VCC) and ADSC is tied to LOW (VSS). The logic state
of ADV is a “Don’t Care”.
35. In this timing diagram, it is assumed that WE = [BWE + WEL*WEH]*GW.
Document #: 38-05120 Rev. **
Page 21 of 24
CY7C1359A/GVT71256T18
Switching Waveforms (continued)
Compare/Fill Write Timing[32, 34, 35]
tKH
tKC
tKL
CLK
tS
ADDRESS
WE#
A1
A1
A2
tH
CE#
DEN#
OE#
D(A1)
D(A2)
DQ
tMOEHZ
tMOEM
tKM
MOE#
MATCH
MATCH HIGH
CHIP DESELECTED
tMOELZ
tKMX
FILL
WRITE
MISS
HIT
Document #: 38-05120 Rev. **
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CY7C1359A/GVT71256T18
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
166
CY7C1359A-166AC/
GVT71256T18T-6
A101
A101
A101
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
150
133
100
CY7C1359A-150AC/
GVT71256T18T-6.7
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
CY7C1359A-133AC/
GVT71256T18T-7.5
CY7C1359A-100AC/
GVT71256T18T-10
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1359A/GVT71256T18
Document Title: CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM
Document Number: 38-05120
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
108311
09/25/01
BRI
New Cypress spec—converted from Galvantech format
Document #: 38-05120 Rev. **
Page 24 of 24
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