GVT71256F18T-6 [CYPRESS]
Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | GVT71256F18T-6 |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 256KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
128K x 36/256K x 18
Synchronous-Pipelined Cache RAM
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a posi-
tive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write En-
ables (BW1, BW2, BW3, BW4, and BWE), and Global Write
Features
• Fast access times: 3.5, 3.8, and 4.0 ns
• Fast clock speed: 166, 150, 133, and 117 MHz
• Provide high performance 3-1-1-1 access rate
• Fast OE access times: 3.5 ns and 3.8 ns
• Optimal for performance (double cycle chip deselect,
depth expansion without wait state)
• 3.3V –5% and +10% core power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
(GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
• Clamp diodes to V
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
at all inputs and outputs
SSQ
• Three chip enables for depth expansion and address
pipeline
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BW1
controls DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and
DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls
DQ25–DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be
active only with BWE being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows writ-
ten data available at the output for the immediately next READ
cycle. This device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system performance.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1348A/GVT71128F36/CY7C1328A/GVT71256F18
operates from a +3.3V core power supply and all outputs op-
erate on a +2.5V supply. All inputs and outputs are JEDEC
standard JESD8-5 compatible. The device is ideally suited for
486, Pentium®, 680x0, and PowerPC™ systems and for sys-
tems that benefit from a wide synchronous data bus.
The
CY7C1348A/GVT71128F36
and
CY7C1328A/
GVT71256F18 SRAM integrate 262,144x18 and 131,072x36
SRAM cells with advanced synchronous peripheral circuitry
Selection Guide
7C1328A-166
7C1328A-150
71256F18-4
7C1348A-150
71128F36-4
7C1328A-133
71256F18-5
7C1348A-133
71128F36-5
7C1328A-117
71256F18-6
7C1348A-117
71128F36-6
71256F18-3
7C1348A-166
71128F36-3
Maximum Access Time (ns)
3.5
425
10
3.8
400
10
4.0
375
10
4.0
350
10
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 14, 2000
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Functional Block Diagram—128Kx36[1]
BYTE
1
2
3
4
WRITE
BW1#
BWE#
D
Q
CLK
BYTE
WRITE
BW2#
D
Q
GW#
BYTE
WRITE
BW3#
D
Q
BYTE
WRITE
BW4#
D
Q
ENABLE
CE#
CE2
D
Q
D
Q
CE2#
OE#
ZZ
Power Down Logic
Input
Register
ADSP#
A16-A2
Address
Register
OUTPUT
REGISTER
ADSC#
DQ1-DQ32,
DQP1,DQP2
DQp3,DQp4
CLR
D
Q
ADV#
A1-A0
MODE
Binary
Counter
&
Logic
Functional Block Diagram—256Kx18[1]
UPPER BYTE
WRITE
W E H #
B W E #
D
Q
LOWER BYTE
WRITE
W E L #
G W #
D
Q
ENABLE
CE#
CE2
D
Q
D
Q
CE2#
ZZ
Power Down Logic
OE#
ADSP#
Input
Register
A17-A2
Address
Register
OUTPUT
REGISTER
ADSC#
DQ1-
DQ16,
DQP1,
DQP2
CLR
D
Q
ADV#
Binary
Counter
& Logic
A1-A0
MODE
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Pin Configurations
100-Pin TQFP
Top View
DQP3
1
DQP2
DQ16
DQ15
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
A10
NC
NC
V
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ17
2
DQ18
3
4
5
6
7
8
9
V
CCQ
V
V
V
CCQ
CCQ
CCQ
V
SSQ
V
SSQ
SSQ
NC
NC
DQ9
DQ10
V
SSQ
DQ19
DQ20
DQ21
DQ22
DQ14
DQ13
DQ12
DQ11
NC
DQP1
DQ8
DQ7
9
V
SSQ
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SSQ
SSQ
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
V
CCQ
V
CCQ
CCQ
V
CCQ
DQ23
DQ24
NC
DQ10
DQ9
DQ11
DQ12
NC
DQ6
DQ5
V
SS
V
SS
V
CC
NC
NC
V
CC
CY7C1328A/GVT71256F18
(256K x 18)
NC
CY7C1348A/GVT71128F36
(128K X 36)
V
NC
CC
V
CC
V
SS
ZZ
DQ8
DQ7
V
SS
ZZ
DQ4
DQ3
DQ25
DQ26
DQ13
DQ14
V
CCQ
V
CCQ
V
CCQ
V
CCQ
V
SSQ
V
V
SSQ
SSQ
V
SSQ
DQ27
DQ28
DQ29
DQ30
DQ6
DQ5
DQ4
DQ3
DQ15
DQ16
DQP2
NC
DQ2
DQ1
NC
NC
V
SSQ
V
V
V
SSQ
SSQ
V
SSQ
V
CCQ
V
CCQ
CCQ
V
CCQ
DQ31
DQ32
DQP4
DQ2
DQ1
DQP1
NC
NC
NC
NC
NC
NC
3
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Pin Descriptions
Name
Type
Description
A0
A1
A2–A17
(A17 for X18)
Input-
Synchronous
Addresses: These inputs are registered and must meet the set-up and hold times around the
rising edge of CLK. The burst counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
BW1
BW2
BW3
BW4
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ
cycle. BW1 controls DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and DQP2. BW3 con-
trols DQ17–DQ24 and DQP3. BW4 controls DQ25–DQ32 and DQP4. Data I/O are high im-
pedance if either of these inputs are LOW, conditioned by BWE being LOW. BW1 is equal to
WEL and BW2 is equal to WEH for X18 device.
BWE
GW
Input-
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the set-up
and hold times around the rising edge of CLK.
Input-
Synchronous
Global Write: This active LOW input allows a full 38-bit (18-bit for X18 device) WRITE to occur
independent of the BWE and BWn lines and must meet the set-up and hold times around the
rising edge of CLK.
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control
inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the
clock’s rising edge.
CE
Input-
Chip Enable: This active LOW input is used to enable the device and to gate ADSP.
Synchronous
CE2
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device.
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
OE
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the internal burst counter. A HIGH
on this pin generates wait cycle (no address advance).
ADSP
ADSC
Input-
Synchronous
Address Status Processor: This active LOW input, along with CE being LOW, causes a new
external address to be registered and a READ cycle is initiated using the new address.
Input-
Synchronous
Address Status Controller: This active LOW input causes device to be deselected or selected
along with new external address to be registered. A READ or WRITE cycle is initiated depend-
ing upon write control inputs.
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or
HIGH on this pin selects Interleaved Burst.
Input-
Snooze: This active HIGH input puts the device in low power consumption standby mode. For
Asynchronous normal operation, this input has to be either LOW or NC (No Connect).
DQ1–8
DQ9–16
DQ17–24
DQ25–32
Input/
Output
Data Inputs/Outputs: Byte one is DQ1–DQ8. Byte two is DQ9–DQ16. Byte three is
DQ17–DQ24. Byte four is DQ25–DQ32. Input data must meet set-up and hold times around
the rising edge of CLK. X18 only has two bytes (Byte one and Byte two).
DQP1–
DQP4
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity bit for DQ9–DQ16.
DQP3 is parity bit for DQ17–DQ24 and DQP4 is parity bit for DQ25–DQ32.
V
V
Supply
Ground
I/O Supply
I/O Ground
-
Power Supply: +3.3V –5% and +10%.
CC
SS
Ground: GND.
V
Output Buffer Supply: +2.5V (from 2.375V to V ).
CCQ
CC
V
Output Buffer Ground: GND.
SSQ
NC
No Connect: These signals are not internally connected. User can connect them to V , V
,
CC SS
or any signal. They can be left unconnected as floating.
4
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Burst Address Table (MODE = NC/V
)
Burst Address Table (MODE = GND)
CC
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
CE CE2 CE2 ADSP ADSC
ADV
X
X
X
X
X
X
X
X
X
X
L
WRITE OE
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
READ Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
WRITE Cycle, Suspend Burst
L
D
Notes:
2. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
3. BWa enables write to DQa. BWb enables write to DQb.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
5
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Partial Truth Table for READ/WRITE
Function
GW
H
BWE
BW1
BW2
X
BW3
X
BW4
X
READ
READ
H
L
L
L
X
X
H
L
H
H
H
H
WRITE one byte
WRITE all bytes
WRITE all bytes
H
H
H
H
H
L
L
L
L
L
X
X
X
X
Power Dissipation.......................................................... 1.0W
Short Circuit Output Current........................................ 50 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Voltage on V Supply Relative to V ......... –0.5V to +4.6V
CC
SS
Ambient
V
...........................................................–0.5V to V +0.5V
CC
[9]
IN
Range
Com’l
Temperature
V
CC
Storage Temperature (plastic) .......................–55°C to +150°
Junction Temperature ..................................................+150°
0°C to +70°C
3.3V −5%/+10%
Note:
9.
TA is the case temperature.
6
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Data Inputs (DQxx)
All Other Inputs
Min.
1.7
1.7
–0.3
–2
Max.
V +0.3
CC
Unit
V
[10, 11]
V
Input High (Logic 1) Voltage
IHD
IH
Il
V
V
4.6
V
[10, 11]
Input Low (Logic 0) Voltage
0.7
2
V
[12]
IL
Input Leakage Current
0V < V < V
CC
µA
µA
V
I
IN
IL
Output Leakage Current
Output(s) disabled, 0V < V
< V
CC
–2
2
O
OUT
[10, 13]
V
Output High Voltage
I
= –2.0 mA
1.7
OH
OH
OL
[10, 13]
V
Output Low Voltage
I
= 2.0 mA
0.7
3.6
V
OL
[10]
V
Supply Voltage
3.135
2.375
V
CC
[10]
V
I/O Supply Voltage
V
V
CCQ
CC
Parameter
Description
Conditions
Device selected; all inputs < V or > V ;
Typ.
-4
-4.4
-5
-6
Unit
I
Power Supply
Current:
150
425
400
375
350
mA
CC
IL
IH
cycle time > t min.; V = Max.;
KC
CC
[14, 15, 16]
Operating
outputs open
[15, 16]
I
I
I
CMOS Standby
Device deselected; V = Max.;
5
10
10
10
10
20
60
mA
mA
mA
SB2
SB3
SB4
CC
all inputs < V + 0.2 or >V – 0.2;
SS
CC
all inputs static; CLK frequency = 0
[15, 16]
TTL Standby
Device deselected; all inputs < V
10
40
20
20
20
IL
or > V ; all inputs static;
IH
V
= Max.; CLK frequency = 0
CC
[15, 16]
Clock Running
Device deselected;
all inputs < V or > V ; V = Max.;
90
80
70
IL
IH CC
CLK cycle time > t min.
KC
Capacitance[17]
Parameter
Description
Test Conditions
Typ.
Max.
Unit
C
C
Input Capacitance
T = 25°C, f = 1 MHz,
5
7
7
8
pF
pF
I
A
V
= 3.3V
CC
Input/Output Capacitance (DQ)
O
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Unit
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
Θ
25
9
°C/W
°C/W
JA
JC
4-layer PCB
Thermal Resistance (Junction to Case)
Θ
Note:
10. All voltages referenced to VSS (GND).
11. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
Undershoot:VIL ≤ –2.0V for t ≤ tKC /2
12. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA.
13. AC I/O curves are available upon request.
14. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
15. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
16. Typical values are measured at 3.3V, 25°C, and 8.5-ns cycle time.
17. This parameter is sampled.
7
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
AC Test Loads and Waveforms
DQ
ALL INPUT PULSES
2.5V
0V
90%
10%
=50
Z
0
Ω
90%
10%
50
Ω
V = 1.25V
t
Rise Time:
1 V/ns
Fall Time:
1 V/ns
(b)
(a)
[18]
Switching Characteristics Over the Operating Range
-3
166 MHz
-4
150 MHz
-5
133 MHz
-6
117 MHz
Parameter
Clock
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
t
t
Clock Cycle Time
6.0
2.4
2.4
6.7
2.6
2.6
7.5
2.8
2.8
8.5
3.4
3.4
ns
ns
ns
KC
KH
KL
Clock HIGH Time
Clock LOW Time
Output Times
t
t
t
t
t
t
t
Clock to Output Valid
3.5
3.8
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
KQ
Clock to Output Invalid
Clock to Output in Low-Z
Clock to Output in High-Z
1.5
0
1.5
0
1.5
0
1.5
0
KQX
[17, 19, 20]
[17, 19, 20]
KQLZ
KQHZ
OEQ
OELZ
OEHZ
1.5
6.0
3.5
1.5
6.7
3.5
1.5
7.5
3.8
1.5
8.5
3.8
[21]
OE to Output Valid
[17, 19, 20]
OE to Output in Low-Z
OE to Output in High-Z
0
0
0
0
[17, 19, 20]
3.5
3.5
3.8
3.8
Set-up Times
[22]
t
Address, Controls, and Data In
1.5
0.5
1.5
0.5
1.5
0.5
2.0
0.5
ns
ns
S
Hold Times
[22]
t
Address, Controls, and Data In
H
Typical Output Buffer Characteristics
Output High Voltage
(V)
Pull-Up Current
Output Low Voltage
(V)
Pull-Down Current
V
I
(mA) Min.
I
(mA) Max.
–105
–105
–105
–83
V
I
(mA) Min.
I (mA) Max.
OL
OH
OH
OH
OL
OL
–0.5
0
–38
–38
–38
–26
–20
0
–0.5
0
0
0
0
0
0.8
1.25
1.5
2.3
2.7
2.9
3.4
0.4
0.8
1.25
1.6
2.8
3.2
3.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
–70
–30
0
–10
0
0
0
0
Notes:
18. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
19. Output loading is specified with CL = 5 pF as in AC Test Loads.
20. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
.
21. OE is a “Don’t Care” when a byte write enable is sampled LOW.
22. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table.
8
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Switching Waveforms
[23, 24]
Read Timing
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
tH
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
tS
CE#
ADV#
OE#
DQ
tS
tH
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Notes:
23. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active.
24. For X18 product, there are only BW1 (i.e., WEL) and BW2 (i.e., WEH) for byte write control.
9
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Switching Waveforms (continued)
[23, 24]
Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
A1
A2
A3
ADDRESS
tH
BW1#, BW2#,
BW3#, BW4#,
BWE#
GW#
CE#
tS
ADV#
OE#
DQ
tH
tOEHZ
tKQX
Q
D(A1)
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
10
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Switching Waveforms (continued)
[23, 24]
Read/Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A2
A3
A4
A5
A1
tH
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
CE#
ADV#
OE#
DQ
Q(A1)
Single Reads
Q(A2)
D(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
D(A5)
D(A5+1)
Single Write
Burst Read
Burst Write
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C1328A-166AC/
Package Type
166
A101
A101
A101
A101
A101
A101
A101
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
GVT71256F18T-3
150
133
117
166
150
133
117
CY7C1328A-150AC/
GVT71256F18T-4
CY7C1328A-133AC/
GVT71256F18T-5
CY7C1328A-117AC/
GVT71256F18T-6
CY7C1348A-166AC/
GVT71128F36T-3
CY7C1348A-150AC/
GVT71128F36T-4
CY7C1348A-133AC/
GVT71128F36T-5
CY7C1348A-117AC/
GVT71128F36T-6
Document #: 38-00999
11
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
PRELIMINARY
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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