CYF0072V33L-150BGXI [CYPRESS]
FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209;
| 型号： | CYF0072V33L-150BGXI |
| 厂家： | 
CYPRESS |
| 描述： | FIFO, PBGA209, 14 X 22 MM, 1.76 MM HEIGHT, FPBGA-209 先进先出芯片 |
| 文件： | 总25页 (文件大小：642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
PRELIMINARY
18/36/72/144 Mbit Programmable FIFOs
18/36/72/144 Mbit Programmable FIFOs
Features
Functional Description
■ Memory organization
❐ Industry's largest first in first out (FIFO) memory densities:
18 Mbit, 36 Mbit, 72 Mbit, and 144 Mbit
❐ Selectable memory organization: ×9, ×12, ×16, ×18, ×20,
×24, ×32, ×36
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
150 MHz. You can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 5.4 Gbps. The read and write ports can support
multiple I/O voltage standards. The user-programmable
registers enable you to configure the device operation as
desired. The device also offers a simple and easy-to-use
interface to reduce implementation and debugging efforts,
improve time-to-market, and reduce engineering costs. This
makes it an ideal memory choice for a wide range of applications
including multiprocessor interfaces, video and image
processing, networking and telecommunications, high-speed
data acquisition, or any system that needs buffering at very high
speeds across different domains.
■ Up to 150-MHz clock operation
■ Unidirectional operation
■ Independent read and write ports
❐ Supports simultaneous read and write operations
❐ Reads and writes operate on independent clocks enabling
data buffering across clock domains
❐ Separate input/output (I/O) supply for read and write I/O ports
❐ Selectable I/O voltage standard: supports 3.3 V, 2.5 V,
1.8 V, and 1.5 V voltage standards.
❐ Available in low voltage complementary metal oxide
semiconductor (LVCMOS) and high-speed transceiver logic
(HSTL) one-half I/O standard
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. The data is sequentially
written into the FIFO from the write port. If the writes and inputs
are enabled, the data on the write port gets written into the device
at the rising edge of the write clock. Enabling the reads and
outputs fetches data on the read port at every rising edge of the
read clock. Both reads and writes can occur simultaneously at
different speeds. Appropriate flags are set whenever the FIFO is
empty, full, half-full, almost-full, or almost-empty.
■ Input and output enable control for write mask and read skip
operations
■ User configured multi-queue operating mode
■ Mark and retransmit: resets read pointer to user marked
position
■ Empty, full, half-full, and programmable almost-empty and
almost-full status flags with preselected offsets
The device also supports multi-queue operation, mark and
retransmit of data, and a mailbox register.
■ Mailbox register to send data from input to output port,
bypassing the FIFO sequence
All product features and specs are common to all densities
(CYFX144VXXX, CYFX072VXXX, CYFX036VXXX, and
CYF018VXXX) unless otherwise specified.
■ Configure programmable flags and registers through serial or
parallel modes
■ Separate serial clock (SCLK) input for serial programming
■ Master reset to clear entire FIFO
■ Partial reset to clear data but retain programmable settings
■ Joint test action group (JTAG) port provided for boundary scan
function
■ Industrial temperature range: –40 °C to +85 °C
Cypress Semiconductor Corporation
Document Number: 001-53687 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 6, 2011
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Logic Block Diagram
Document Number: 001-53687 Rev. *G
Page 2 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Contents
Pin Diagram .......................................................................4
Pin Definitions .................................................................. 5
Architecture ...................................................................... 7
Reset Logic ................................................................. 7
Flag Operation ............................................................ 7
Full Flag ...................................................................... 7
Half-Full Flag ............................................................... 7
Empty Flag .................................................................. 7
Programmable Almost-Empty and
Almost-Full Flags ................................................................ 7
Retransmit from Mark Operation ................................. 7
Mailbox Register .........................................................7
Selecting Word Sizes .................................................. 8
Power Up ........................................................................... 8
Write Mask and Read Skip Operation ......................... 8
Multi-Queue Operation ................................................ 8
Programming Flag Offsets and
Width Expansion Configuration ................................. 11
Memory Organization for Different Port Sizes .......... 12
Read/Write Clock Requirements ............................... 12
Device Specific Functionality Table .......................... 12
Maximum Ratings ........................................................... 13
Operating Range ............................................................ 13
Switching Characteristics ............................................. 15
Switching Waveforms .................................................... 16
Ordering Information ..................................................... 21
Part Numbering Nomenclature ................................. 21
Package Diagram ........................................................... 22
Acronyms ........................................................................ 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ...................... 25
Products .................................................................... 25
PSoC Solutions ......................................................... 25
Configuration Registers ...................................................... 9
Document Number: 001-53687 Rev. *G
Page 3 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Pin Diagram
Figure 1. 209-Ball FBGA (Top View)
1
2
3
4
5
6
PORTSZ1
PORTSZ2
DNU
7
DNU
8
RQSEL0
RQSEL1
RQSEL2
VCC1
VCC2
VSS
9
10
Q0
11
Q1
A
B
C
D
E
F
FF
EF
D0
D1
D3
WQSEL0 PORTSZ0
RT
D2
WQSEL1
DNU
VCC1
DNU
REN
RCLK
Vss
Q2
Q3
D4
D5
WEN WQSEL2
VCC1
Q4
Q5
D6
D7
VSS
VCC2
VSS
VCC1
VCC2
VSS
DNU
LD
DNU
Q6
Q7
D8
D9
VCCIO_W
VSS
VCCIO_W
VSS
VCCIO_W
VSS
VCCIO_W
VSS
VCCIO_W
VSS
VCCIO_W
VCC1
VCCIO_W
DNU
VCCIO_R
VSS
VCCIO_R
VSS
VCCIO_R
VSS
VCCIO_R
VSS
VCCIO_R
VSS
VCCIO_R
VCC1
VCC2
VSS
Q8
Q9
D10
D12
D14
D16
DNU
D18
D20
D22
D24
D26
D28
DVal
PAF
TDO
D11
D13
D15
D17
DNU
D19
D21
D23
D25
D27
D29
DNU
PAE
HF
Q10
Q12
Q14
Q16
Q11
Q13
Q15
Q17
G
H
J
VCC2
VSS
VCC2
VSS
VCC1
VCC2
VSS
VCC2
VSS
VCC1
VCC2
WCLK
VCC2
VSS
VCC2
DNU
VCC2
VSS
VCC1
VCC2
DNU
VCC2
VSS
VCC2
K
L
IE
VCCIO_R VCCIO_R VCCIO_R
VCC1
VCC2
VSS
Q18
Q20
Q22
Q24
Q26
Q28
Q30
Q32
Q34
Q19
Q21
Q23
Q25
Q27
Q29
Q31
Q33
Q35
M
N
P
R
T
VCC1
VCC2
VSS
VCC2
VSS
VCC1
VCC2
VSS
VCC2
VSS
SPI_SEN
VCCIO_R
SPI_SI
DNU
VCC2
VSS
VCC2
VCC1
D31
VCC2
VCC1
Vref
VCC2
VSS
U
V
W
D30
PRS
SPI_SCLK
MB
OE
D32
D33
DNU
MRS
DNU
TCK
MARK
Vref
D34
D35
TDI
TRST
TMS
Document Number: 001-53687 Rev. *G
Page 4 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Pin Definitions
Pin Name
D[35:0]
I/O
Input
Pin Description
Data inputs: Data inputs for a 36-bit bus
Q[35:0]
WEN
REN
IE
Output Data outputs: Data outputs for a 36-bit bus
Input
Input
Input
Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers.
Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for 'write masking' or incrementing the write pointer without writing into a location.
OE
Input
Input
Input
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
WCLK
RCLK
Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and
into the configuration registers if LD is low.
Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is
high and from the configuration registers if LD is low.
EF
Output Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
Output Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Output Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty
offset value programmed into the FIFO. It is synchronized to RCLK.
PAF
LD
Output Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset
value programmed into the FIFO. It is synchronized to WCLK.
Input
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO
RT
Input
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to the write pointer.
MRS
Input
Input
Input
Master reset: MRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Master Reset, the configuration registers are all set to default values.
PRS
Partial reset: PRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Partial Reset, the configuration register settings are all retained.
SPI_SCLK
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
SPI_SI
SPI_SEN
MARK
Input
Input
Input
Serial input: Serial input of SPI_SEN is enabled.
Serial enable: Enables serial loading of programmable flag offsets and configuration registers.
Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any
subsequent retransmit operation resets the read pointer to this position.
MB
Input
Input
Input
Input
Input
Input
Input
Mailbox: When asserted the reads and writes happen to mailbox register.
Write queue select: Write queue select pin. Select maximum eight queues using pins.
Read queue select: Read queue select pin. Select maximum eight queues using pins.
Test clock (TCK) Pin for JTAG
WQSEL[2:0]
RQSEL[2:0]
TCK
TRST
TMS
Reset pin for JTAG
Test mode select (TMS) pin for JTAG
TDI
Test data in (TDI) pin for JTAG
TDO
Output Test data out (TDO) for JTAG
Document Number: 001-53687 Rev. *G
Page 5 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Pin Definitions (continued)
Pin Name
HF
I/O
Pin Description
Output Half-full flag: Half-full status flag
DVal
Output Data valid: Active low data valid signal
PORTSZ [2:0]
VCC1
Input
Port word size select: Port word width select pins (common for read and write ports)
Core voltage supply 1: 1.8-V supply voltage
Power
Supply
VCC2
Power
Supply
Core voltage supply 2: 1.5-V supply voltage
VCCIO_R
VCCIO_W
Vref
Power
Supply
Supply for read port I/Os: Read port inputs and I/O supply
Supply for write port I/Os: Write port inputs and I/O supply
Reference voltage: Reference voltage (regardless of I/O standard used)
Power
Supply
Input
Reference
VSS
Ground Ground
Do not use: These pins need to be left floating or tied to Ground
DNU
–
Document Number: 001-53687 Rev. *G
Page 6 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Half-Full Flag
Architecture
The Half-Full (HF) flag goes LOW when half of the memory array
is written. The assertion of HF is synchronized to WCLK.
The CYFX144VXXX, CYFX072VXXX, CYFX036VXXX, and
CYFX018VXXX are of memory arrays of 144 Mbit, 72 Mbit,
36 Mbit, and 18 Mbit respectively. The memory organization is
user configurable and word sizes can be selected as x9, x12,
x16, x18, x20, x24, x32, or x36. The logic blocks to implement
FIFO functionality and the associated features are built around
these memory arrays.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, that is, it is
exclusively updated by each rising edge of RCLK.
The input and output data buses have a width of 36 bits. The
input data bus goes to an input register and the data flow from
the input register to the memory is controlled by the write logic
block. The inputs to the write logic block are WCLK, WEN, IE,
and WQSEL. When the writes are enabled through WEN and if
the inputs are enabled by IE, then the data on the input bus is
written into the memory array at the rising edge of WCLK. This
also increments the write pointer. Enabling writes but disabling
the data input pins through IE only increments the write pointer
without doing any writes or altering the contents of the location.
In a multi-queue operating mode, the WQSEL selects the queue
in which the write should occur.
Programmable Almost-Empty and Almost-Full Flags
The CYFX072VXXX includes programmable Almost-Empty and
Almost-Full flags. Each flag is programmed (see Programming
Flag Offsets and Configuration Registers on page 9) a specific
distance from the corresponding boundary flags (Empty or Full).
When the FIFO contains the number of words (or fewer) for
which the flags are programmed, the PAF or PAE is asserted,
signifying that the FIFO is either almost-full or almost-empty. The
PAF flag signal transition is caused by the rising edge of the write
clock and the PAE flag transition is caused by the rising edge of
the read clock.
Similarly, the output register is connected to the data output bus.
Transfer of contents from the memory to the output register is
controlled by the read control logic. The inputs to the read control
logic include RCLK, REN, OE, RQSEL, and MARK. When reads
are enabled by REN and outputs are enabled through OE, the
data from the memory pointed by the read pointer is transferred
to the output data bus at the rising edge of RCLK along with
active low DVal. If the outputs are disabled but the reads
enabled, the outputs are in high impedance state, but internally
the read pointer is incremented. In a multi-queue operating
mode, the RQSEL selects the queue from which the read occurs.
Retransmit from Mark Operation
The retransmit feature is useful for transferring packets of data.
It enables the receipt of data to be acknowledged by the receiver
and retransmitted if necessary. The retransmit feature is used
when the number of writes equal to or less than the depth of the
FIFO has occurred – and at least one word has been read since
the last reset cycle. A HIGH pulse on RT resets the internal read
pointer to a physical location of the FIFO that is marked by the
user (using the MARK pin). With every valid read cycle after
retransmit, previously accessed data is read and the read pointer
is incremented until it is equal to the write pointer. Flags are
governed by the relative locations of the read and write pointers
and are updated during a retransmit cycle. Data written to FIFO
after activation of RT are also transmitted. The full depth of the
FIFO can be repeatedly retransmitted.
The MARK signal is used to ‘mark’ the location from which data
is retransmitted when requested.
Reset Logic
The FIFO can be reset in two ways: Master Reset (MRS) and
Partial Reset (PRS). The MRS initializes the read and write
pointers to zero and sets the output register to all zeroes. It also
resets the configuration registers to their default values. The
word size is configured through pins; values of the PORTSZ pins
are latched during MRS. A Master Reset is required after
power-up before accessing the FIFO. The PRS resets only the
read and write pointer to the first location and does not affect the
programmed configuration registers.
To mark a location, the Mark pin is asserted when reading that
particular location.
Mailbox Register
This is used to transfer data from the inputs to the outputs
directly, bypassing the FIFO sequence. A write operation when
the Mailbox (MB) signal is asserted writes the data in the mailbox
register. A read operation when the MB is asserted reads the
contents from the mailbox register. The width of mailbox register
always corresponds to port size.
Flag Operation
This device provides five flag pins to indicate the condition of the
FIFO contents.
Full Flag
The Full Flag (FF) goes LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, that is, it is
exclusively updated by each rising edge of WCLK.
Document Number: 001-53687 Rev. *G
Page 7 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Selecting Word Sizes
Write Mask and Read Skip Operation
The word sizes are configured based on the logic levels on the
PORTSZ pins during the master reset (MRS) cycle only (latched
on low to high edge). The port size cannot be changed during
normal mode of operation and these pins are ignored. If word
size is less than x36, the unused output pins are tri-stated by the
device.
As mentioned in Architecture on page 7, enabling writes but
disabling the inputs (IE HIGH) increments the write pointer
without doing any write operations or altering the contents of the
location.
This feature is called Write Mask and allows you to move the
write pointer without actually writing to the locations. This “write
masking” ability is useful in some video applications such as
Picture In Picture (PIP).
Data Valid Signal (DVal)
Data valid (DVal) is an active low signal and is provided for easy
capture of output data to the user. When a read operation is
performed, the DVal signal goes low along with output data. This
helps you to capture the data without keeping track of REN to
data output latency. This signal also helps when write and read
operations are performed continuously at different frequencies
by indicating when valid data is read out at the output port Q.
Similarly, during a read operation, if the outputs are disabled by
having the OE high, the read data does not appear on the output
bus; however, the read pointer is incremented.
Multi-Queue Operation
By default, the FIFO is sequenced considering the complete
memory as a single block. It is also possible to divide the whole
array into smaller parts, and each part can be independently
accessed with a FIFO sequence. This is like having a number of
independent queues inside the FIFO instead of the FIFO acting
as one big queue. You can configure the number of queues.
Power Up
The device becomes functional after VCC1, VCC2, VCCIO_R/W
,
and Vref attain minimum stable voltage required as given in
Recommended DC Operating Conditions on page 13. The
device can be accessed TPU time after these supplies attain the
minimum required level (see Switching Characteristics on page
15).
If the number of queues is less than 8, the controls for deciding
the queue number to read from or write to will be through three
pins each for input and output (RQSEL[2:0] and WQSEL[2:0]).
The queue to be accessed during a read or a write is decided by
the states of these pins during the operation (see Table 2).
However, if a larger number of queues are required to be
implemented (more than 8), it has to be set in the configuration
registers; the queue to be accessed is decided by the values
written into the configuration registers.
Table 1. Word Size Selection
PORTSZ[2:0]
Word Size
×9
000
001
010
011
100
101
110
111
×12
The number of queues is configured based on the value in the
configuration register 3 (refer to Table 4 on page 10). The
maximum number of queues into which the FIFO can be divided
is 128. Setting bit 7 (Enable Queue Registers) of the register 3
to “1” enables registers 1 and 2, which, in turn, determine the
queue to be written to or read from. In this mode, the pins RQSEL
and WQSEL are disabled. Setting bit 7 of the register 3 to “0”,
however, disables the registers 1 and 2. The queue is selected
based on the logic levels on the WQSEL and RQSEL pins during
read and write operation.
×16
×18
×20
×24
×32
×36
When RQSEL is changed, valid data is read after a latency as
defined in Table 3 on page 9 and Table 11 on page 14; the latency
is different across parts, depending on number of queues
supported. For WQSEL, the first write can be performed on the
next WCLK cycle.
Table 2. Multi-Queue Configuration
RQSEL[2:0]/WQSEL[2:0]
Queue Number Selected
000
001
010
011
100
101
110
111
1
2
3
4
5
6
7
8
Document Number: 001-53687 Rev. *G
Page 8 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Programming Flag Offsets and Configuration
Registers
Table 3. Latencies for Queue Change Operation (for 2-queue
part only - CYF1XXXVXXX - 100BGXI)
The CYFX072VXXX has 10 8-bit user configurable registers.
These registers contain the almost-full offset (M) and
almost-empty (N) values which decide when the PAF and PAE
flags are flagged, and device configuration such as the queue
number for the multi-queue operation.
For 2-Queue Part[1]
Latencies
Queue-to-Queue change for
RQSEL
0[2]
RQSEL change to data valid
LREN_TO_DATA (REN to data
valid) for all parts
These registers can be programmed into the FIFO in one of two
ways: using either the serial or parallel loading method. The
loading method is selected using the SPI_SEN (Serial Enable)
pin. A low on the SPI_SEN selects the serial method for writing
into the registers. For serial programming, there is a separate
SCLK and a Serial Input (SI). In parallel mode, a low on the load
(LD) pin causes the write and read operation to these registers.
The write and read operation happens from the first location
(0x1) to the last location (0xA) in a sequence. If LD is high, the
writes occur to the FIFO.
(see Table 11 on page 14 for
spec numbers)[3]
Queue-to-Queue change for
WQSEL
Even number of data writes
(minimum of 2)[4]
*
.
In addition to loading register values into the FIFO, it is also
possible to read the current register values. Register values can
be read through the parallel output port regardless of the
programming mode selected (serial or parallel). Register values
cannot be read serially. The registers may be programmed (and
reprogrammed) any time after master reset, regardless of
whether serial or parallel programming is selected.
See Table 5 on page 10 and Table 6 on page 11 for access to
configuration registers in serial and parallel modes.
The read and write operations loop back when they reach the
maximum address location of the configuration registers.
Simultaneous read and write operations should be avoided on
the configuration registers.
Notes
1. For multi-queue parts having more than two queues, see the individual device datasheets.
2. The RQSEL can be changed for every clock cycle.
3. After changing the RQSEL, the valid data is available after REN to data valid latency.
4. The WQSEL can be changed after writing even number of locations in the current queue (minimum of 2).
Document Number: 001-53687 Rev. *G
Page 9 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Table 4. Configuration Registers
ADDR Configuration Register
Default
0x00
Bit [7] Bit [6] Bit [5] Bit [4]
Bit [3] Bit [2] Bit [1] Bit [0]
0x1 Read Queue Number Select
0x2 Write Queue Number Select
0x3 Number of Queues
X
X
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
0x00
0x00
Enable
queue
registers
0x4 Almost-Empty Flag generation 0x7F
address - (LSB) (N)
D7
D6
X
D5
X
D4
X
D3
X
D2
X
D1
D9
D0
D8
0x5 Almost-Empty Flag generation 0x00
address - (MSB) (N)
X
0x6 Reserved
X
X
X
X
X
X
X
X
X
0x7 Almost-Full Flag generation
address - (LSB) (M)
0x7F
D7
D6
D5
D4
D3
D2
D1
D0
0x8 Almost-Full Flag generation
address - (MSB) (M)
0x00
X
X
X
X
X
X
D9
D8
0x9 Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0xA Fast CLK Bit Register
1XXXXXXXb Fast CLK
bit
Table 5. Writing and Reading Configuration Registers in Parallel Mode
SPI_SEN
LD
WEN REN
WCLK
RCLK
SPI_SCLK
Operation
1
0
0
1
↑ First rising edge
because both LD and
REN are low
X
X
Parallel write to first register
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
↑ Second rising edge
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Parallel write to second register
↑ Third rising edge
Parallel write to third register
↑ Fourth rising edge
Parallel write to fourth register
•
•
•
•
•
•
↑ Tenth rising edge
↑ Eleventh rising edge
Parallel write to tenth register
Parallel write to first register
(roll back)
1
1
0
0
1
1
0
0
X
X
↑Firstrisingedgesince
both LD and REN are
low
X
X
Parallel read from first register
↑ Second rising edge
Parallel read from second
register
1
1
0
0
1
1
0
0
X
X
↑ Third rising edge
↑ Fourth rising edge
X
X
Parallel read from third register
Parallel read from fourth
register
1
1
1
0
0
0
1
1
1
0
0
0
X
X
X
•
•
•
X
X
X
•
•
•
Document Number: 001-53687 Rev. *G
Page 10 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Table 5. Writing and Reading Configuration Registers in Parallel Mode (continued)
SPI_SEN
LD
WEN REN
WCLK
RCLK
SPI_SCLK
Operation
1
0
1
0
X
↑ Tenth rising edge
X
Parallel read from tenth
register
1
0
1
0
X
↑ Eleventh rising edge
X
Parallel read from first register
(roll back)
1
X
X
0
X
1
1
0
1
0
1
X
0
1
X
X
X
X
X
X
No operation
↑ Rising edge
X
Write to FIFO memory
Read from FIFO memory
Illegal operation
X
X
X
X
↑ Rising edge
X
Table 6. Writing into Configuration Registers in Serial Mode
SPI_SEN
LD
WEN
REN
WCLK
RCLK
SCLK
Operation
0
1
X
X
X
X
EachrisingoftheSCLKclocks
in one bit from the SI (Serial
In). Any of the 10 registers can
be addressed and written to,
following the SPI protocol.
↑ Rising edge
X
X
1
1
0
X
0
X
X
X
Parallel write to FIFO memory.
↑ Rising edge
X
X
Parallel read from FIFO
memory.
↑ Rising edge
1
0
1
1
X
X
X
This corresponds to parallel
mode (refer to Table 5).
Figure 2. Serial WRITE to Configuration Register
Width Expansion Configuration
The width of CYFX072VXXX can be expanded to provide word widths greater than 36 bits. During width expansion mode, all control
line inputs are common and all flags are available. Empty (Full) flags are created by ANDing the Empty (Full) flags of every FIFO; the
PAE and PAF flags can be detected from any one device. This technique avoids reading data from or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew between RCLK and WCLK.
Figure 3 on page 12 demonstrates a 72 bit-word width by using two 36-bit word CYFX072VXXXs.
Document Number: 001-53687 Rev. *G
Page 11 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Figure 3. Using Two CYFX072VXXXs for Width Expansion
DATAIN (D)
72
36
36
READCLOCK(RCLK)
READENABLE(REN)
OUTPUT ENABLE(OE)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
PAF
CYFX072VXXX
CYFX072VXXX
PAE
HF
EF
DATAOUT (Q)
EF
FF
FF
EF
36
72
FF
36
■ The clock frequency for both clocks should be between the
minimum and maximum range given in Table 9 on page 13.
Memory Organization for Different Port Sizes
The 72-Mbit memory has different organization for different port
sizes. Table 7 shows the depth of the FIFO for all port sizes.
The device uses internal PLL to achieve high performance.
Whenever there is change in the frequency of the clock, the
device takes TPLL time to synchronize with the input clock. (see
Switching Characteristics on page 15). The PLL requires
re-synchronization when there is change in the frequency of
either WCLK or RCLK or when master reset is asserted.
Note that for all port sizes, four locations are not available for
writing the data and are used to safeguard against false
synchronization of empty and full flags.
Table 7. Word Size Selection
For proper FIFO operation, the device must determine which of
the input clocks – RCLK or WCLK – is faster. This is evaluated
by using counters after the MRS cycle. The device uses two
10-bit counters inside (one running on RCLK and other on
WCLK), which count 1,024 cycles of read and write clock after
MRS. The clock of the counter which reaches its terminal count
first is used as master clock inside the FIFO.
PORTSZ[2:0]
Word Size
x9
FIFO Depth
8 Meg
Memory Size
72 Mbit
48 Mbit
64 Mbit
72 Mbit
40 Mbit
48 Mbit
64 Mbit
72 Mbit
000
001
010
011
100
101
110
111
x12
4 Meg
x16
4 Meg
x18
4 Meg
x20
2 Meg
When there is change in the relative frequency of RCLK and
WCLK during normal operation of FIFO, you can specify it by
using “Fast CLK bit” in the configuration register (0xA).
x24
2 Meg
x32
2 Meg
x36
2 Meg
“1” - indicates freq (WCLK) > freq (RCLK)
“0” - indicates freq (WCLK) < freq (RCLK)
Read/Write Clock Requirements
The result of counter evaluated frequency is available in this
register bit. You can override the counter evaluated frequency for
faster clock by changing this bit.
The read and write clocks must satisfy the following
requirements:
■ Both read (RCLK) and write (WCLK) clocks should be
free-running.
Whenever there is a change in this bit value, you must wait TPLL
time before issuing the next read or write to FIFO.
Device Specific Functionality Table
Functions
Write mask
Partial reset
CYF0XXXVXXX-150
CYF0XXXVXXX-133
CYF0XXXVXXX-110 CYF1XXXVXXX-100
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
No
PAE, PAF, HF
Document Number: 001-53687 Rev. *G
Page 12 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Voltage applied to I/O pins ...........................–0.3 V to 3.75 V
Output current into outputs (LOW) .............................. 20 mA
Storage temperature (without bias) ............ –65 °C to +150 °C
Static discharge voltage........................................... > 2001 V
(per MIL–STD–883, Method 3015)
Ambient temperature with
power applied
–55 °C to +125 °C
Operating Range
Core supply voltage 1 (VCC 1) to
ground potential.................................................–0.5 V to 2.5 V
Range
Commercial
Industrial
Ambient Temperature
0 °C to +70 °C
Core supply voltage 2 (VCC 2) to
ground potential...............................................–0.3 V to 1.65 V
–40 °C to +85 °C
I/O port supply voltage (VCCIO_R, VCCIO_W
)
–0.3 V to 3.7 V
Table 8. Recommended DC Operating Conditions
Parameter Description
VCC1
Min
Typ
1.80
1.5
Max
1.90
Unit
Core supply voltage 1
Core supply voltage 2
1.70
1.425
0.68
V
V
V
V
V
V
V
V
VCC2
Vref
1.575
0.95
Reference voltage (irrespective of I/O standard used)
I/O supply voltage, read and write LVCMOS33
0.75
3.30
2.50
1.8
VCCIO_R
VCCIO_W
3.00
3.60
banks.
LVCMOS25
2.30
2.70
LVCMOS18
LVCMOS15
HSTL1/2
1.70
1.90
1.425
1.425
1.5
1.575
1.575
1.5
Table 9. Electrical Characteristics
Parameter Description
Icc Active current
Conditions
Density
Min
–
Typ
Max
480
150
Unit
mA
VCC1=VCC1MAX
VCC2=VCC2MAX
,
18/36/72M
–
–
,
–
mA
All I/O switching,
150 MHz)
VCCIO_R/W = VCCIO_R/WMAX
–
–
50
mA
(All outputs disabled)
Icc
Active current
VCC1=VCC1MAX
VCC2=VCC2MAX
,
,
18/36/72M
–
–
–
–
480
150
mA
mA
All I/O switching,
110 MHz,)
VCCIO_R/W = VCCIO_R/WMAX
–
–
50
mA
(All outputs disabled)
II
Input pin leakage current VIN = VCCIOmax to 0 V
I/O pin leakage current VO = VCCIOmax to 0 V
–
–
–
–15
–15
–
–
–
6
15
15
–
µA
µA
pF
IOZ
CPIO
I/O capacitance
–
Document Number: 001-53687 Rev. *G
Page 13 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Table 10. I/O Characteristics
Nominal
I/O standard I/O supply
voltage
Input Voltage (V)
Output voltage (V)
Output Current (mA)
VIL(max)
VIH(min)
VOL(max)
VOH(min)
IOL(max)
IOH(max)
LVCMOS33
LVCMOS25
LVCMOS18
3.3 V
2.5 V
1.8 V
0.80
0.70
2.00
1.70
0.40
0.70
0.45
2.40
1.70
24
24
16
24
24
16
35%
VCCIO_R/W
65% VCCIO_R/W
VCCIO_R/W – 0.45
LVCMOS15
1.5 V
30%
VCCIO_R/W
70% VCCIO_R/W 25% VCCIO_R/W 75% VCCIO_R/W
12
12
HSTL1
HSTL2
1.5 V
1.5 V
Vref – 0.1
Vref – 0.1
Vref + 0.1
Vref + 0.1
0.40
0.40
VCCIO_R/W – 0.40
CCIO_R/W – 0.40
8
8
V
15
15
Table 11. Latency Table
Latency Parameter
Part No.
Latency
Detail
CYF0XXXVXXX - 150BGXI
CYF0XXXVXXX - 110BGXI
LIN - initial latency
26
9
Initial latency for data read after FIFO goes empty
Initial latency for data read after FIFO goes empty
CYF0XXXVXXX - 133BGXI
CYF1XXXVXXX - 133BGXI
LIN - initial latency
Latency when REN is asserted low to first data output from
FIFO
LREN_TO_DATA
All parts
All parts
5
Latency when REN is asserted along with LD to first data
read from configuration registers
LREN_TO_CONFIG
5
Latency from write port to read port when MB = 1 (at same
frequency)
LMAILBOX
LRT
All parts
All parts
3
19
Latency from RT going low to first new read data
Document Number: 001-53687 Rev. *G
Page 14 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Switching Characteristics
-110
-150
Parameter
Description
Unit
Min
–
Max
2
Min
–
Max
2
tPU
tS
Power-up time after all supplies reach minimum value
ms
MHz
MHz
MHz
MHz
MHz
ns
Clock cycle frequency
Clock cycle frequency
Clock cycle frequency
Clock cycle frequency
Clock cycle frequency
Data access time
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.5 V HSTL
24
24
24
24
24
3
110
110
110
110
110
8
24
24
24
24
24
3
150
150
150
130
150
8
tS
tS
tS
tS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tQS
tQH
tENS
tENH
tRS
tRSF
tPRT
Clock cycle time
9.09
4.35
4.35
3
41.67
–
6.6
3.15
3.15
3
41.67
–
ns
Clock high time
ns
Clock low time
–
–
ns
Data setup time
–
–
ns
Data hold time
3
–
3
–
ns
RQSEL and WQSEL setup time
RQSEL and WQSEL hold time
Enable setup time
3
–
3
–
ns
3
–
3
–
ns
3
–
3
–
ns
Enable hold time
3
–
3
–
ns
Reset pulse width
100
–
–
100
–
–
ns
Reset to flag output time
Retransmit pulse width
50
–
50
–
ns
5
5
RCLK
cycles
tOLZ
tOE
Output enable to output in Low Z
Output enable to output valid
Output enable to output in High Z
Write clock to FF
4
–
–
–
–
–
–
–
–
15
15
15
8
4
–
–
–
–
–
–
–
–
15
15
15
8
ns
ns
ns
ns
ns
ns
ns
ns
ms
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
Read clock to EF
8
8
Clock to PAF flag
14
14
14
6
14
14
14
6
Clock to PAE flag
Clock to HF flag
tPLL
Time required to synchronize PLL
Document Number: 001-53687 Rev. *G
Page 15 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Switching Waveforms
Figure 4. Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D
[35:0]
t
ENH
t
ENS
WEN, IE
NO OPERATION
Figure 5. Read Cycle Timing
t
CLK
RCLK
REN
t
t
ENH
ENS
NO OPERATION
LREN_TO_DATA cycles
t
A
VALID DATA
Q
[35:0]
t
OLZ
t
OHZ
OE
DVal
Document Number: 001-53687 Rev. *G
Page 16 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Switching Waveforms (continued)
Figure 6. Write Queue Selection
tQS
WCLK
WQSEL [2:0]
WEN
Data Valid
D [35:0]
Figure 7. Reset Timing
t
RS
MRS
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
HF
OE=1
OE=0
Q
[3–5:0]
Document Number: 001-53687 Rev. *G
Page 17 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Switching Waveforms (continued)
Figure 8. Empty Flag Timing
RCLK
t
REF
EF
REN
OE
Q
Qout
Qout-Last
Invalid Data
Qout
Qout-Last-1
[35:0]
Dval
Figure 9. Full Flag Timing
WCLK
t
DS
D0 (written)
D3 (not written)
D4 (not written)
D1 (written)
D2 (not written)
t
WFF
FF
WEN
Figure 10. Half-Full Timing
t
t
CLKL
CLKH
WCLK
t
t
ENH
ENS
WEN
HF
t
HF
HALF-FULL + 1
OR MORE
HALF-FULL OR LESS
Document Number: 001-53687 Rev. *G
Page 18 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Switching Waveforms (continued)
Figure 11. Programmable Almost-Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
PAE
t
t
ENH
ENS
N +
1
WORDS
IN FIFO
t
PAE
N is the offset in config register for PAE
Figure 12. Programmable Almost-Full Flag Timing
t
t
CLKL
CLKH
WCLK
t
t
ENH
ENS
WEN
PAF
t
PAF
FULL – M WORDS
IN FIFO
M is the offset in config register for PAE
Document Number: 001-53687 Rev. *G
Page 19 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Figure 13. Initial Data Latency
n
L
IN
1
2
WCLK
/RCLK
D0-D35
D
D
D
D
D
WEN/REN
OE
Q0
Q1
Q0-Q35
DVAL
L
(initial latency)
IN
Figure 14. Mailbox Operation
WCLK
/RCLK
D0-D35
D0
D3
D4
D1
D2
WEN/REN
LMAILBOX
MB
tA
Q0 = D0
Q1 = D1
Q0-Q35
Q3 = D2
Figure 15. Configuration Register Read
WCLK
/RCLK
REN
LRENB_TO_CONFIG
LD
Q0-Q35
Reg - 1
Document Number: 001-53687 Rev. *G
Page 20 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Ordering Information
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
150 CYF0018V33L-150BGXI
CYF0036V33L-150BGXI
51-85167 209-ball fine-pitch ball grid array (FPBGA) (14 × 22 × 1.76 mm) Industrial
CYF0072V18L-150BGXI
CYF0072V25L-150BGXI
CYF0072V33L-150BGXI
110 CYF0072V33L-110BGXI
100 CYF0144V18L-100BGXI
* Contact your local sales representative for availability of these parts.
Ordering Code Definition
CY F X XXX VXX X - XXX BGXI
Speed:
100 MHz
110 MHz
133 MHz
150 MHz
I/O Standard:
L = LVCMOS
H = HSTL (1.5 V)
I/O Voltage:
15 = 1.5 V
18 = 1.8V
25 = 2.5 V
33 = 3.3 V
Density:
018 = 18M
036 = 36M
072 = 72M
144 = 144M
0 - single-queue
1 - multi-queue (2 queues)
2 - multi-queue (8 queues*)
3 - multi-queue (128 queues*)
FIFO
Cypress
Document Number: 001-53687 Rev. *G
Page 21 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Package Diagram
Figure 16. 209-Ball FBGA (14 × 22 × 1.76 mm), 51-85167
51-85167 *A
Document Number: 001-53687 Rev. *G
Page 22 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Acronyms
Document Conventions
Units of Measure
Acronym
FF
Description
Full flag
Symbol
°C
Unit of Measure
degrees Celsius
FIFO
HF
First in first out
Half full
μA
microampere
milliampere
millisecond
megahertz
nanosecond
ohm
mA
ms
MHz
ns
HSTL
IE
High-speed transceiver logic
Input enable
I/O
Input/output
FPBGA
JTAG
LVCMOS
fine-pitch ball grid array
Joint test action group
Ω
pF
pico Farad
volt
Low voltage complementary metal oxide
semiconductor
V
W
watt
MB
Mailbox
MRS
OE
Master reset
Output enable
Programmable almost-full
Programmable almost-empty
Partial reset
PAF
PAE
PRS
RCLK
REN
RCLK
RQSEL
SCLK
TDI
Read clock
Read enable
Read clock
Read queue select
Serial clock
Test data in
TDO
TCK
Test data out
Test clock
TMS
WCLK
WEN
Test mode select
Write clock
Write enable
Document Number: 001-53687 Rev. *G
Page 23 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Document History Page
Document Title: CYFX018VXXX/CYFX036VXXX/CYFX072VXXX/CYFX144VXXX, 18/36/72/144 Mbit Programmable FIFOs
Document Number: 001-53687
Orig. of Submission
Rev.
**
ECN No.
Change
Date
Description of Change
2711566 VKN/PYRS
05/27/09 New data sheet
*A
2725088
2839536
NXR
NXR
06/26/2009 Included pinout, AC and DC specs, timing diagrams and package diagram
*B
01/28/2010 Changed Balls B5, D5, F6, K1, K2, K4, K8 and U2 from NC to DNU,
Balls C5, C7, G6, H6, J6, L6, M6, N6, T5, T7 FROM NC to VCC1,
Balls K9, K10, K11 From NC to VCCIOR
Ball W9 from NC to Vref in pin configuration table
Swapped Voltage range of VSS1 and VSS
2
Updated ICC spec
Removed TSKEW parameter
Added Ordering Information table
Added Part Numbering Nomenclature.
Changed title to
CYFX018VXXX/CYFX036VXXX/CYFX072VXXX/CYFX144VXXX,
18/36/72/144 Mbit Programmable FIFOs.
*C
*D
2884377
2963225
HKV
02/25/2010 Post to external web.
AJU/HPV 06/28/2010 Changed frequency of operation from 250 MHz to 150 MHz
Removed Depth Expansion feature and changed associated pin functionality
Removed Independent Port size selectability feature
Added Data Valid (DVal) signal feature
Updated Logic Block Diagram to reflect above changes.
Pinout changes:
Balls V5, V8, A7, B7, D7, and C6 renamed DNU
Ball U1 changed from RXO to DVal
Ball V2 changed from WXO/HF to HF
Ball A5, A6, B6 changed from WPORTSZ to PORTSZ
Ball A9 changed from RT/FL to RT
Renamed pwr as POWER, gnd as GND
Added Table 3
Table 6 – LD changed to ‘1’ for serial writes
Updated Electrical Characteristics and I/O Characteristics
Switching Characteristics Table:
Renamed tPC as tPU
Min frequency changed from 110MH to 24MHz
Changed tCLKH and tCLKL to 3.15 ns
Changed All setup and hold times to 3 ns
Changed tRSF to 50 ns
Removed tRSR
Changed All clock-to-flag timing to min=8 ns and max=14 ns
T
PLL changed to 6 ms
Changed all OE-related parameters to 15 ns
Scaled ICC for reduced frequency
Updated all waveforms
Added the following tables:
Word Size Selection, Device Specific Functionality Table, and Latency Table
Added Acronyms.
*E
*F
2994379
3101023
AJU
07/26/2010 Updated Ordering Information
SIVS
12/03/2010 Added supply-wise current consumption data in Electrical Characteristics.
Changed initial latency LIN from 34 to 26 and added initial latency LIN for
110 MHz part in Latency Table.
Added 110 MHz part information in Device Specific Functionality Table
Added details for the 110 MHz part in Switching Characteristics.
Added details for the 110 MHz part in Ordering Information.
*G
3129722
HKV
01/06/2011 Post to external web.
Document Number: 001-53687 Rev. *G
Page 24 of 25
PRELIMINARY
CYFX018VXXX, CYFX036VXXX
CYFX072VXXX, CYFX144VXXX
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
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psoc.cypress.com/solutions
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Lighting & Power Control
Memory
cypress.com/go/memory
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Wireless/RF
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53687 Rev. *G
Revised January 6, 2011
Page 25 of 25
All product and company names mentioned in this document are the trademarks of their respective holders.
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