CYF1018V_技术文档

CYF1018V, CYF1036V

CYF1072V

18/36/72-Mbit Programmable

2-Queue FIFOs

18/36/72-Mbit Programmable 2-Queue FIFOs

Features

Functional Description

■ Memory organization

❐ Industry’s largest first in first out (FIFO) memory densities:

18-Mbit, 36-Mbit, 72-Mbit

❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20,

× 24, × 32, × 36

The Cypress programmable FIFO family offers the industry’s

highest-density programmable FIFO memory device. It has

independent read and write ports, which can be clocked up to

100 MHz. User can configure input and output bus sizes. The

maximum bus size of 36 bits enables a maximum data

throughput of 3.6 Gbps. The read and write ports can support

multiple I/O voltage standards. The user-programmable

registers enable user to configure the device operation as

desired. The device also offers a simple and easy-to-use

interface to reduce implementation and debugging efforts,

improve time-to-market, and reduce engineering costs. This

makes it an ideal memory choice for a wide range of applications

including multiprocessor interfaces, video and image

processing, networking and telecommunications, high-speed

data acquisition, or any system that needs buffering at very high

speeds across different domains.

■ Up to 100-MHz clock operation

■ Unidirectional operation

■ Independent read and write ports

❐ Supports simultaneous read and write operations

❐ Reads and writes operate on independent clocks upto a

maximum clock ratio of 2, enabling data buffering across

clock domains

❐ Supports multiple I/O voltage standard: Low voltage

complementary metal oxide semiconductor (LVCMOS) 3.3 V

and 1.8 V voltage standards.

As implied by the name, the functionality of the FIFO is such that

the data is read out of the read port in the same sequence in

which it was written into the write port. The data is sequentially

written into the FIFO from the write port. If the writes and inputs

are enabled, the data on the write port gets written into the device

at the rising edge of the write clock. Enabling the reads and

outputs fetches data on the read port at every rising edge of the

read clock. Both reads and writes can occur simultaneously at

different speeds provided the ratio of read to write clock is

between 0.5 and 2. Appropriate flags are set whenever the FIFO

is empty or full.

■ output enable control for read skip operations

■ User configured two-Queue operating mode

■ Mark and retransmit: resets read pointer to user marked

position

■ Empty and full status flags

■ Flow-through mailbox register to send data from input to output

port, bypassing the FIFO sequence

■ Configure programmable flags and registers through serial or

parallel modes

The device also supports two-Queue operation, mark and

retransmit of data, and a flow-through mailbox register.

■ Separate serial clock (SCLK) input for serial programming

■ Master reset to clear entire FIFO

All product features and specs are common to all densities

(CYF1072V, CYF1036V, and CYF1018V) unless otherwise

specified. All descriptions are given assuming the device is

CYF1072V operated in × 36 mode. They hold good for other

densities (CYF1036V, and CYF1018V) and all port sizes × 9,

×12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.

the only difference will be in the input and output bus width.

Table 1 on page 8 shows the part of bus with valid data from

D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and

× 36 modes.

■ Joint test action group (JTAG) port provided for boundary scan

function

■ Industrial temperature range: –40 °C to +85 °C

Cypress Semiconductor Corporation

Document Number: 001-68321 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 12, 2011

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CYF1072V

Logic Block Diagram

Document Number: 001-68321 Rev. **

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CYF1018V, CYF1036V

CYF1072V

Contents

Pin Diagram for CYF1XXXV .............................................4

Pin Definitions ..................................................................5

Architecture ......................................................................7

Reset Logic .................................................................7

Flag Operation .............................................................7

Full Flag .......................................................................7

Empty Flag ..................................................................7

Retransmit from Mark Operation .................................7

Flow-through mailbox Register ....................................7

Selecting Word Sizes ..................................................8

Data Valid Signal .........................................................8

Power Up ...........................................................................8

Read Skip Operation ...................................................8

Multi-Queue Operation ................................................8

Width Expansion Configuration .................................10

Memory Organization for Different Port Sizes ...........11

Read/Write Clock Requirements ...............................11

JTAG operation .........................................................11

Maximum Ratings ...........................................................13

Operating Range .............................................................13

Recommended DC Operating Conditions ....................13

Electrical Characteristics ...............................................13

I/O Characteristics ..........................................................14

Latency Table ..................................................................14

Switching Characteristics ..............................................15

Switching Waveforms ....................................................16

Ordering Information ......................................................24

Ordering Code Definitions .........................................24

Package Diagram ............................................................25

Acronyms ........................................................................26

Document Conventions .................................................26

Units of Measure .......................................................26

Document History Page .................................................27

Sales, Solutions, and Legal Information ......................28

Worldwide Sales and Design Support .......................28

Products ....................................................................28

PSoC Solutions .........................................................28

Document Number: 001-68321 Rev. **

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Pin Diagram for CYF1XXXV

Figure 1. 209-ball FBGA (Top View)

1

2

3

4

5

6

PORTSZ1

PORTSZ2

DNU

7

DNU

8

RQSEL0

DNU

9

10

Q0

11

Q1

A

B

C

D

E

F

FF

D0

D1

WQSEL0 PORTSZ0

RT

EF

D2

D3

DNU

VCC1

VCC2

VSS

DNU

VCC1

DNU

REN

RCLK

VSS

Q2

Q3

D4

D5

WEN

VSS

VCC2

VSS

VCC2

VSS

VCC2

WCLK

VCC2

VSS

VCC2

VSS

VCC2

VSS

D30

VCC1

DNU

Q4

Q5

D6

D7

LD

VCC1

VCC2

VSS

Q6

Q7

D8

D9

VCCIO

VSS

VCCIO

DNU

VCCIO

VSS

VCC2

VSS

Q8

Q9

D10

D12

D14

D16

DNU

D18

D20

D22

D24

D26

D28

DVal0

DNU

TDO

D11

D13

D15

D17

DNU

D19

D21

D23

D25

D27

D29

DNU

DVal1

Q10

Q12

Q14

Q16

VCCIO

Q18

Q20

Q22

Q24

Q26

Q28

Q30

Q32

Q34

Q11

Q13

Q15

Q17

VCCIO

Q19

Q21

Q23

Q25

Q27

Q29

Q31

Q33

Q35

G

H

J

VCC2

VSS

VCCIO

VSS

VCC1

DNU

VCCIO

VSS

VCC2

VSS

VCC2

VSS

VCC2

DNU

VCC2

VSS

VCCIO

VSS

VCCIO

VSS

VCC2

DNU

VCC2

VCCIO

VCC2

VSS

K

L

VCCIO

VSS

VCC1

SPI_SEN

VCCIO

SPI_SI

DNU

VCCIO

VSS

VCC2

VSS

M

N

P

R

T

VCC2

VSS

VCCIO

VSS

VCCIO

VSS

VCC2

VSS

VCC2

VSS

VCC2

VCC1

D31

VCCIO

VCC1

DNU

VCCIO

VCC1

SPI_SCLK

MB

VCC2

VCC1

Vref

VCC2

VSS

U

V

W

OE

D32

D33

DNU

MRS

DNU

MARK

Vref

D34

D35

TDI

TRST

TMS

TCK

Document Number: 001-68321 Rev. **

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Pin Definitions

Pin Name

D[35:0]

I/O

Input

Output Data outputs: Data outputs for a 36-bit bus.

Pin Description

Data inputs: Data inputs for a 36-bit bus.

Q[35:0]

WEN

REN

OE

Input

Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers.

Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.

Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs

are in High Z (high impedance) state.

WCLK

RCLK

Input

Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and

into the configuration registers if LD is low.

Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is

high and from the configuration registers if LD is low.

DVal0

DVal1

EF

Output Data valid for Queue-0 : Active low signal indicating valid data read for Queue-0 from Q[35:0].

Output Data valid for Queue-1 : Active low signal indicating valid data read for Queue-1 from Q[35:0].

Output Empty flag: When EF is LOW, the Queue is empty. EF is synchronized to RCLK.

Output Full flag: When FF is LOW, the Queue is full. FF is synchronized to WCLK.

FF

LD

Input

Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When

LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO.

RT

Input

Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which

is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed

data is read and the read pointer is incremented until it is equal to the write pointer.

MRS

Input

Master reset: MRS initializes the read and write pointers to zero and sets the output register to all zeroes.

During Master Reset, the configuration registers are all set to default values and flags are reset.

SPI_SCLK

Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset

registers if SPI_SEN is enabled.

SPI_SI

SPI_SEN

MARK

Input

Serial input: Serial input when SPI_SEN is enabled.

Serial enable: Enables serial loading of programmable flag offsets and configuration registers.

Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any

subsequent retransmit operation resets the read pointer to this position.

MB

Input

Mailbox: When asserted the reads and writes happen to flow-through mailbox register.

Write Queue select: select Queue-0 when low and Queue-1 when high.

Read Queue select: select Queue-0 when low and Queue-1 when high.

Test clock (TCK) pin for JTAG.

WQSEL0

RQSEL0

TCK

TRST

TMS

Reset pin for JTAG.

Test mode select (TMS) pin for JTAG.

TDI

Test data in (TDI) pin for JTAG.

TDO

Output Test data out (TDO) for JTAG.

PORTSZ [2:0]

V_CC1

Input

Port word size select: Port word width select pins (common for read and write ports).

Power

Supply

Core voltage supply 1: 1.8 V supply voltage

V_CC2

Power

Supply

Core voltage supply 2: 1.5 V supply voltage

Document Number: 001-68321 Rev. **

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CYF1072V

Pin Definitions (continued)

Pin Name

V_CCIO

I/O

Pin Description

Power

Supply

Supply for I/Os.

Vref

Input

Reference

Reference voltage: Reference voltage (regardless of I/O standard used)

V_SS

Ground Ground

Do not use: These pins need to be left floating.

DNU

–

Document Number: 001-68321 Rev. **

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Flag Operation

Architecture

This device provides two flag pins to indicate the condition of the

FIFO contents.

The CYF1072V, CYF1036V, and CYF1018V are of memory

arrays of 72-Mbit, 36-Mbit, and 18-Mbit respectively. The

memory organization is user configurable and word sizes can be

selected as × 9, × 12, × 16, × 18, × 20, × 24, × 32, or × 36. The

logic blocks to implement FIFO functionality and the associated

features are built around these memory arrays.

Full Flag

The Full Flag (FF) goes LOW when the device is full. All write

operations are ignored whenever FF is LOW regardless of the

state of WEN. FF is synchronized to WCLK, that is, it is

exclusively updated by each rising edge of WCLK. In 2Q mode,

FF indicates the status of the Queue selected by WQSEL0.The

worst case assertion latency for Full Flag is four. As the user

cannot know that the FIFO is full for four clock cycles, it is

possible that user continues writing data during this time. In this

case, the four data word written will be stored to prevent data loss

and these words have to be read back in order for full flag to get

de-asserted. The minimum number of reads required to

de-assert full-flag is two and the maximum number of reads

required to de-assert full flag is six. The assertion and

de-assertion of full flag with associated latencies is explained in

Latency Table on page 14.

The input and output data buses have a maximum width of

36 bits configurable through PORTSZ[2:0]. The input data bus

goes to an input register and the data flow from the input register

to the memory is controlled by the write logic block. The inputs

to the write logic block are WCLK, WEN and WQSEL0. When the

writes are enabled through WEN, the data on the input bus is

written into the memory array at the rising edge of WCLK. This

also increments the write pointer. WQSEL0 selects the Queue

for write operation.

Similarly, the output register is connected to the data output bus.

Transfer of contents from the memory to the output register is

controlled by the read control logic. The inputs to the read control

logic include RCLK, REN, OE, RQSEL0, RT and MARK. When

reads are enabled by REN and outputs are enabled through OE,

the data from the memory pointed by the read pointer is

transferred to the output data bus at the rising edge of RCLK

along with active low Dval0 or Dval1 based on the Queue

number selected using RQSEL0. If the outputs are disabled

through OE but the reads enabled, the outputs are in high

impedance state, but internally the read pointer is incremented.

The MARK signal is used to ‘mark’ the location from which data

is retransmitted when requested.

Empty Flag

The Empty Flag (EF) goes LOW when the device is empty. Read

operations are ignored whenever EF is LOW, regardless of the

state of REN. EF is synchronized to RCLK, i.e., it is exclusively

updated by each rising edge of RCLK. In 2Q mode, EF indicates

the status of the Queue selected by RQSEL0. The assertion and

de-assertion of empty flag with associated latencies is explained

in Latency Table on page 14.

Retransmit from Mark Operation

During write operation, the number of writes performed is always

a even number (i.e., minimum write burst length is two and

number of writes always a multiple of two), whereas during read

operation, the number of reads performed can be even or odd

(i.e., minimum read burst length is one).

The retransmit feature is useful for transferring packets of data

repeatedly. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary. The retransmit

feature is used when the number of writes equal to or less than

the depth of the FIFO has occurred – and at least one word has

been read since the last reset cycle. A HIGH pulse on RT resets

the internal read pointer to a physical location of the FIFO that is

marked by the user (using the MARK pin). In 2-Queue mode the

MARK and RT signals are validated with RQSEL0, i.e., Mark or

Retransmit function will be performed for the Queue that is

selected by RQSEL0. With every valid read cycle after

retransmit, previously accessed data is read and the read pointer

is incremented until it is equal to the write pointer. Flags are

governed by the relative locations of the read and write pointers

and are updated during a retransmit cycle. Data written to FIFO

after activation of RT are also transmitted. The full depth of the

FIFO can be repeatedly retransmitted. To mark a location, the

Mark pin is asserted when reading that particular location.

By default, the FIFO is accessed as a single Queue device. It is

possible to divide the whole memory space into 2 equal sized

array, and each array can be independently accessed as an

independent FIFO. This is like having two independent Queues

inside the FIFO instead of entire memory space acting as single

Queue FIFO. User can configure the number of Queues by

setting the value of D0 of configuration register 3(refer Table 3

on page 9). Table 2 on page 8 shows the value to be set in D0 of

configuration register 3 to configure the device in single-Queue

or two-Queue mode.

Reset Logic

The Master Reset (MRS) initializes the read and write pointers

to zero, sets the output registers to all zeros and sets the status

of the flags to FF deasserted and EF asserted. MRS also resets

the configuration register and the mark address to their default

values. MRS affects all the Queues in the FIFO. A MRS is

required after power up before accessing the FIFO. After MRS,

a minimum latency of 1024 clocks is necessary before the first

access. The word size is configured through pins; values of the

three PORTSZ pins are latched during rising edge of MRS. After

MRS, the device is configured in single Queue mode by default.

Flow-through mailbox Register

This feature transfers data from input to output directly by

bypassing the FIFO sequence. When MB signal is asserted the

data present in D[35:0] will be available at Q[35:0] after two

WCLK cycles. Normal read and write operations are not allowed

during flow-through mailbox operation. Before starting

Flow-through mailbox operation FIFO read should be completed

to make data valid (DVal0/DVal1) high in order to avoid data loss

from FIFO. The width of flow-through mailbox register always

corresponds to port size.

Document Number: 001-68321 Rev. **

Page 7 of 28

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CYF1072V

valid data on Q bus for either Queue-0 or Queue-1. This helps to

capture the data without keeping track of REN and RQSEL0 to

data output latency. These signals also help to capture the output

data when write and read operations are performed continuously

at different frequencies by indicating when valid data is read out

at the output port Q[35:0].

Selecting Word Sizes

The word sizes are configured based on the logic levels on the

PORTSZ pins during the master reset (MRS) cycle only (latched

on low to high edge). The port size cannot be changed during

normal mode of operation and these pins are ignored. Table 1.

explains the pins of D[35:0] and Q[35:0] that will have valid data

in modes where the word size is less than × 36. If word size is

less than × 36, the unused output pins are tri-stated by the device

and unused input pins will be ignored by the internal logic. The

pins with valid data input D[N:0] and output Q[N:0] is given in

Table 1.

Power Up

The device becomes functional after V_CC1, V_CC2, V_CCIO, and

Vref attain minimum stable voltage required as given in

Recommended DC Operating Conditions on page 13. The

device can be accessed t_PUtime after these supplies attain the

minimum required level

Data Valid Signal

Data valid (Dval0, Dval1) are active low signals provided for easy

capture of output data. When a read operation is performed, the

DVal0/DVal1 signal goes low along with output data indicating

(see Switching Characteristics on page 15). There is no power

sequencing requirement for the device.

Table 1. Word Size Selection

PORTSZ[2:0]

Word Size

×9

Active input data pins D[X:0] Active output data pins Q[X:0]

000

001

010

011

100

101

110

111

D[8:0]

D[11:0]

D[15:0]

D[17:0]

D[19:0]

D[23:0]

D[31:0]

D[35:0]

Q[8:0]

Q[11:0]

Q[15:0]

Q[17:0]

Q[19:0]

Q[23:0]

Q[31:0]

Q[35:0]

×12

×16

×18

×20

×24

×32

×36

Table 2. Multi-Queue Configuration

operating mode

RQSEL0/WQSEL0

Queue Number Selected

1Q mode

register 0x3[0]=0

0

1

0

1

0

invalid

2Q mode

register 0x3[0]=1

0

1

In multi Queue mode , the entire memory space is divided into

equal sized memory array and each individual memory array can

be accessed as an independent FIFO based on additional

control signals. These independent memory arrays are called as

Queues. For example, when 72M device, is configured into two

Queue mode, the entire memory space of 72M is divided into two

36M memory array called as Queue-0 and Queue-1. These

Queues can be accessed independently as a FIFO by selecting

the Queue select signals WQSEL0 and RQSEL0. In this way, two

Queues can be created for a given device where data can be

stored independently and read out independently.

Read Skip Operation

As mentioned in Architecture on page 7, during a read operation,

if the outputs are disabled by having the OE high, the read data

does not appear on the output bus; however, the read pointer is

incremented.

Multi-Queue Operation

In general, the entire memory space is accessed as a First In

First Out (FIFO) order for the write and read operation. In this

case, the entire memory space is called a single Queue. For

example, for 72M device, the entire memory space is available

as a single Queue FIFO operation.

Document Number: 001-68321 Rev. **

Page 8 of 28

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CYF1072V

Table 3. Configuration Registers

ADDR Configuration Register

Default

0x00

Bit [7] Bit [6] Bit [5] Bit [4]

Bit [3] Bit [2] Bit [1] Bit [0]

0x1 Reserved

X

0x2 Reserved

0x00

0x7F

0x00

0x7F

0x00

0x3 Number of Queues

0x4 Reserved

D0

X

0x5 Reserved

X

0x6 Reserved

X

0x7 Reserved

X

0x8 Reserved

X

0x9 Reserved

X

0xA Fast CLK Bit Register

1XXXXXXXb Fast CLK

bit

X

Table 4. Writing and Reading Configuration Registers in Parallel Mode

SPI_SEN

LD

WEN REN

WCLK

RCLK

SPI_SCLK

Operation

1

0

1

 First rising edge

because both LD and

REN are low

X

Parallel write to first register

1

0

1

 Second rising edge

X

Parallel write to second register

 Third rising edge

Parallel write to third register

 Fourth rising edge

Parallel write to fourth register



 Tenth rising edge

 Eleventh rising edge

Parallel write to tenth register

Parallel write to first register

(roll back)

1

0

1

0

X

Firstrisingedgesince

both LD and REN are

low

X

Parallel read from first register

 Second rising edge

Parallel read from second

register

1

0

1

0

X

 Third rising edge

 Fourth rising edge

X

Parallel read from third register

Parallel read from fourth

register

1

0

1

0

X



X



 Tenth rising edge

Parallel read from tenth

register

1

0

1

0

X

 Eleventh rising edge

X

Parallel read from first register

(roll back)

1

X

1

0

1

X

No operation

X

 Rising edge

Write to FIFO memory

Document Number: 001-68321 Rev. **

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Table 4. Writing and Reading Configuration Registers in Parallel Mode (continued)

SPI_SEN

LD

1

WEN REN

WCLK

RCLK

 Rising edge

X

SPI_SCLK

Operation

Read from FIFO memory

Illegal operation

X

0

X

0

1

X

0

Table 5. Writing into Configuration Registers in Serial Mode

SPI_SEN

LD

WEN

REN

WCLK

RCLK

SCLK

Operation

0

1

X

EachrisingoftheSCLKclocks

in one bit from the SI (Serial

In). Any of the 10 registers can

be addressed and written to,

following the SPI protocol.

 Rising edge

X

1

0

X

0

X

Parallel write to FIFO memory.

 Rising edge

X

Parallel read from FIFO

memory.

 Rising edge

1

0

1

X

This corresponds to parallel

mode (refer to Table 4).

Figure 2. Serial WRITE to Configuration Register

This technique avoids reading data from or writing data to the

FIFO that is “staggered” by one clock cycle due to the variations

in skew between RCLK and WCLK. Figure 3 on page 11

demonstrates a 72 bit-word width by using two 36-bit word

CYF1072Vs.

Width Expansion Configuration

The width of CYF1072V can be expanded to provide word widths

greater than 36 bits. During width expansion mode, all control

line inputs are common and all flags are available. Empty (Full)

flags are created by ANDing the Empty (Full) flags of every FIFO.

Document Number: 001-68321 Rev. **

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CYF1072V

Figure 3. Using Two CYF1072V for Width Expansion

DATAIN (D)

72

36

READCLOCK(RCLK)

READENABLE(REN)

OUTPUT ENABLE(OE)

WRITE CLOCK(WCLK)

WRITE ENABLE(WEN)

CYF1072V

EF

FF

EF

DATAOUT (Q)

36

72

FF

36

■ The ratio of RCLK to WCLK must be in the range of 0.5 to 2.

Memory Organization for Different Port Sizes

The device uses internal PLL to achieve high performance.

Whenever there is change in the frequency of the clock, the

device takes t_PLLtime to synchronize with the input clock. (see

Switching Characteristics on page 15). The PLL requires

re-synchronization when there is change in the frequency of

either WCLK or RCLK or when master reset is asserted.

The 72-Mbit memory has different organization for different port

sizes. Table 6 shows the depth of the FIFO for all port sizes.

Note that for all port sizes, four to eight locations are not available

for writing the data and are used to safeguard against false

synchronization of empty and full flags.

Table 6. Word Size Selection

For proper FIFO operation, the device must determine which of

the input clocks – RCLK or WCLK – is faster. This is evaluated

by using counters after the MRS cycle. The device uses two

10-bit counters inside (one running on RCLK and other on

WCLK), which count 1,024 cycles of read and write clock after

MRS. The clock of the counter which reaches its terminal count

first is used as master clock inside the FIFO.

PORTSZ[2:0]

Word Size

× 9

FIFO Depth

8 Meg

Memory Size

72 Mbit

48 Mbit

64 Mbit

72 Mbit

40 Mbit

48 Mbit

64 Mbit

72 Mbit

000

001

010

011

100

101

110

111

× 12

4 Meg

× 16

4 Meg

× 18

4 Meg

When there is change in the relative frequency of RCLK and

WCLK during normal operation of FIFO, user can specify it by

using “Fast CLK bit” in the configuration register (0xA).

× 20

2 Meg

× 24

2 Meg

× 32

2 Meg

“1” - indicates f_req(WCLK) > f_req(RCLK)

“0” - indicates f_req(WCLK) < f_req(RCLK)

× 36

2 Meg

The memory size mentioned is when the device is configured in

single-Queue mode.

The result of counter evaluated frequency is available in this

register bit. User can override the counter evaluated frequency

for faster clock by changing this bit.

Read/Write Clock Requirements

Whenever there is a change in this bit value, user must wait t_PLL

time before issuing the next read or write to FIFO.

The read and write clocks must satisfy the following

requirements:

JTAG operation

■ Both read (RCLK) and write (WCLK) clocks should be

free-running.

CYF1072V has two devices connected internally in a JTAG chain

as shown in Figure 4 on page 12.

■ The clock frequency for both clocks should be between the

minimum and maximum range given in Switching

Characteristics on page 15.

Document Number: 001-68321 Rev. **

Page 11 of 28

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CYF1072V

Figure 4. JTAG Operation

Table 7 shows the IR register length and device ID .

Table 7. JTAG IDCODES

IR Register length

Device ID (HEX)

“Ignore”

Bypass register length

Device-1

Device-2

3

8

1

1E3261CF

For boundary scan, device-1 should be in bypass mode.

Table 8 and Table 9 shows the JTAG instruction set for devices 1 and 2.

Table 8. JTAG Instructions

Device-1

BYPASS

opcode (Binary)

111

Table 9. JTAG Instructions

Device-2

EXTEST

HIGHZ

SAMPLE/PRELOAD

BYPASS

IDCODE

opcode (HEX)

00

07

01

FF

0F

Document Number: 001-68321 Rev. **

Page 12 of 28

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CYF1018V, CYF1036V

CYF1072V

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

I/O port supply voltage (V_CCIO).......................–0.3 V to 3.7 V

Voltage applied to I/O pins............................–0.3 V to 3.75 V

Output current into outputs (LOW) .............................. 20 mA

Storage temperature (without bias) ......... –65 C to +150 C

Ambient temperature with

power applied .......................................... –55 C to +125 C

Static discharge voltage...........................................> 2001 V

(per MIL–STD–883, Method 3015)

Core supply voltage 1 (V_CC1) to

ground potential..............................................–0.3 V to 2.5 V

Operating Range

Core supply voltage 2 (V_CC2) to

ground potential............................................–0.3 V to 1.65 V

Range

Ambient Temperature

–40 C to +85 C

Industrial

Latch-up current .................................................. >100mA

Recommended DC Operating Conditions

Parameter

V_CC1

Description

Min

1.70

1.425

0.7

Typ

1.80

1.5

Max

1.90

1.575

0.8

Unit

Core supply voltage 1

Core supply voltage 2

V

V_CC2

Vref

Reference voltage (irrespective of I/O standard used)

I/O supply voltage, read and write LVCMOS33

0.75

3.30

1.8

V_CCIO

3.00

1.70

3.60

1.90

banks.

LVCMOS18

Electrical Characteristics

Parameter

I_cc

Description

Active current

Conditions

V_CC1= V_CC1MAX

_CC2= V_CC2MAX

Min

Typ

–

Max

Unit

mA

–

300

500

V

,

–

All I/O switching, 100 MHz

V_CCIO= V_CCIOMAX

–

100

mA

(All outputs disabled)

I_I

Input pin leakage current V_IN= V_CCIOmaxto 0 V

I/O pin leakage current V_O= V_CCIOmaxto 0 V

–15

–

15

16

µA

pF

I_OZ

C_P

Capacitance for TMS

and TCK

–

C_PIO

Capacitance for all I/Os

apart from TMS and TCK

–

8

pF

Document Number: 001-68321 Rev. **

Page 13 of 28

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CYF1018V, CYF1036V

CYF1072V

I/O Characteristics

Nominal

I/O standard I/O supply

voltage

Input Voltage (V)

V_IL(max) V_IH(min)

Output voltage (V)

Output Current (mA)

V_OL(max)

V_OH(min)

I_OL(max)

I_OH(max)

LVCMOS33

LVCMOS18

3.3 V

1.8 V

0.80

2.20

0.45

2.40

24

16

24

16

30% V_CCIO

65% V_CCIO

V_CCIO– 0.45

Latency Table

Latency Parameter

Number of cycles

Detail

Min = 0

L_{FF_ASSERT}

Max = 4

Last data write to FF going low

Last data read to EF going low

L_{EF_ASSERT}

0

1

2

4

L_{RQSEL_CHANGE}

L_{WQSEL_CHANGE}

L_MAILBOX

Minimum RCLK cycles before RQSEL0 can change

Minimum WCLK cycles before WQSEL0 can change

Latency from write port to read port when MB = 1 (w.r.t WCLK)

Latency when REN is asserted low to first data output from FIFO

L_{REN_TO_DATA}

Latency when REN is asserted along with LD to first data read from

configuration registers

L_{REN_TO_CONFIG}

L_{FF_DEASSERT}

L_{RT_TO_REN}

4

7

9

Read to FF going high

RT 5th cycle to REN going low for read

Min = 20

Max = 23

L_{RT_TO_DATA}

L_IN

RT 5th cycle to valid data on Q[35:0]

Min = 8

Max = 29

Initial latency for data read after FIFO goes empty during

simultaneous read/write

Min = 6

Max = 27

L_{EF_DEASSERT}

Write to EF going high

Figure 5. AC test load conditions

(a) V_CCIO= 1.8 Volt

(b) V_CCIO= 3.3 Volt

(c) All Input Pulses

Document Number: 001-68321 Rev. **

Page 14 of 28

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CYF1072V

Switching Characteristics

Over the operating Range

-100

Parameter

Description

Power-up time after all supplies reach minimum value

Unit

Max

Min

–

t_PU

2

100

10

41.67

–

ms

MHz

ns

t_S

Clock cycle frequency

Data access time

Clock cycle time

Clock high time

3.3 V LVCMOS

1.8 V LVCMOS

24

–

t_S

t_A

t_CLK

t_CLKH

t_CLKL

t_DS

10

4.5

3

ns

Clock low time

–

ns

Data setup time

Data hold time

–

ns

t_DH

3

–

ns

t_QS

RQSEL0 and WQSEL0 setup time

RQSEL0 and WQSEL0 hold time

Enable setup time

3

–

ns

t_QH

3

–

ns

t_ENS

t_ENH

t_{ENS_SI}

t_{ENH_SI}

t_{RATE_SPI}

t_RS

3

–

ns

Enable hold time

3

–

ns

setup time for SPI_SI and SPI_SEN pin

hold time for SPI_SI and SPI_SEN pin

frequency of SPI_SCLK

5

–

ns

5

–

ns

–

25

–

MHz

ns

Reset pulse width

100

25

–

t_PZS

t_PZH

t_RSF

t_PRT

Port size select to MRS seup time

MRS to port size select hold time

Reset to flag output time

–

ns

–

ns

50

–

ns

Retransmit pulse width

5

RCLK

cycles

t_OLZ

Output enable to output in Low Z

Output enable to output valid

Output enable to output in High Z

Write clock to FF

4

–

15

9

ns

t_OE

t_OHZ

–

ns

t_WFF

–

ns

t_REF

Read clock to EF

–

9

ns

t_PLL

Time required to synchronize PLL

JTAG TCK cycle time

–

1024

–

cycles

ns

t_{RATE_JTAG}

t_{S_JTAG}

t_{H_JTAG}

t_{CO_JTAG}

100

8

setup time for JTAG TMS,TDI

hold time for JTAG TMS,TDI

JTAG TCK low to TDO valid

–

ns

8

–

ns

–

20

ns

Document Number: 001-68321 Rev. **

Page 15 of 28

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CYF1072V

Switching Waveforms

Figure 6. Write Cycle Timing

t

CLK

t

CLKL

CLKH

WCLK

t

DH

DS

D[35:0]

t

ENH

t

ENS

WEN

NO OPERATION

Figure 7. Read Cycle Timing

t

CLK

RCLK

t

ENH

ENS

REN

NO OPERATION

L

REN_TO_DATA

t

A

VALID DATA

Q[35:0]

t

OLZ

t

OHZ

OE

DVal0 or Dval1

Figure 8. Reset Timing

t

RS

MRS

t

RSF

EF

FF

OE=1

OE=0

Q[35:0]

Document Number: 001-68321 Rev. **

Page 16 of 28

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CYF1018V, CYF1036V

CYF1072V

Switching Waveforms (continued)

Figure 9. MRS to PORTSZ [2:0]

WCLK/RCLK

MRS

t_PZS

t_PZH

PORTSZ[2:0]

Figure 10. Flow-through mailbox Operation

2

3

1

WCLK

D[35:0]

DO

D1

D2

D3

D4

REN / WEN

L _MAILBOX

MB

Q[35:0]

QO

Q1

Q2

Q3

Q4

DVal0/

DVal1

Document Number: 001-68321 Rev. **

Page 17 of 28

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CYF1072V

Figure 11. Configuration Register Write

WCLK

WEN

t_ENS

LD

t_DH

t_DS

D[35:0]

config-reg 0

config-reg 1

config-reg 2

config-reg 3

config-reg 4

config-reg 5

Figure 12. Configuration Register Read

WCLK

/RCLK

REN

L_{REN_TO_CONFIG}

LD

Q[35:0]

Reg - 1

Figure 13. WQSEL to FF

WCLK

WQSEL0

FF

FF for QUE-0

FF for QUE-1

t_QS

t_WFF

Document Number: 001-68321 Rev. **

Page 18 of 28

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CYF1072V

Figure 14. RQSEL0 to EF

1

2

3

4

5

RCLK

RQSEL0

EF

L _{REN_TO_DATA}

EF for QUE-1

EF for QUE-0

t_REF

t_QS

Figure 15. Write to Empty Flag De-assertion

WCLK

WEN

D[35:0]

EF

L_{EF_DEASSERT}

EF for QUE-0

RCLK

REN

WQSEL0/

RQSEL0

Document Number: 001-68321 Rev. **

Page 19 of 28

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CYF1018V, CYF1036V

CYF1072V

Figure 16. Read to Empty Flag Assertion

1

2

3

4

5

RCLK

REN

Q

LAST

Q[35:0]

DVal0

L_{REN_TO_DATA}

EF

EF for QUE-0

t_REF

WQSEL0/

RQSEL0

Figure 17. Full Flag Assertion

WCLK

WEN

D[35:0]

FF

NOT

D

0

D

1

D

x

D

LAST

NOT

WRITTEN

LAST-1

WRITTEN

FF for QUE-0

t_WFF

WQSEL0/

RQSEL0

Document Number: 001-68321 Rev. **

Page 20 of 28

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CYF1072V

Figure 18. Full Flag De-assertion

WCLK

WEN

D[35:0]

FF

D

LAST

LAST-4

LAST-3

LAST-2

LAST-1

L_{FF_DEASSERT}

RCLK

REN

WQSEL0/

RQSEL0

Figure 19. Switching between Queues - Write

WCLK

WEN

WQSEL0

D[35:0]

QUE-0

wdata - 0

QUE-0

wdata - 1

QUE-1

wdata - 0

QUE-1

wdata - 1

QUE-0

wdata - 2

QUE-0

wdata - 3

Document Number: 001-68321 Rev. **

Page 21 of 28

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CYF1072V

Figure 20. Switching between Queues - Read

1

2

3

4

5

RCLK

REN

L _{REN_TO_DATA}

RQSEL0

QUE-0

QUE-1

QUE-0

Q[35:0]

DVal0

DVal1

rdata - 0

rdata - 1

Figure 21. Simultaneous Write & Read QUE - 0

WCLK

WEN

D

0

D

1

D

2

D

3

D

N

D

N+1

D

N+2

D

N+3

D[35:0]

RCLK

L _IN

REN

Q

3

Q

0

Q

1

Q

2

Q[35:0]

DVal0

WQSEL0/

RQSEL0

Document Number: 001-68321 Rev. **

Page 22 of 28

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CYF1018V, CYF1036V

CYF1072V

Figure 22. Mark

RCLK

REN

MARK

RQSEL0

Q[35:0]

DVal0

Q (N+3)

Q (N+5)

Q (N-2)

Q (N-1)

Q (N)

Q (N+1)

Q (N+2)

Q (N+4)

Q (N+6)

DATA MARKED IN QUE-0

Figure 23. Retransmit

RCLK

REN

L_{RT_TO_REN}

t_PRT

L_{RT_TO_DATA}

RT

RQSEL0

Q (N+1)

Q (N)

Q[35:0]

DVal0

RETRANSMIT FROM

DATA MARKED IN QUE-0

Document Number: 001-68321 Rev. **

Page 23 of 28

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CYF1018V, CYF1036V

CYF1072V

Ordering Information

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Package Type

100 CYF1018V33L-100BGXI

CYF1036V33L-100BGXI

CYF1072V33L-100BGXI

CYF1018V18L-100BGXI

CYF1036V18L-100BGXI

CYF1072V18L-100BGXI

51-85167 209-ball fine-pitch ball grid array (FBGA) (14 × 22 × 1.76 mm)

Industrial

Ordering Code Definitions

CY F X XXX VXX X - XXX BGXI

Speed:

100 MHz

I/O Standard:

L = LVCMOS

I/O Voltage:

18 = 1.8V

33 = 3.3 V

Density:

018 = 18M

036 = 36M

072 = 72M

1 - Multi-Queue (2 Queues)

FIFO

Cypress

Document Number: 001-68321 Rev. **

Page 24 of 28

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CYF1072V

Package Diagram

Figure 24. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167

51-85167 *A

Document Number: 001-68321 Rev. **

Page 25 of 28

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CYF1018V, CYF1036V

CYF1072V

Acronyms

Document Conventions

Units of Measure

Acronym

FF

Description

Full flag

Symbol

Unit of Measure

degree Celsius

FIFO

First in first out

Empty flag

Input/output

°C

A

mA

ms

MHz

ns

micro Amperes

milli Amperes

milli seconds

Mega Hertz

nano seconds

ohms

EF

I/O

FBGA

JTAG

LVCMOS

fine-pitch ball grid array

Joint test action group

Low voltage complementary metal oxide

semiconductor



pF

V

pico Farad

Volts

MB

Mailbox

MRS

Master reset

Output enable

Read clock

W

Watts

OE

RCLK

REN

Read enable

Read clock

RCLK

RQSEL0

SCLK

TDI

Read Queue select

Serial clock

Test data in

TDO

Test data out

Test clock

TCK

TMS

Test mode select

Write clock

WCLK

WEN

WQSEL0

QUE-0

QUE-1

Write enable

Write Queue select

Queue number 0

Queue number 1

Document Number: 001-68321 Rev. **

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Document History Page

Document Title: CYF1018V/CYF1036V/CYF1072V, 18/36/72-Mbit Programmable 2-Queue FIFOs

Document Number: 001-68321

Orig. of Submission

Rev.

ECN No.

Change

Date

Description of Change

**

3209860

SIVS

03/30/2011 New data sheet

Document Number: 001-68321 Rev. **

Page 27 of 28

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CYF1072V

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Clocks & Buffers

Interface

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,

life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical

components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-68321 Rev. **

Revised April 12, 2011

Page 28 of 28

All products and company names mentioned in this document may be the trademarks of their respective holders.

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型号：	CYF1018V
厂家：	CYPRESS
描述：	18/36/72-Mbit Programmable 2-Queue FIFOs Independent read and write ports 36分之18 / 72- Mbit的可编程2 -队列FIFO的独立读写端口先进先出芯片
文件：	总28页 (文件大小：892K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYF1018V [CYPRESS]

相关型号：

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CYF1036V33L-100BGXI

CYF1072V

CYF1072V18L-100BGXI

CYF1072V33L-100BGXI

CYF2018V

CYF2018V18L-100BGXI

CYF2018V33L-100BGXI