CYF0144V18L-133BGXI [CYPRESS]
FIFO, 4MX36, 10ns, Synchronous, CMOS, PBGA209, FBGA-209;
| 型号： | CYF0144V18L-133BGXI |
| 厂家： | 
CYPRESS |
| 描述： | FIFO, 4MX36, 10ns, Synchronous, CMOS, PBGA209, FBGA-209 时钟 LTE 先进先出芯片 内存集成电路 |
| 文件： | 总29页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CYF0144V
144-Mbit Programmable FIFOs
144-Mbit Programmable FIFOs
Features
Functional Description
■ Memory organization
❐ Industry’s largest first in first out (FIFO) memory density:
144-Mbit
❐ Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
133 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 4.8 Gbps. The read and write ports can support
multiple I/O voltage standards. The user-programmable
registers enable user to configure the device operation as
desired. The device also offers a simple and easy-to-use
interface to reduce implementation and debugging efforts,
improve time-to-market, and reduce engineering costs. This
makes it an ideal memory choice for a wide range of applications
including multiprocessor interfaces, video and image
processing, networking and telecommunications, high-speed
data acquisition, or any system that needs buffering at very high
speeds across different clock domains.
■ Up to 133-MHz clock operation
■ Unidirectional operation
■ Independent read and write ports
❐ Supports simultaneous read and write operations
❐ Reads and writes operate on independent clocks upto a
maximum ratio, of two enabling data buffering across clock
domains.
❐ Supports multiple I/O voltage standard: low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. The data is sequentially
written into the FIFO from the write port. If the writes and inputs
are enabled, the data on the write port gets written into the device
at the rising edge of the write clock. Enabling the reads and
outputs fetches data on the read port at every rising edge of the
read clock. Both reads and writes can occur simultaneously at
different speeds provided the ratio between read and write clock
is in the range of 0.5 to 2. Appropriate flags are set whenever the
FIFO is empty, full, half-full, almost-full, or almost-empty.
■ Input and output enable control for write mask and read skip
operations
■ Mark and retransmit: resets read pointer to user marked
position
■ Empty, full, half-full, and programmable almost-empty and
almost-full status flags with preselected offsets
■ Flow-through mailbox register to send data from input to output
port, bypassing the FIFO sequence
■ Configure programmable flags and registers through serial or
parallel modes
The device also supports mark and retransmit of data, and a
flow-through mailbox register.
All descriptions are given assuming the device CYF0144V is
operated in × 36 mode. They hold good for all port sizes × 9,
× 12, × 16, × 18, × 20, × 24 and × 32 unless otherwise specified.
The only difference will be in the input and output bus width.
Table 1 on page 8 shows the part of bus with valid data from
D[35:0] and Q[35:0] in × 9, × 12, × 16, × 18, × 20, × 24, × 32 and
× 36 modes.
■ Separate serial clock (SCLK) input for serial programming
■ Master reset to clear entire FIFO
■ Partial reset to clear data but retain programmable settings
■ Joint test action group (JTAG) port provided for boundary scan
function
■ Industrial temperature range: –40 °C to +85 °C
Cypress Semiconductor Corporation
Document Number: 001-70361 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 7, 2012
PRELIMINARY
CYF0144V
Logic Block Diagram
D[35:0]
IE
WEN
WCLK
LD
SPI_SEN SPI_SCLK
SPI_SI
MB
INPUT
REGISTER
CONFIGURATION
REGISTERS/MAILBOX
WRITE
CONTROL LOGIC
FF
PAF
EF
WRITE POINTER
FLAG LOGIC
PAE
DVal
HF
Memory Array
144-Mbit
MRS
PRS
RESET POINTER
JTAG CONTROL
READ POINTER
TCK
TRST
TMS
READ CONTROL
LOGIC
MARK, RT
TDO
TDI
OUTPUT
REGISTER
RCLK
REN
OE
MEMORY LOGIC
ORGANIZATION
Q[35:0]
PORTSZ[2:0]
Document Number: 001-70361 Rev. *A
Page 2 of 29
PRELIMINARY
CYF0144V
Contents
Pin Diagram for CYF0144VXXL .......................................4
Pin Definitions ..................................................................5
Architecture ......................................................................7
Reset Logic .................................................................7
Flag Operation .............................................................7
Full Flag .......................................................................7
Half-Full Flag ...............................................................7
Empty Flag ..................................................................7
Programmable Almost-Empty and
Almost-Full Flags ................................................................7
Retransmit from Mark Operation .................................7
Flow-through Mailbox Register ....................................7
Selecting Word Sizes ..................................................8
Data Valid Signal (DVal) ..............................................8
Power Up .....................................................................8
Write Mask and Read Skip Operation .........................8
Programming Flag Offsets and
Maximum Ratings ...........................................................13
Operating Range .............................................................13
Recommended DC Operating Conditions ....................13
Electrical Characteristics ...............................................13
I/O Characteristics ..........................................................14
Latency Table ..................................................................14
AC Test Load Conditions ...............................................15
Switching Characteristics ..............................................16
Switching Waveforms ....................................................17
Ordering Information ......................................................25
Ordering Code Definitions .........................................25
Package Diagram ............................................................26
Acronyms ........................................................................27
Document Conventions .................................................27
Units of Measure .......................................................27
Document History Page .................................................28
Sales, Solutions, and Legal Information ......................29
Worldwide Sales and Design Support .......................29
Products ....................................................................29
PSoC Solutions .........................................................29
Configuration Registers ......................................................8
Width Expansion Configuration .................................10
Memory Organization for Different Port Sizes ...........11
Read/Write Clock Requirements ...............................11
JTAG Operation ........................................................12
Document Number: 001-70361 Rev. *A
Page 3 of 29
PRELIMINARY
CYF0144V
Pin Diagram for CYF0144VXXL
Figure 1. 209-ball FBGA (Top View)
1
2
3
4
5
PORTSZ0
DNU
VCC1
DNU
VCCIO
VSS
6
PORTSZ1
PORTSZ2
DNU
7
DNU
DNU
VCC1
DNU
VCCIO
VSS
8
9
10
11
Q1
A
B
C
D
E
F
FF
D0
D1
DNU
DNU
DNU
VCC1
VCC2
VSS
DNU
DNU
DNU
VCC1
VCC2
VSS
RT
Q0
Q2
EF
D2
D3
REN
RCLK
VSS
Q3
D4
D5
WEN
VSS
Q4
Q5
D6
D7
LD
Q6
Q7
D8
D9
VCC2
VSS
VCCIO
DNU
VCC2
VSS
Q8
Q9
D10
D12
D14
D16
DNU
D18
D20
D22
D24
D26
D28
DVal
PAF
TDO
D11
D13
D15
D17
DNU
D19
D21
D23
D25
D27
D29
DNU
PAE
HF
Q10
Q12
Q14
Q16
VCCIO
Q18
Q20
Q22
Q24
Q26
Q28
Q30
Q32
Q34
Q11
Q13
Q15
Q17
VCCIO
Q19
Q21
Q23
Q25
Q27
Q29
Q31
Q33
Q35
G
H
J
VCC2
VSS
VCC2
VSS
VCCIO
VSS
VCCIO
VSS
VCCIO
VSS
VCCIO
VSS
VCC1
VCCIO
VSS
VCCIO
VSS
VCCIO
VSS
VCCIO
VSS
VCC2
VSS
VCC2
VSS
VCC1
VCC2
WCLK
VCC2
VSS
VCC2
DNU
VCC2
VSS
VCC1
VCC2
DNU
VCC2
VSS
VCC2
VCCIO
VCC2
VSS
K
L
IE
VCC1
M
N
P
R
T
VCC1
VCC2
VSS
VCC2
VSS
VCC1
VCC2
VSS
VCC2
VSS
SPI_SEN
VCCIO
SPI_SI
DNU [1]
MRS
VCC2
VSS
VCC2
VCC1
D31
VCCIO
VCC1
PRS
VCCIO
VCC1
SPI_SCLK
MB
VCC2
VCC1
VREF
DNU
TCK
VCC2
VSS
U
V
W
D30
D32
D34
OE
D33
DNU
TDI
MARK
DNU
D35
TRST
TMS
Note
1. This pin should be tied to V preferably or can be left floating to ensure normal operation.
SS
Document Number: 001-70361 Rev. *A
Page 4 of 29
PRELIMINARY
CYF0144V
Pin Definitions
Pin Name
D[35:0]
I/O
Input
Output Data outputs: Data outputs for a 36-bit bus
Pin Description
Data inputs: Data inputs for a 36-bit bus
Q[35:0]
WEN
REN
IE
Input
Input
Input
Write enable: WEN enables WCLK to write data into the FIFO memory and configuration registers.
Read enable: REN enables RCLK to read data from the FIFO memory and configuration registers.
Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIFO. The internal write address
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for ‘write masking’ or incrementing the write pointer without writing into a location.
OE
Input
Input
Input
Output enable: When OE is LOW, FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
WCLK
RCLK
Write clock: When enabled by WEN, the rising edge of WCLK writes data into the FIFO if LD is high and
into the configuration registers if LD is low.
Read clock: When enabled by REN, the rising edge of RCLK reads data from the FIFO memory if LD is
high and from the configuration registers if LD is low.
EF
Output Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
Output Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Output Programmable almost-empty: When PAE is LOW, the FIFO is almost empty based on the almost-empty
offset value programmed into the FIFO. It is synchronized to RCLK.
PAF
LD
Output Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset
value programmed into the FIFO. It is synchronized to WCLK.
Input
Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configuration registers. When
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO.
RT
Input
Retransmit: A HIGH pulse on RT resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal to the write pointer.
MRS
Input
Master reset: MRS initializes the internal read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the configuration registers are all set to default values and flags are
reset.
PRS
Input
Input
Partial reset: PRS initializes the internal read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the configuration register settings are all retained and flags are reset.
SPI_SCLK
Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
SPI_SI
SPI_SEN
MARK
Input
Input
Input
Serial input: Serial input data in SPI mode.
Serial enable: Enables serial loading of programmable flag offsets and configuration registers.
Mark for retransmit: When this pin is asserted the current location of the read pointer is marked. Any
subsequent retransmit operation resets the read pointer to this position.
MB
Input
Input
Input
Input
Input
Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
Test clock (TCK) Pin for JTAG
TCK
TRST
TMS
TDI
Reset pin for JTAG
Test mode select (TMS) pin for JTAG
Test data in (TDI) pin for JTAG
TDO
Output Test data out (TDO) for JTAG
Document Number: 001-70361 Rev. *A
Page 5 of 29
PRELIMINARY
CYF0144V
Pin Definitions (continued)
Pin Name
HF
I/O
Pin Description
Output Half-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK.
Output Data valid: Active low data valid signal to indicate valid data on Q[35:0]
DVal
PORTSZ [2:0]
VCC1
Input
Port word size select: Port word width select pins (common for read and write ports)
Core voltage supply 1: 1.8 V supply voltage
Power
Supply
VCC2
VCCIO
VREF
Power
Supply
Core voltage supply 2: 1.5 V supply voltage
Supply for I/Os
Power
Supply
Input
Reference
Reference voltage: Reference voltage (regardless of I/O standard used)
VSS
Ground Ground
Do not use: These pins need to be left floating
DNU
–
Document Number: 001-70361 Rev. *A
Page 6 of 29
PRELIMINARY
CYF0144V
de-asserted.The minimum number of reads required to
de-assert full-flag is two and the maximum number of reads
required to de-assert full flag is six.
Architecture
The CYF0144V is a memory array of 144-Mbits. The memory
organization is user configurable and word sizes can be selected
as × 9, × 12, × 16, × 18, × 20, × 24, × 32, or × 36. The logic blocks
to implement FIFO functionality and the associated features are
built around these memory arrays.
Half-Full Flag
The Half-Full (HF) flag goes LOW when half of the memory array
is written. The assertion of HF is synchronized to WCLK. The
assertion and de-assertion of Half-Full flag with associated
latencies is explained in Latency Table on page 14.
The input and output data buses have a maximum width of
36 bits. The input data bus goes to an input register and the data
flow from the input register to the memory is controlled by the
write logic block. The inputs to the write logic block are WCLK,
WEN and IE. When the writes are enabled through WEN and if
the inputs are enabled by IE, then the data on the input bus is
written into the memory array at the rising edge of WCLK. This
also increments the write pointer. Enabling writes but disabling
the data input pins through IE only increments the write pointer
without doing any writes or altering the contents of the location.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, that is, it is
exclusively updated by each rising edge of RCLK. The assertion
and de-assertion of empty flag with associated latencies is
explained in Latency Table on page 14.
Similarly, the output register is connected to the data output bus.
Transfer of contents from the memory to the output register is
controlled by the read control logic. The inputs to the read control
logic include RCLK, REN, OE, RT and MARK. When reads are
enabled by REN and outputs are enabled through OE, the data
from the memory pointed by the read pointer is transferred to the
output data bus at the rising edge of RCLK along with active low
DVal. If the outputs are disabled but the reads enabled, the
outputs are in high impedance state, but internally the read
pointer is incremented.
Programmable Almost-Empty and Almost-Full Flags
The CYF0144V includes programmable Almost-Empty and
Almost-Full flags. Each flag is programmed (see Programming
Flag Offsets and Configuration Registers on page 8) a specific
distance from the corresponding boundary flags (Empty or Full).
(offset can range from 16 to 1024) When the FIFO contains the
number of words (or fewer) for which the flags are programmed,
the PAF or PAE is asserted, signifying that the FIFO is either
almost-full or almost-empty. The PAF flag signal transition is
caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock. The
assertion and de-assertion of empty flag with associated
latencies is explained in Latency Table on page 14.
During write operation, the number of writes performed is always
a even number (i.e., minimum write burst length is two and
number of writes always a multiple of two). Whereas during read
operation, the number of reads performed can be even or odd
(i.e., minimum read burst length is one).
Retransmit from Mark Operation
The MARK signal is used to ‘mark’ the location from which data
is retransmitted when requested.
The retransmit feature is useful for transferring packets of data
repeatedly. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
feature is used when the number of writes after MARK is equal
to or less than the depth of the FIFO and at least one word has
been read since the last reset cycle. A HIGH pulse on RT resets
the internal read pointer to a physical location of the FIFO that is
marked by the user (using the MARK pin). With every valid read
cycle after retransmit, previously accessed data is read and the
read pointer is incremented until it is equal to the write pointer.
Flags are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data written
to FIFO after activation of RT are also transmitted. The full depth
of the FIFO can be repeatedly retransmitted.
Reset Logic
The FIFO can be reset in two ways: Master Reset (MRS) and
Partial Reset (PRS). The MRS initializes the read and write
pointers to zero and sets the output register to all zeroes. It also
resets the configuration registers to their default values. The
word size is configured through pins; values of the three
PORTSZ pins are latched during MRS. A Master Reset is
required after power-up before accessing the FIFO. The PRS
resets only the read and write pointer to the first location and
does not affect the programmed configuration registers.
Flag Operation
To mark a location, the Mark pin is asserted when reading that
particular location.
This device provides five flag pins to indicate the condition of the
FIFO contents.
Flow-through Mailbox Register
Full Flag
This feature transfers data from input to output directly by
bypassing the FIFO sequence. When MB signal is asserted the
data present in D[35:0] will be available at Q[35:0] after two
WCLK cycles. Normal read and write operations are not allowed
during flow-through mailbox operation. Before starting
Flow-through mailbox operation FIFO read should be completed
to make data valid DVal high in order to avoid data loss from
FIFO. The width of flow-through mailbox register always
corresponds to port size.
The Full Flag (FF) goes LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, that is, it is
exclusively updated by each rising edge of WCLK. The worst
case assertion latency for Full Flag is four. As the user cannot
know that the FIFO is full for four clock cycles, it is possible that
user continues writing data during this time. In this case, the four
data word written will be stored to prevent data loss and these
words have to be read back in order for full flag to get
Document Number: 001-70361 Rev. *A
Page 7 of 29
PRELIMINARY
CYF0144V
a read operation is performed, the DVal signal goes low along
with output data. This helps user to capture the data without
keeping track of REN to data output latency. This signal also
helps when write and read operations are performed
continuously at different frequencies by indicating when valid
data is available at the output port Q[35:0].
Selecting Word Sizes
The word sizes are configured based on the logic levels on the
PORTSZ pins during the master reset (MRS) cycle only (latched
on low to high edge). The port size cannot be changed during
normal mode of operation and these pins are ignored. Table 1.
explains the pins of D[35:0] and Q[35:0] that will have valid data
in modes where the word size is less than × 36. If word size is
less than × 36, the unused output pins are tri-stated by the device
and unused input pins will be ignored by the internal logic. The
pins with valid data input D[N:0] and output Q[N:0] is given in
Table 1.
Power Up
The device becomes functional after VCC1, VCC2, VCCIO, and
VREF attain minimum stable voltage required as given in
Recommended DC Operating Conditions on page 13. The
device can be accessed at tPU time after these supplies attain the
minimum required level (see the Switching Characteristics on
page 16). There is no particular power sequencing required for
the device.
Data Valid Signal (DVal)
Data valid (DVal) is an active low signal, synchronized to RCLK
and is provided for easy capture of output data to the user. When
Table 1. Word Size Selection
PORTSZ[2:0]
Word Size
× 9
Active Input Data Pins D[X:0] Active Output Data Pins Q[X:0]
000
001
010
011
100
101
110
111
D[8:0]
D[11:0]
D[15:0]
D[17:0]
D[19:0]
D[23:0]
D[31:0]
D[35:0]
Q[8:0]
Q[11:0]
Q[15:0]
Q[17:0]
Q[19:0]
Q[23:0]
Q[31:0]
Q[35:0]
× 12
× 16
× 18
× 20
× 24
× 32
× 36
pin. A low on the SPI_SEN selects the serial method for writing
into the registers. For serial programming, there is a separate
SCLK and a Serial Input (SI). In parallel mode, a low on the load
(LD) pin causes the write and read operation to these registers.
The write and read operation happens from the first location
(0x1) to the last location (0xA) in a sequence. If LD is high, the
writes occur to the FIFO.
Write Mask and Read Skip Operation
As mentioned in Architecture on page 7, enabling writes but
disabling the inputs (IE HIGH) increments the write pointer
without doing any write operations or altering the contents of the
location.
This feature is called Write Mask and allows user to move the
write pointer without actually writing to the locations. This “write
masking” ability is useful in some video applications such as
Picture In Picture (PIP).
In addition to loading register values into the FIFO, it is also
possible to read the current register values. Register values can
be read through the parallel output port regardless of the
programming mode selected (serial or parallel). Register values
cannot be read serially. The registers may be programmed (and
reprogrammed) any time after master reset, regardless of
whether serial or parallel programming is selected.
Similarly, during a read operation, if the outputs are disabled by
having the OE high, the read data does not appear on the output
bus; however, the read pointer is incremented.
Programming Flag Offsets and Configuration
Registers
See Table 3 on page 9 and Table 4 on page 10 for access to
configuration registers in serial and parallel modes.
The CYF0144V has ten 8-bit user configurable registers. These
registers contain the almost-full offset (M) and almost-empty (N)
values which decide when the PAF and PAE flags are asserted.
In parallel mode, the read and write operations loop back when
the maximum address location of the configuration registers is
reached. Simultaneous read and write operations should be
avoided on the configuration registers. Any change in
configuration registers will take effect after eight write clock
cycles (WCLK) cycles.
These registers can be programmed into the FIFO in one of two
ways: using either the serial or parallel loading method. The
loading method is selected using the SPI_SEN (Serial Enable)
Document Number: 001-70361 Rev. *A
Page 8 of 29
PRELIMINARY
CYF0144V
Table 2. Configuration Registers
ADDR Configuration Register
Default
0x00
Bit [7] Bit [6] Bit [5] Bit [4]
Bit [3] Bit [2] Bit [1] Bit [0]
0x1 Reserved
0x2 Reserved
0x3 Reserved
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x00
0x00
X
X
X
X
X
X
X
X
0x4 Almost-Empty Flag generation 0x7F
address - (LSB) (N)
D7
D6
D5
D4
D3
D2
D1
D0
0x5 Almost-Empty Flag generation 0x00
address - (MSB) (N)
X
X
X
X
X
X
D9
D8
0x6 Reserved
0x00
0x7F
X
X
X
X
X
X
X
X
0x7 Almost-Full Flag generation
address - (LSB) (M)
D7
D6
D5
D4
D3
D2
D1
D0
0x8 Almost-Full Flag generation
address - (MSB) (M)
0x00
X
X
X
X
X
X
D9
D8
0x9 Reserved
0x00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0xA Fast CLK Bit Register
1XXXXXXXb Fast CLK
bit
Table 3. Writing and Reading Configuration Registers in Parallel Mode
SPI_SEN
LD
WEN REN
WCLK
RCLK
SPI_SCLK
Operation
1
0
0
1
First rising edge
because both LD and
WEN are low
X
X
Parallel write to first register
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Second rising edge
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Parallel write to second register
Third rising edge
Parallel write to third register
Fourth rising edge
Parallel write to fourth register
·
·
·
·
·
·
Tenth rising edge
Eleventh rising edge
Parallel write to tenth register
Parallel write to first register
(roll back)
1
1
0
0
1
1
0
0
X
X
Firstrisingedgesince
both LD and REN are
low
X
X
Parallel read from first register
Second rising edge
Parallel read from second
register
1
1
0
0
1
1
0
0
X
X
Third rising edge
Fourth rising edge
X
X
Parallel read from third register
Parallel read from fourth
register
1
1
1
0
0
0
1
1
1
0
0
0
X
X
X
·
·
·
X
X
X
·
·
·
Document Number: 001-70361 Rev. *A
Page 9 of 29
PRELIMINARY
CYF0144V
Table 3. Writing and Reading Configuration Registers in Parallel Mode (continued)
SPI_SEN
LD
WEN REN
WCLK
RCLK
SPI_SCLK
Operation
1
0
1
0
X
Tenth rising edge
X
Parallel read from tenth
register
1
0
1
0
X
Eleventh rising edge
X
Parallel read from first register
(roll back)
1
X
X
0
X
1
1
0
1
0
1
X
0
1
X
X
X
X
X
X
No operation
Rising edge
X
Write to FIFO memory
Read from FIFO memory
Illegal operation
X
X
X
X
Rising edge
X
Table 4. Writing into Configuration Registers in Serial Mode
SPI_SEN
LD
WEN
REN
WCLK
RCLK
SCLK
Operation
0
1
X
X
X
X
Rising edge Each rising of the SCLK clocks
in one bit from the SI (Serial
In). Any of the 10 registers can
be addressed and written to,
following the SPI protocol.
X
X
1
1
0
X
0
Rising edge
X
X
X
Parallel write to FIFO memory.
X
X
Rising edge
Parallel read from FIFO
memory.
1
0
1
1
X
X
X
This corresponds to parallel
mode (refer to Table 3 on page
9).
Figure 2. Serial WRITE to Configuration Register
Width Expansion Configuration
The width of CYF0144V can be expanded to provide word widths greater than 36 bits. During width expansion mode, all control line
inputs are common and all flags are available. Empty (Full) flags are created by ANDing the Empty (Full) flags of every FIFO; the PAE
and PAF flags can be detected from any one device. This technique avoids reading data from or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 3 on page 11 demonstrates an example
of 72-bit word width by using two 36-bit word CYF0144Vs.
Document Number: 001-70361 Rev. *A
Page 10 of 29
PRELIMINARY
CYF0144V
Figure 3. Using Two CYF0144V for Width Expansion
DATAIN (D)
72
36
36
READCLOCK(RCLK)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
READENABLE(REN)
OUTPUT ENABLE(OE)
PAF
CYF0144V
CYF0144V
PAE
HF
EF
EF
FF
FF
EF
DATAOUT (Q)
36
72
FF
36
Memory Organization for Different Port Sizes
Read/Write Clock Requirements
The 144-Mbit memory has different organization for different port
sizes. Table 5 shows the depth of the FIFO for all port sizes.
The read and write clocks must satisfy the following
requirements:
Note that for all port sizes, four to eight locations are not available
for writing the data and are used to safeguard against false
synchronization of empty and full flags.
■ Both read (RCLK) and write (WCLK) clocks should be
free-running.
■ The clock frequency for both clocks should be between the
minimum and maximum range given in Electrical
Characteristics on page 13.
Table 5. Word Size Selection
PORTSZ[2:0]
000
Word Size
× 9
FIFO Depth
16 Meg
8 Meg
Memory Size
144 Mbit
96 Mbit
■ The WCLK to RCLK ratio should be in the range of 0.5 to 2.
For proper FIFO operation, the device must determine which of
the input clocks – RCLK or WCLK – is faster. This is evaluated
by using counters after the MRS cycle. The device uses two
10-bit counters inside (one running on RCLK and other on
WCLK), which count 1,024 cycles of read and write clock after
MRS. The clock of the counter which reaches its terminal count
first is used as master clock inside the FIFO.
001
× 12
010
× 16
8 Meg
128 Mbit
144 Mbit
80 Mbit
011
× 18
8 Meg
100
× 20
4 Meg
101
× 24
4 Meg
96 Mbit
110
× 32
4 Meg
128 Mbit
144 Mbit
When there is change in the relative frequency of RCLK and
WCLK during normal operation of FIFO, user can specify it by
using “Fast CLK bit” in the configuration register (0xA).
111
× 36
4 Meg
“1” - indicates freq (WCLK) > freq (RCLK)
“0” - indicates freq (WCLK) < freq (RCLK)
The result of counter evaluated frequency is available in this
register bit. User can override the counter evaluated frequency
for faster clock by changing this bit.
Whenever there is a change in this bit value, user must wait tPLL
time before issuing the next read or write to FIFO.
Document Number: 001-70361 Rev. *A
Page 11 of 29
PRELIMINARY
CYF0144V
JTAG Operation
CYFX144V has two devices connected internally in a JTAG chain as shown in Figure 4.
Figure 4. Device Connection in a JTAG Chain
TRST
TMS
TCK
TDI
TDO
Table 6 shows the IR register length and device ID.
Table 6. JTAG IDCODES
IR Register Length
Device ID (HEX)
Bypass Register Length
Device-1
Device-2
3
8
“Ignore”
1E3261CF
1
1
Table 7. JTAG Instructions for Device-1
Device-1
Opcode (Binary)
BYPASS
111
Table 8. JTAG Instructions for Device-2
Device-2
EXTEST
Opcode (HEX)
00
07
01
FF
0F
HIGHZ
SAMPLE/PRELOAD
BYPASS
IDCODE
Document Number: 001-70361 Rev. *A
Page 12 of 29
PRELIMINARY
CYF0144V
I/O port supply voltage (VCCIO) ......................–0.3 V to 3.7 V
Voltage applied to I/O pins ...........................–0.3 V to 3.75 V
Output current into outputs (LOW) ............................. 24 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage
(per MIL–STD–883, Method 3015) .........................> 2001 V
Storage temperature (without bias) ........ –65 C to +150 C
Ambient temperature with
power applied ......................................... –55 C to +125 C
Operating Range
Core supply voltage 1 (VCC1) to
ground potential .............................................–0.3 V to 2.5 V
Range
Ambient Temperature
–40 C to +85 C
Core supply voltage 2 (VCC2) to
ground potential ...........................................–0.3 V to 1.65 V
Industrial
Latch up current ............................................... > 100 mA
Recommended DC Operating Conditions
Parameter
VCC1
Description
Min
1.70
1.425
0.7
Typ
1.80
1.5
Max
1.90
1.575
0.8
Unit
V
Core supply voltage 1
Core supply voltage 2
VCC2
VREF
VCCIO
V
Reference voltage (irrespective of I/O standard used)
I/O supply voltage, read and write banks. LVCMOS33
0.75
3.30
1.8
V
3.00
1.70
3.60
1.90
V
LVCMOS18
V
Electrical Characteristics
Parameter
ICC
Description
Conditions
Min
–
Typ
–
Max
400
500
Unit
mA
Active current
VCC1 = VCC1MAX
,
VCC2 = VCC2MAX
All I/O switching,
133 MHz
,
–
–
mA
VCCIO = VCCIOMAX
–
–
50
mA
(All outputs disabled)
II
Input pin leakage current
I/O pin leakage current
VIN = VCCIOMAX to 0 V
–15
–15
–
–
–
–
–
15
15
16
8
µA
µA
pF
pF
IOZ
CP
CPIO
VO = VCCIOMAX to 0 V
Capacitance for TMS and TCK
–
–
Capacitance for all other pins except TMS
and TCK
–
Document Number: 001-70361 Rev. *A
Page 13 of 29
PRELIMINARY
CYF0144V
I/O Characteristics
Over the operating range
Input Voltage (V)
Output voltage (V)
Output Current (mA)
Nominal I/O
I/O standard
supply voltage
VIL(max)
0.80
VIH(min)
2.20
VOL(max)
0.45
VOH(min)
2.40
IOL(max)
IOH(max)
LVCMOS33
LVCMOS18
3.3 V
1.8 V
24
16
24
16
30% VCCIO
65% VCCIO
0.45
VCCIO – 0.45
Latency Table
Latency Parameter Number of cycles
Detail
LFF_ASSERT
Min = 0
Max = 4
Last data write to FF going low
LEF_ASSERT
0
1
2
4
4
5
5
7
7
8
9
Last data read to EF going low
PRS to normal operation
LPRS_TO_ACTIVE
LMAILBOX
Latency from write port to read port when MB = 1 (wrt WCLK)
Latency when REN is asserted low to first data output from FIFO
LREN_TO_DATA
LREN_TO_CONFIG
LWEN_TO_PAE_HI
LWEN_TO_PAF_LO
LREN_TO_PAE_LO
LREN_TO_PAF_HI
LFF_DEASSERT
LRT_TO_REN
Latency when REN is asserted along with LD to first data read from configuration registers
Write to PAE going high
Write to PAF going low
Read to PAE going low
Read to PAF going high
Read to FF going high
RT fifth cycle to REN going low for read
RT fifth cycle to valid data on Q[35:0]
LRT_TO_DATA
Min = 19
Max = 21
LIN
Min = 25
Max = 26
Initial latency for data read after FIFO goes empty during simultaneous read/write
Write to EF going high
LEF_DEASSERT
Min = 23
Max = 24
Document Number: 001-70361 Rev. *A
Page 14 of 29
PRELIMINARY
CYF0144V
AC Test Load Conditions
Figure 5. AC Test Load Conditions
R = 50 O
Zo = 50 O
OUTPUT
C = 30pF
Vth = 0.9V
(a) VCCIO = 1.8 Volt
R = 50
Zo = 50
OUTPUT
C = 30pF
Vth = 1.5V
(b) VCCIO = 3.3 Volt
VCCIO
GND
90%
90%
10%
10%
=<1ns
=<1ns
(c) All Input Pulses
Document Number: 001-70361 Rev. *A
Page 15 of 29
PRELIMINARY
CYF0144V
Switching Characteristics
-133
Parameter
Description
Unit
Min
Max
2
tPU
Power-up time after all supplies reach minimum value
–
24
24
–
ms
tS
Clock cycle frequency
Clock cycle frequency
Data access time
3.3 V LVCMOS
1.8 V LVCMOS
133
133
10
41.67
–
MHz
tS
MHz
tA
ns
tCLK
Clock cycle time
7.5
3.375
3.375
3
ns
tCLKH
tCLKL
tDS
Clock high time
ns
Clock low time
–
ns
Data setup time
–
ns
tDH
Data hold time
3
–
ns
tENS
tENH
tENS_SI
tENH_SI
tRATE_SPI
tRS
Enable setup time
3
–
ns
Enable hold time
3
–
ns
Setup time for SPI_SI and SPI_SEN pins
Hold time for SPI_SI and SPI_SEN pins
Frequency of SCLK
5
–
ns
5
–
ns
–
25
–
MHz
Reset pulse width
100
25
25
–
ns
tPZS
Port size select to MRS setup time
MRS to port size select hold time
Reset to flag output time
Retransmit pulse width
Output enable to output in Low Z
Output enable to output valid
Output enable to output in High Z
Write clock to FF
–
ns
tPZH
–
ns
tRSF
50
–
ns
tPRT
5
RCLK cycles
tOLZ
4
15
15
15
8.5
8.5
17
17
17
1024
–
ns
ns
tOE
–
tOHZ
tWFF
tREF
–
ns
–
ns
Read clock to EF
–
ns
tPAF
Clock to PAF flag
–
ns
tPAE
Clock to PAE flag
–
ns
tHF
Clock to HF flag
–
ns
tPLL
Time required to synchronize PLL
JTAG TCK cycle time
Setup time for JTAG TMS, TDI
Hold time for JTAG TMS, TDI
JTAG TCK low to TDO valid
–
cycles
ns
tRATE_JTAG
tS_JTAG
tH_JTAG
tCO_JTAG
100
8
–
ns
8
–
ns
–
20
ns
Document Number: 001-70361 Rev. *A
Page 16 of 29
PRELIMINARY
CYF0144V
Switching Waveforms
Figure 6. Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
D[35:0]
t
t
DH
DS
t
ENH
t
ENS
WEN, IE
NO OPERATION
Figure 7. Read Cycle Timing
t
CLK
RCLK
t
t
ENH
ENS
REN
NO OPERATION
LREN_TO_DATA
t
A
VALID DATA
Q[35:0]
t
OLZ
t
OHZ
OE
DVal
Document Number: 001-70361 Rev. *A
Page 17 of 29
PRELIMINARY
CYF0144V
Switching Waveforms (continued)
Figure 8. Reset Timing
t
RS
MRS
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
HF
OE=1
Q[35:0]
–
OE=0
Figure 9. MRS to PORTSZ[2:0]
WCLK/RCLK
MRS
tPZS
tPZH
PORTSZ[2:0]
Document Number: 001-70361 Rev. *A
Page 18 of 29
PRELIMINARY
CYF0144V
Switching Waveforms (continued)
Figure 10. Empty Flag Timing
RCLK
t
REF
EF
REN
OE
Q[35:0]
Q(Last)-3
Q(Last)
Invalid Data
Q(Last)-2
Q(Last)-1
DVal
Figure 11. Full Flag Timing
WCLK
t
DS
D[35:0]
D0 (written)
D3 (not written)
D4 (not written)
D1 (written)
D2 (written)
t
WFF
FF
WEN
Document Number: 001-70361 Rev. *A
Page 19 of 29
PRELIMINARY
CYF0144V
Switching Waveforms (continued)
Figure 12. Initial Data Latency
WCLK
/RCLK
D[35:0]
D0
D3
D4
Q1
D1
D2
t
A
WEN/REN
OE
Q0
Q[35:0]
DVal
LIN (initial latency)
Figure 13. Flow-through Mailbox Operation
WCLK
D[35:0]
DO
D1
D2
D3
D4
REN / WEN
L MAILBOX
MB
Q[35:0]
QO
Q1
Q2
Q3
Q4
DVal
Document Number: 001-70361 Rev. *A
Page 20 of 29
PRELIMINARY
CYF0144V
Switching Waveforms (continued)
Figure 14. Configuration Register Write
WCLK
tENS
WEN
LD
tDH
tDS
D[35:0]
config-reg 0
config-reg 1
config-reg 2
config-reg 3
config-reg 4
config-reg 5
Figure 15. Configuration Register Read
WCLK
/RCLK
REN
LREN_TO_CONFIG
t
A
LD
Q[35:0]
Reg - 1
Figure 16. Empty Flag Deassertion
WCLK
/ IE
WEN
D0
D1
D[35:0]
EF
L EF_DEASSERT
tREF
RCLK
REN
Document Number: 001-70361 Rev. *A
Page 21 of 29
PRELIMINARY
CYF0144V
Switching Waveforms (continued)
Figure 17. Empty Flag Assertion
RCLK
REN
tA
Q
LAST
Q[35:0]
DVal
L REN_TO_DATA
EF
tREF
Figure 18. Full Flag Assertion
WCLK
/ IE
WEN
NOT
WRITTEN
D
0
D
1
D
x
D
D
LAST
NOT
WRITTEN
D[35:0]
LAST-1
FF
Figure 19. Full Flag Deassertion
WCLK
WEN / IE
D
D
D
D
D
D
LAST
D[35:0]
LAST-5
LAST-4
LAST-3
LAST-2
LAST-1
L FF_DEASSERT
FF
RCLK
REN
Document Number: 001-70361 Rev. *A
Page 22 of 29
PRELIMINARY
CYF0144V
Switching Waveforms (continued)
Figure 20. PAE Assertion and Deassertion
WCLK
WEN/ IE
RCLK
WEN for
OFFSET +1
LOCATION
REN
PAE
L WEN_TO_PAE_HI
1 READ
L REN_TO_PAE_LO
tPAE
tPAE
Figure 21. PAF Assertion and Deassertion
WCLK
WEN/ IE
FULL - (OFFSET +1)
WRITE
RCLK
REN
PAF
L REN_TO_PAF_HI
1 READ
L WEN_TO_PAF_LO
tPAF
tPAF
Figure 22. HF Assertion and Deassertion
WCLK
/ IE
WEN
FULL / 2
WRITE
RCLK
REN
L REN_TO_PAF_HI
L WEN_TO_PAF_LO
1 READ
HF
tHF
tHF
Document Number: 001-70361 Rev. *A
Page 23 of 29
PRELIMINARY
CYF0144V
Switching Waveforms (continued)
Figure 23. Mark
RCLK
tENS
REN
tENH
MARK
Q[35:0]
DVal
Q (N+3)
Q (N+5)
Q (N-2)
Q (N-1)
Q (N)
Q (N+1)
Q (N+2)
Q (N+4)
Q (N+6)
DATA MARKED
Figure 24. Retransmit
RCLK
REN
tPRT
LRT_TO_REN
LRT_TO_DATA
RT_FL
Q[35:0]
Q (N+1)
Q (N)
RETRANSMIT FROM
DATA MARKED
DVal
n
Document Number: 001-70361 Rev. *A
Page 24 of 29
PRELIMINARY
CYF0144V
Ordering Information
Speed
Package
Diagram
Operating
Range
(MHz)
Ordering Code
Package Type
51-85167 209-ball FBGA (14 × 22 × 1.76 mm) Pb-free
133 CYF0144V18L-133BGXI
CYF0144V33L-133BGXI
Industrial
Ordering Code Definitions
CY F 0 144 VXX L - 133 BGX I
I = Industrial
BGX - Pb-free
FBGA
Speed:
133 MHz
I/O Standard:
L = LVCMOS
I/O Voltage:
18 = 1.8 V
33 = 3.3 V
Density:
144 = 144M
0 - single-queue
FIFO
Cypress
Document Number: 001-70361 Rev. *A
Page 25 of 29
PRELIMINARY
CYF0144V
Package Diagram
Figure 25. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *C
Document Number: 001-70361 Rev. *A
Page 26 of 29
PRELIMINARY
CYF0144V
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
EF
empty flag
fine-pitch ball grid array
Unit of Measure
FBGA
FF
°C
MHz
A
mA
mm
ms
ns
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
nanosecond
ohm
full flag
FIFO
HF
first in first out
half-full flag
HSTL
IE
high-speed transceiver logic
input enable
I/O
input/output
JTAG
LSB
joint test action group
least significant bit
%
percent
pF
V
picofarad
volt
LVCMOS low voltage complementary metal oxide
semiconductor
W
watt
MB
mailbox
MSB
MRS
OE
most significant bit
master reset
output enable
programmable almost-empty
programmable almost-full
partial reset
PAE
PAF
PRS
RCLK
REN
SCLK
TCK
TDI
read clock
read enable
serial clock
test clock
test data in
TDO
TMS
WCLK
WEN
test data out
test mode select
write clock
write enable
Document Number: 001-70361 Rev. *A
Page 27 of 29
PRELIMINARY
CYF0144V
Document History Page
Document Title: CYF0144V, 144-Mbit Programmable FIFOs
Document Number: 001-70361
Orig. of
Change
Submission
Date
Rev.
**
ECN No.
3290935
3744461
Description of Change
ADMU
SMCH
11/15/2011 New data sheet.
*A
11/07/2012 Updated Functional Description.
Updated Pin Diagram for CYF0144VXXL (Updated Figure 1, added Note 1 and
referred the same note in DNU (ball U6)).
Updated Architecture (Updated Selecting Word Sizes).
Updated Maximum Ratings (Changed the value of Output current into outputs
(LOW) from 20 mA to 24 mA).
Updated Electrical Characteristics (Changed maximum value of ICC parameter
from 700 mA to 400 mA (for Condition “VCC1 = VCC1MAX”), changed maximum
value of ICC parameter from 600 mA to 500 mA (for Condition
“VCC2 = VCC2MAX, all I/O switching, 100 MHz”), changed maximum value of
I
CC parameter from 100 mA to 50 mA (for Condition “VCCIO = VCCIOMAX (All
outputs disabled)”)).
Added AC Test Load Conditions.
Updated Switching Characteristics (Changed the minimum value of tS_JTAG
and tH_JTAG parameters from 5 ns to 8 ns, changed the maximum value of
t
CO_JTAG parameter from 10 ns to 20 ns).
Updated Package Diagram (spec 51-85167 (Changed revision from *B to *C)).
Document Number: 001-70361 Rev. *A
Page 28 of 29
PRELIMINARY
CYF0144V
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-70361 Rev. *A
Revised November 7, 2012
Page 29 of 29
All products and company names mentioned in this document may be the trademarks of their respective holders.
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