CY8C21434-12X14I_技术文档

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

PSoC^®Programmable System-on-Chip™

❐ Up to eight analog inputs on GPIOs

❐ Configurable interrupt on all GPIOs

Features

■ Powerful Harvard-architecture processor

❐ M8C processor speeds up to 24 MHz

❐ Low power at high speed

❐ Operating voltage: 2.4 V to 5.25 V

❐ Operating voltages down to 1.0 V using on-chip switch mode

pump (SMP)

❐ Industrial temperature range: –40 °C to +85 °C

■ Advanced peripherals (PSoC^®blocks)

❐ Four analog Type E PSoC blocks provide:

• Two comparators with digital-to-analog converter (DAC)

references

■ Versatile analog mux

❐ Common internal analog bus

❐ Simultaneous connection of I/O combinations

❐ Capacitive sensing application capability

■ Additional system resources

❐ I²C ^[2]master, slave, and multi-master to 400 kHz

❐ Watchdog and sleep timers

❐ User-configurable low-voltage detection (LVD)

❐ Integrated supervisory circuit

❐ On-chip precision voltage reference

• Single or dual 10-bit 28 channel analog-to-digital

converters (ADC)

❐ Four digital PSoC blocks provide:

• 8- to 32-bit timers, counters, and pulse width modulators

(PWMs)

Logic Block Diagram

• Cyclical redundancy check (CRC) and pseudo random

sequence (PRS) modules

• Full-duplex universal asynchronous receiver transmitter

(UART), serial peripheral interface (SPI) master or slave

• Connectable to all general purpose I/O (GPIO) pins

❐ Complex peripherals by combining blocks

■ Flexible on-chip memory

❐ 8 KB flash program storage 50,000 erase/write cycles

❐ 512 bytes static random access memory (SRAM) data

storage

❐ In-system serial programming (ISSP)

❐ Partial flash updates

❐ Flexible protection modes

❐ EEPROM emulation in flash

■ Complete development tools

❐ Free development software (PSoC Designer™)

❐ Full-featured, in-circuit emulator (ICE) and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128-KB trace memory

■ Precision, programmable clocking

❐ Internal ±2.5% 24- / 48-MHz main oscillator ^[1]

❐ Internal oscillator for watchdog and sleep

■ Programmable pin configurations

❐ 25-mA sink, 10-mA source on all GPIOs

❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes

on all GPIOs

Errata: For information on silicon errata, see “Errata” on page 49. Details include trigger conditions, devices affected, and proposed workaround.

Notes

1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

2

2. Errata:The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is transitioning in to or out of sleep

mode.

Cypress Semiconductor Corporation

Document Number: 38-12025 Rev. AD

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 15, 2014

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Contents

PSoC Functional Overview ..............................................3

The PSoC Core ...........................................................3

The Digital System ......................................................3

The Analog System .....................................................4

Additional System Resources .....................................4

PSoC Device Characteristics ......................................5

Getting Started ..................................................................5

Application Notes ........................................................5

Development Kits ........................................................5

Training .......................................................................5

CYPros Consultants ....................................................5

Solutions Library ..........................................................5

Technical Support .......................................................5

Development Tools ..........................................................6

PSoC Designer Software Subsystems ........................6

Designing with PSoC Designer .......................................7

Select User Modules ...................................................7

Configure User Modules ..............................................7

Organize and Connect ................................................7

Generate, Verify, and Debug .......................................7

Pin Information .................................................................8

16-pin Part Pinout ........................................................8

Pin Definitions .............................................................8

20-pin Part Pinout ........................................................9

Pin Definitions .............................................................9

28-pin Part Pinout ......................................................10

Pin Definitions ...........................................................10

32-pin Part Pinout ......................................................11

Pin Definitions ...........................................................12

56-pin Part Pinout ......................................................13

Pin Definitions ...........................................................14

Register Reference .........................................................16

Register Conventions ................................................16

Register Mapping Tables ..........................................16

Absolute Maximum Ratings ..........................................19

Operating Temperature ..................................................19

Electrical Specifications ................................................20

DC Electrical Characteristics .....................................20

AC Electrical Characteristics .....................................26

Packaging Information ...................................................34

Thermal Impedances .................................................38

Solder Reflow Specifications .....................................38

Development Tool Selection .........................................39

Software ....................................................................39

Development Kits ......................................................39

Evaluation Tools ........................................................39

Device Programmers .................................................40

Accessories (Emulation and Programming) ..............40

Ordering Information ......................................................41

Ordering Code Definitions .........................................42

Acronyms ........................................................................43

Reference Documents ....................................................43

Document Conventions .................................................44

Units of Measure .......................................................44

Numeric Conventions ................................................44

Glossary ..........................................................................44

Errata ...............................................................................49

Part Numbers Affected ..............................................49

CY8C21234 Qualification Status ...............................49

CY8C21234 Errata Summary ....................................50

Document History Page .................................................51

Sales, Solutions, and Legal Information ......................55

Worldwide Sales and Design Support .......................55

Products ....................................................................55

PSoC® Solutions ......................................................55

Cypress Developer Community .................................55

Technical Support .....................................................55

Document Number: 38-12025 Rev. AD

Page 2 of 55

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CY8C21334, CY8C21234

The Digital System

PSoC Functional Overview

The digital system consists of four digital PSoC blocks. Each

block is an 8-bit resource that is used alone or combined with

other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which

are called user modules. Digital peripheral configurations

include:

The PSoC family consists of many devices with on-chip

controllers. These devices are designed to replace multiple

traditional MCU-based system components with one low-cost

single-chip programmable component. A PSoC device includes

configurable blocks of analog and digital logic, and

programmable interconnect. This architecture makes it possible

for you to create customized peripheral configurations, to match

the requirements of each individual application. Additionally, a

fast central processing unit (CPU), flash program memory,

SRAM data memory, and configurable I/O are included in a

range of convenient pinouts.

■ PWMs (8- to 32-bit)

■ PWMs with dead band (8- to 32-bit)

■ Counters (8- to 32-bit)

■ Timers (8- to 32-bit)

The PSoC architecture, shown in Figure 1, consists of four main

areas: the core, the system resources, the digital system, and

the analog system. Configurable global bus resources allow

combining all of the device resources into a complete custom

system. Each CY8C21x34 PSoC device includes four digital

blocks and four analog blocks. Depending on the PSoC

package, up to 28 GPIOs are also included. The GPIOs provide

access to the global digital and analog interconnects.

■ UART 8- with selectable parity

■ Serial peripheral interface (SPI) master and slave

■ I²C slave and multi-master ^[4]

■ CRC/generator (8-bit)

■ IrDA

■ PRS generators (8-bit to 32-bit)

The PSoC Core

The digital blocks are connected to any GPIO through a series

of global buses that can route any signal to any pin. The buses

also allow for signal multiplexing and for performing logic

operations. This configurability frees your designs from the

constraints of a fixed peripheral controller.

The PSoC core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and internal main

oscillator (IMO) and internal low speed oscillator (ILO). The CPU

core, called the M8C, is a powerful processor with speeds up to

24 MHz ^[3]. The M8C is a four-million instructions per second

(MIPS) 8-bit Harvard-architecture microprocessor.

Digital blocks are provided in rows of four, where the number of

blocks varies by PSoC device family. This allows the optimum

choice of system resources for your application. Family

resources are shown in Table 1 on page 5.

System resources provide these additional capabilities:

■ Digital clocks for increased flexibility

Figure 1. Digital System Block Diagram

■ I²C ^[4]functionality to implement an I²C master and slave

Port 3

Port 1

Port 2

Port 0

■ An internal voltage reference, multi-master, that provides an

absolute value of 1.3 V to a number of PSoC subsystems

Digital Clocks

From Core

To Analog

System

To System Bus

■ A SMP that generates normal operating voltages from a single

battery cell

DIGITAL SYSTEM

■ Various system resets supported by the M8C

The digital system consists of an array of digital PSoC blocks that

may be configured into any number of digital peripherals. The

digital blocks are connected to the GPIOs through a series of

global buses. These buses can route any signal to any pin,

freeing designs from the constraints of a fixed peripheral

controller.

Digital PSoC Block Array

Row 0

4

DBB00

DBB01 DCB02 DCB03

8

The analog system consists of four analog PSoC blocks,

supporting comparators, and analog-to-digital conversion up to

10 bits of precision.

8

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Notes

3. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

2

4. Errata:The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is transitioning in to or out of sleep

mode.

Document Number: 38-12025 Rev. AD

Page 3 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

The Analog Multiplexer System

The Analog System

The analog mux bus can connect to every GPIO pin. Pins may

be connected to the bus individually or in any combination. The

bus also connects to the analog system for analysis with

comparators and analog-to-digital converters. An additional 8:1

analog input multiplexer provides a second path to bring Port 0

pins to the analog array.

The analog system consists of four configurable blocks that allow

for the creation of complex analog signal flows. Analog

peripherals are very flexible and can be customized to support

specific application requirements. Some of the common PSoC

analog functions for this device (most available as user modules)

are:

Switch-control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

■ ADCs (single or dual, with 8-bit or 10-bit resolution)

■ Pin-to-pin comparator

■ Single-ended comparators (up to two) with absolute (1.3 V)

reference or 8-bit DAC reference

■ Track pad, finger sensing

■ 1.3-V reference (as a system resource)

■ Chip-wide mux that allows analog input from any I/O pin

■ Crosspoint connection between any I/O pin combinations

In most PSoC devices, analog blocks are provided in columns of

three, which includes one continuous time (CT) and two switched

capacitor (SC) blocks. The CY8C21x34 devices provide limited

functionality Type E analog blocks. Each column contains one

CT Type E block and one SC Type E block. Refer to the PSoC

Technical Reference Manual for detailed information on the

CY8C21x34’s Type E analog blocks.

Additional System Resources

System resources, some of which are listed in the previous

sections, provide additional capability useful to complete

systems. Additional resources include a switch-mode pump,

low-voltage detection, and power-on-reset (POR).

Figure 2. Analog System Block Diagram

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks may be routed

to both the digital and analog systems. Additional clocks can

be generated using digital PSoC blocks as clock dividers.

Array Input

■ The I²C ^[5]module provides 100- and 400-kHz communication

over two wires. Slave, master, and multi-master modes are all

supported.

Configuration

■ LVD interrupts can signal the application of falling voltage

levels, while the advanced POR circuit eliminates the need for

a system supervisor.

ACI0[1:0]

ACI1[1:0]

■ An internal 1.3-V reference provides an absolute reference for

the analog system, including ADCs and DACs.

All I/O

X

■ An integrated switch-mode pump generates normal operating

voltages from a single 1.2-V battery cell, providing a low cost

boost converter.

ACOL1MUX

X

Analog Mux Bus

■ Versatile analog multiplexer system.

X

Array

ACE00

ACE01

ASE11

ASE10

Note

2

5. Errata:The I C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep

mode.

Document Number: 38-12025 Rev. AD

Page 4 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4

analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is

highlighted in Table 1.

Table 1. PSoC Device Characteristics

PSoC Part

Number

Digital

I/O

Digital

Rows

Digital

Blocks

Analog

Inputs

Analog

SRAM

Size

Flash

Size

Outputs Columns Blocks

CY8C29x66

CY8C28xxx

up to 64

up to 44

4

16

up to 12

up to 44

4

12

2 K

1 K

32 K

16 K

up to 3

up to 12

up to 4

up to 6

up to

12 + 4

[6]

CY8C27x43

CY8C24x94

CY8C24x23A

CY8C23x33

CY8C22x45

CY8C21x45

CY8C21x34

CY8C21x23

CY8C20x34

CY8C20xx6

up to 44

up to 56

up to 24

up to 26

up to 38

up to 24

up to 28

up to 16

up to 28

up to 36

2

1

2

1

0

8

4

8

4

0

up to 12

up to 48

up to 12

up to 38

up to 24

up to 28

4

2

0

4

2

4

2

0

12

6

256

1 K

16 K

4 K

6

256

4

256

8 K

[6]

6

1 K

16 K

8 K

[6]

6

512

[6]

4

512

8 K

[6]

up to

8

4

256

4 K

[6,7]

up to 28

up to 36

3

512

8 K

[6,7]

3

up to 2 K

up to 32 K

covers a wide variety of topics and skill levels to assist you in

your designs.

Getting Started

For in-depth information, along with detailed programming

details, see the PSoC^®Technical Reference Manual.

CYPros Consultants

Certified PSoC consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC consultant go to the CYPros Consultants web site.

For up-to-date ordering, packaging, and electrical specification

information, see the latest PSoC device datasheets on the web.

Application Notes

Solutions Library

Cypress application notes are an excellent introduction to the

wide variety of possible PSoC designs.

Visit our growing library of solution focused designs. Here you

can find various application designs that include firmware and

hardware design files that enable you to complete your designs

quickly.

Development Kits

PSoC Development Kits are available online from and through a

growing number of regional and global distributors, which

include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and

Newark.

Technical Support

Technical support – including a searchable Knowledge Base

articles and technical forums – is also available online. If you

cannot find an answer to your question, call our Technical

Support hotline at 1-800-541-4736.

Training

Free PSoC technical training (on demand, webinars, and

workshops), which is available online via www.cypress.com,

Notes

6. Limited analog functionality.

®

7. Two analog blocks and one CapSense .

Document Number: 38-12025 Rev. AD

Page 5 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Code Generation Tools

Development Tools

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range

of debugging tools. You can develop your design in C, assembly,

or a combination of the two.

PSoC Designer™ is the revolutionary integrated design

environment (IDE) that you can use to customize PSoC to meet

your specific application requirements. PSoC Designer software

accelerates system design and time to market. Develop your

applications using a library of precharacterized analog and digital

peripherals (called user modules) in a drag-and-drop design

environment. Then, customize your design by leveraging the

dynamically generated application programming interface (API)

libraries of code. Finally, debug and test your designs with the

integrated debug environment, including in-circuit emulation and

standard software debug features. PSoC Designer includes:

Assemblers. The assemblers allow you to merge assembly

code seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and are

linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices. The

optimizing C compilers provide all of the features of C, tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

■ Application editor graphical user interface (GUI) for device and

user module configuration and dynamic reconfiguration

■ Extensive user module catalog

■ Integrated source-code editor (C and assembly)

■ Free C compiler with no size restrictions or time limits

■ Built-in debugger

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow you to read and program and

read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints,

and provide program run, halt, and step control. The debugger

also allows you to create a trace buffer of registers and memory

locations of interest.

■ In-circuit emulation

■ Built-in support for communication interfaces:

2

[8]

❐ Hardware and software I C slaves and masters

❐ Full-speed USB 2.0

❐ Up

to

four

full-duplex

universal

asynchronous

receiver/transmitters (UARTs), SPI master and slave, and

wireless

Online Help System

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional

subsystem has its own context-sensitive help. This system also

provides tutorials and links to FAQs and an online support Forum

to aid the designer.

PSoC Designer supports the entire library of PSoC 1 devices and

runs on Windows XP, Windows Vista, and Windows 7.

PSoC Designer Software Subsystems

Design Entry

In-Circuit Emulator

In the chip-level view, choose a base device to work with. Then

select different onboard analog and digital components that use

the PSoC blocks, which are called user modules. Examples of

user modules are ADCs, DACs, amplifiers, and filters. Configure

the user modules for your chosen application and connect them

to each other and to the proper pins. Then generate your project.

This prepopulates your project with APIs and libraries that you

can use to program your application.

A

low-cost, high-functionality in-circuit emulator (ICE) is

available for development support. This hardware can program

single devices.

The emulator consists of a base unit that connects to the PC

using a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24 MHz) operation.

The tool also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

reconfiguration makes it possible to change configurations at run

time. In essence, this allows you to use more than 100 percent

of PSoC’s resources for an application.

Note

2

8. Errata:The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is transitioning in to or out of sleep

mode.

Document Number: 38-12025 Rev. AD

Page 6 of 55

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CY8C21334, CY8C21234

specifications. Each datasheet describes the use of each user

module parameter, and other information you may need to

successfully implement your design.

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

The PSoC development process is summarized in four steps:

Organize and Connect

You build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins. You perform the

selection, configuration, and routing so that you have complete

control over all on-chip resources.

Generate, Verify, and Debug

1. Select User Modules.

When you are ready to test the hardware configuration or move

on to developing code for the project, you perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system. The

generated code provides application programming interfaces

(APIs) with high-level functions to control and respond to

hardware events at run-time and interrupt service routines that

you can adapt as needed.

2. Configure User Modules.

3. Organize and Connect.

4. Generate, Verify, and Debug.

Select User Modules

PSoC Designer provides a library of prebuilt, pretested hardware

peripheral components called “user modules.” User modules

make selecting and implementing peripheral devices, both

analog and digital, simple.

A complete code development environment allows you to

develop and customize your applications in either C, assembly

language, or both.

Configure User Modules

Each user module that you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a PWM

User Module configures one or more digital PSoC blocks, one

for each 8 bits of resolution. The user module parameters permit

you to establish the pulse width and duty cycle. Configure the

parameters and properties to correspond to your chosen

application. Enter values directly or by selecting values from

drop-down menus. All the user modules are documented in

datasheets that may be viewed directly in PSoC Designer or on

the Cypress website. These user module datasheets explain the

internal operation of the user module and provide performance

The last step in the development process takes place inside

PSoC Designer’s debugger (access by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full speed. PSoC Designer debugging

capabilities rival those of systems costing many times more. In

addition to traditional single-step, run-to-breakpoint, and

watch-variable features, the debug interface provides a large

trace buffer and allows you to define complex breakpoint events.

These include monitoring address and data bus values, memory

locations, and external signals.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Pin Information

The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with

a “P”) is capable of Digital I/O and connection to the common analog bus. However, V , V , SMP, and XRES are not capable of

SS

DD

Digital I/O.

16-pin Part Pinout

Figure 3. CY8C21234 16-pin PSoC Device

A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

SMP

V_DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

SOIC

V_SS

P1[4], EXTCLK, M

P1[2], M

M, I2C SCL, P1[1]

V_SS

P1[0], I2C SDA, M

Pin Definitions

CY8C21234 16-pin SOIC

Type

Pin No.

Name

P0[7]

Description

Digital

Analog

1

I/O

I, M

Analog column mux input

2

I/O

I, M

P0[5]

P0[3]

P0[1]

SMP

3

I/O

Analog column mux input, integrating input

4

I/O

Analog column mux input, integrating input

5

Power

I/O

Switch-mode pump (SMP) connection to required external components

[9]

6

V

Ground connection

SS

2

[10]

7

M

P1[1]

I C serial clock (SCL), ISSP-SCLK

[9]

8

Power

I/O

V

Ground connection

2

SS

[10]

9

M

P1[0]

P1[2]

P1[4]

P0[0]

P0[2]

P0[4]

P0[6]

I C serial data (SDA), ISSP-SDATA

10

11

12

13

14

15

16

I/O

M

I/O

M

Optional external clock input (EXTCLK)

Analog column mux input

Supply voltage

I/O

I, M

I/O

Power

V

DD

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Notes

9. All V pins should be brought out to one common GND plane.

SS

10. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

20-pin Part Pinout

Figure 4. CY8C21334 20-pin PSoC Device

A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

V_SS

V_DD

20

19

18

17

16

15

14

13

12

11

1

2

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

XRES

3

4

5

SSOP

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

6

P1[6], M

7

P1[4], EXTCLK, M

P1[2], M

8

M, I2C SCL, P1[1]

V_SS

9

P1[0], I2C SDA, M

10

Pin Definitions

CY8C21334 20-pin SSOP

Type

Pin No.

Name

Description

Digital

I/O

Analog

1

I, M

P0[7]

P0[5]

P0[3]

P0[1]

Analog column mux input

2

I/O

3

I/O

Analog column mux input, integrating input

4

I/O

Analog column mux input, integrating input

[11]

5

Power

I/O

V

Ground connection

SS

2

6

M

P1[7]

P1[5]

P1[3]

P1[1]

I C SCL

2

7

I/O

I C SDA

8

I/O

2

[12]

9

I/O

I C SCL, ISSP-SCLK

[11]

10

11

12

13

14

15

16

17

18

19

20

Power

I/O

V

Ground connection

2

SS

[12]

M

P1[0]

P1[2]

P1[4]

P1[6]

XRES

P0[0]

P0[2]

P0[4]

P0[6]

I C SDA, ISSP-SDATA

I/O

Optional external clock input (EXTCLK)

I/O

Input

I/O

Active high external reset with internal pull-down

Analog column mux input

Supply voltage

I, M

I/O

Power

V

DD

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Notes

11. All V pins should be brought out to one common GND plane.

SS

12. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.

Document Number: 38-12025 Rev. AD

Page 9 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

28-pin Part Pinout

Figure 5. CY8C21534 28-pin PSoC Device

A, I, M, P0[7]

A, I, M, P0[5]

A, I, M, P0[3]

A, I, M, P0[1]

M, P2[7]

V_DD

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

P0[0], A, I, M

P2[6], M

3

4

5

M, P2[5]

6

M, P2[3]

P2[4], M

7

SSOP

M, P2[1]

P2[2], M

8

V_SS

P2[0], M

9

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

XRES

10

11

12

13

14

P1[6], M

P1[4], EXTCLK, M

P1[2], M

M, I2C SCL, P1[1]

V_SS

P1[0], I2C SDA, M

Pin Definitions

CY8C21534 28-pin SSOP

Type

Pin No.

Name

Description

Digital

I/O

Analog

I, M

1

2

3

4

5

6

7

8

9

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

Analog column mux input

I/O

I, M

M

Analog column mux input and column output

I/O

Analog column mux input and column output, integrating input

Analog column mux input, integrating input

I/O

M

I/O

I, M

Direct switched capacitor block input

I/O

[13]

Power

I/O

V

Ground connection

SS

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

M

P1[7]

P1[5]

P1[3]

P1[1]

I C SCL

2

I/O

I C SDA

I/O

2

[14]

I/O

I C SCL, ISSP-SCLK

[13]

Power

I/O

V

Ground connection

2

SS

[14]

M

P1[0]

P1[2]

P1[4]

P1[6]

XRES

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I C SDA, ISSP-SDATA

I/O

Optional external clock input (EXTCLK)

I/O

Input

I/O

Active high external reset with internal pull-down

Direct switched capacitor block input

I, M

M

I/O

Direct switched capacitor block input

I/O

M

I/O

I, M

Analog column mux input

Supply voltage

I/O

Power

V

DD

LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.

Notes

13. All V pins should be brought out to one common GND plane.

SS

14. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.

Document Number: 38-12025 Rev. AD

Page 10 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

32-pin Part Pinout

Figure 6. CY8C21434 32-pin PSoC Device

Figure 7. CY8C21634 32-pin PSoC Device

Figure 8. CY8C21434 32-pin Sawn PSoC Device Sawn

Figure 9. CY8C21634 32-pin Sawn PSoC Device Sawn

A, I, M, P0[1]

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

M, P3[3]

1

2

3

4

5

6

7

8

P0[0], A, I, M

A, I, M, P0[1]

24

1

2

3

4

5

6

7

8

P0[0], A, I, M

24

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

SMP

23 P2[6], M

22 P2[4], M

P2[2], M

21

23 P2[6], M

22 P2[4], M

P2[2], M

21

QFN

(Top View)

QFN

(Top View)

20 P2[0], M

P3[2], M

19

P3[2], M

19

M, P3[1]

M, I2C SCL, P1[7]

Vss

18 P3[0], M

17 XRES

18 P3[0], M

17 XRES

M, I2C SCL, P1[7]

Document Number: 38-12025 Rev. AD

Page 11 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Pin Definitions

[15]

CY8C21434/CY8C21634 32-pin QFN

Type

Pin No.

Name

Description

Digital

I/O

Analog

I, M

1

P0[1]

Analog column mux input, integrating input

2

I/O

M

P2[7]

P2[5]

P2[3]

P2[1]

P3[3]

SMP

P3[1]

3

I/O

4

I/O

5

I/O

6

I/O

In CY8C21434 part

6

Power

I/O

SMP connection to required external components in CY8C21634 part

In CY8C21434 part

7

M

[16]

7

Power

I/O

V

Ground connection in CY8C21634 part

SS

2

8

M

P1[7]

P1[5]

P1[3]

P1[1]

I C SCL

2

9

I/O

I C SDA

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

I/O

2

[17]

I/O

I C SCL, ISSP-SCLK

[16]

Power

I/O

V

Ground connection

SS

2

[17]

M

P1[0]

P1[2]

P1[4]

P1[6]

XRES

P3[0]

P3[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I C SDA, ISSP-SDATA

I/O

Optional external clock input (EXTCLK)

I/O

Input

I/O

Active high external reset with internal pull-down

M

I/O

M

I/O

M

I/O

M

I/O

M

I/O

M

I/O

I, M

Analog column mux input

Supply voltage

I/O

Power

I/O

V

DD

I, M

P0[7]

P0[5]

P0[3]

Analog column mux input

Analog column mux input, integrating input

I/O

[16]

Power

V

Ground connection

SS

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Notes

15. The center pad on the QFN package must be connected to ground (V_SS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must

be electrically floated and not connected to any other signal.

16. All V_SSpins should be brought out to one common GND plane.

17. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.

Document Number: 38-12025 Rev. AD

Page 12 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

56-pin Part Pinout

The 56-pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Figure 10. CY8C21001 56-pin PSoC Device

Vss

56

55

Vdd

1

2

AI, P0[7]

AI, P0[5]

AI, P0[3]

P0[6], AI

P0[4], AI

P0[2], AI

3

4

5

6

54

53

AI, P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

NC

P0[0], AI

P2[6]

52

51

P2[4]

P2[2]

P2[0]

NC

7

8

9

50

49

48

10

47

46

45

44

43

42

41

40

39

38

37

36

35

34

NC

11

12

13

P3[2]

P3[0]

CCLK

HCLK

XRES

NC

OCDE

OCDO

SMP

14

SSOP

15

16

17

Vss

NC

18

19

20

P3[3]

P3[1]

NC

21

22

23

NC

P1[6]

I2C SCL, P1[7]

P1[4], EXTCLK

P1[2]

I2C SDA, P1[5]

24

25

33

32

NC

P1[3]

P1[0], I2C

NC

SDA, SDATA

26

27

28

31

30

SCLK, I2C SCL, P1[1]

Vss

NC

29

Document Number: 38-12025 Rev. AD

Page 13 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Pin Definitions

CY8C21001 56-pin SSOP

Type

Pin No.

Digital

Pin Name

Description

Analog

1

Power

I/O

V

Ground connection

SS

2

I

P0[7]

Analog column mux input

3

I/O

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

NC

Analog column mux input and column output

Analog column mux input

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

I

Direct switched capacitor block input

No connection. Pin must be left floating

OCD even data I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

NC

OCD

Power

I/O

OCDE

OCDO

SMP

OCD odd data output

SMP connection to required external components

[18]

V

Ground connection

SS

[18]

Ground connection

P3[3]

P3[1]

NC

I/O

No connection. Pin must be left floating

NC

2

I/O

P1[7]

P1[5]

NC

I C SCL

2

I C SDA

No connection. Pin must be left floating

I/O

P1[3]

P1[1]

I

FMTEST

2

[19]

I/O

I C SCL, ISSP-SCLK

[18]

Power

V

Ground connection

SS

NC

No connection. Pin must be left floating

NC

2

[19]

I/O

P1[0]

P1[2]

P1[4]

P1[6]

I C SDA, ISSP-SDATA

V

FMTEST

Optional external clock input (EXTCLK)

Notes

18. All V_SSpins should be brought out to one common GND plane.

19. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.

Document Number: 38-12025 Rev. AD

Page 14 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Pin Definitions (continued)

CY8C21001 56-pin SSOP

Type

Pin No.

Pin Name

NC

Description

Digital

Analog

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

No connection. Pin must be left floating

NC

No connection. Pin must be left floating

Active high external reset with internal pull-down

OCD high-speed clock output

NC

Input

XRES

HCLK

CCLK

P3[0]

P3[2]

NC

OCD

I/O

OCD CPU clock output

I/O

No connection. Pin must be left floating

NC

I/O

I

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I/O

I

Analog column mux input

I/O

Analog column mux input and column output

Analog column mux input

I/O

Power

V

Supply voltage

DD

LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.

Document Number: 38-12025 Rev. AD

Page 15 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Register Reference

This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, see the PSoC Technical Reference

Manual.

Register Conventions

The register conventions specific to this section are listed in Table 2.

Table 2. Register Conventions

Convention

Description

Read register or bit(s)

R

W

L

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

C

#

Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into

two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the

XOI bit is set to 1, the user is in Bank 1.

Note In the following register mapping tables, blank fields are reserved and must not be accessed.

Document Number: 38-12025 Rev. AD

Page 16 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 3. Register Map 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

40

Name

ASE10CR0

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

C0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

PRT0IE

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

ASE11CR0

RW

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

CUR_PP

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

STK_PP

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

IDX_PP

RW

#

MVR_PP

MVW_PP

I2C_CFG

I2C_SCR

I2C_DR

RW

#

I2C_MSCR

INT_CLR0

INT_CLR1

RW

INT_CLR3

INT_MSK3

RW

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

#

AMX_IN

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

INT_MSK0

INT_MSK1

INT_VC

RW

RC

W

RW

#

AMUXCFG

PWM_CR

RES_WDT

#

CMP_CR0

CMP_CR1

#

W

RW

#

RW

DEC_CR0

DEC_CR1

RW

#

ADC0_CR

ADC1_CR

#

W

RW

#

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

W

RW

#

RDI0RI

RW

RDI0SYN

RDI0IS

ACE00CR1

ACE00CR2

RW

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

ACE01CR1

ACE01CR2

RW

CPU_F

RL

DAC_D

RW

#

CPU_SCR1

CPU_SCR0

#

Blank fields are reserved and must not be accessed.

# Access is bit specific.

Document Number: 38-12025 Rev. AD

Page 17 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 4. Register Map 1 Table: Configuration Space

Name

PRT0DM0

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

ASE10CR0

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

RW

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

RW

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

ASE11CR0

RW

GDI_O_IN

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

RW

GDI_E_IN

GDI_O_OU

GDI_E_OU

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

RW

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

RW

R

DBB00FN

DBB00IN

DBB00OU

RW

CLK_CR0

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

RW

CLK_CR1

ABF_CR0

AMD_CR0

CMP_GO_EN

DBB01FN

DBB01IN

DBB01OU

RW

VLT_CMP

ADC0_TR

ADC1_TR

RW

AMD_CR1

ALT_CR0

RW

DCB02FN

DCB02IN

DCB02OU

RW

IMO_TR

ILO_TR

BDG_TR

ECO_TR

W

RW

W

CLK_CR3

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RW

DCB03FN

DCB03IN

DCB03OU

RW

RDI0RI

RW

RDI0SYN

RDI0IS

ACE00CR1

ACE00CR2

RW

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

ACE01CR1

ACE01CR2

RW

CPU_F

RL

FLS_PR1

RW

DAC_CR

RW

#

CPU_SCR1

CPU_SCR0

#

Blank fields are reserved and must not be accessed.

# Access is bit specific.

Document Number: 38-12025 Rev. AD

Page 18 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Absolute Maximum Ratings

Symbol

Description

Storage temperature

Min

Typ

Max

Units

Notes

T

–55

25

+100

°C

Higher storage temperatures

reduce data retention time.

Recommended storage

STG

temperature is +25 °C ± 25 °C.

Extended duration storage

temperatures above 65 °C

degrade reliability.

T

Bake temperature

–

125

–

See

package

label

°C

BAKETEMP

BAKETIME

t

Bake time

See

package

label

72

Hours

T

Ambient temperature with power applied

–40

–

+85

°C

V

A

V

Supply voltage on V relative to V

SS

–0.5

+6.0

DD

IO

DD

DC input voltage

V

– 0.5

V

+ 0.5

V

SS

DD

DC voltage applied to tri-state

Maximum current into any port pin

Electrostatic discharge voltage

Latch-up current

V

IOZ

MIO

I

–25

+50

mA

V

ESD

LU

2000

–

Human body model ESD.

200

mA

Operating Temperature

Symbol

Description

Ambient temperature

Junction temperature

Min

–40

Typ

Max

Units

Notes

T

–

+85

°C

A

T

+100

The temperature rise from ambient to

junction is package specific. SeeTable

29 on page 38. You must limit the

power consumption tocomply with this

requirement.

J

Document Number: 38-12025 Rev. AD

Page 19 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up-to-date electrical specifications,

visit the Cypress web site at http://www.cypress.com.

Specifications are valid for –40 C  T  85 C and T  100 C as specified, except where noted.

A

J

Refer to Table 16 on page 26 for the electrical specifications for the IMO using SLIMO mode.

Figure 11. Voltage versus CPU Frequency

Figure 14. IMO Frequency Trim Options

5.25

4.75

5.25

4.75

SLIMO

Mode=1

Mode=0

3.60

3.00

2.40

SLIMO

Mode=1

Mode=0

3.00

2.40

SLIMO

Mode=1 Mode=1

93 kHz

12 MHz

CPU Frequency

24 MHz

3 MHz

93 kHz

6 MHz

12 MHz

24 MHz

IMO Frequency

DC Electrical Characteristics

DC Chip-Level Specifications

Table 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters

A

are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 5. DC Chip-level Specifications

Symbol

Description

Supply voltage

Supply current, IMO = 24 MHz

Min

2.40

–

Typ

–

3

Max

5.25

4

Units

V

mA

Notes

See Table 13 on page 24

Conditions are V = 5.0 V,

DD

T = 25 °C, CPU = 3 MHz,

48 MHz disabled. VC1 = 1.5 MHz,

VC2 = 93.75 kHz, VC3 = 0.366 kHz

V

DD

I

DD

A

Supply current, IMO = 6 MHz using

SLIMO mode.

–

1.2

1.1

2

mA

Conditions are V = 3.3 V,

DD3

DD

T = 25 °C, CPU = 3 MHz, clock

A

doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz

Supply current, IMO = 6 MHz using

SLIMO mode.

1.5

Conditions are V = 2.55 V,

DD27

DD

T = 25 °C, CPU = 3 MHz, clock

A

doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz

I

Sleep (mode) current with POR, LVD,

sleep timer, WDT, and internal slow

oscillator active. Mid temperature range.

Sleep (mode) current with POR, LVD,

Sleep Timer, WDT, and internal slow

oscillator active.

–

2.6

2.8

4

5

µA

V

= 2.55 V, 0 °C T  40 °C

SB27

DD

A

= 3.3 V, –40 °C T  85 °C

SB

A

V

Reference voltage (Bandgap)

Analog ground

1.28

1.16

1.30

1.32

1.33

V

Trimmed for appropriate V

DD

REF

DD

V

= 3.0 V to 5.25 V

Trimmed for appropriate V

= 2.4 V to 3.0 V

REF27

V

DD

AGND

V

– 0.003

V

+ 0.003

REF

Document Number: 38-12025 Rev. AD

Page 20 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

DC General-Purpose I/O Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively.

A

Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.

Table 6. 5-V and 3.3-V DC GPIO Specifications

Symbol

Description

Min

4

Typ

5.6

–

Max

Units

k

Notes

R

Pull-up resistor

8

–

PU

PD

OH

R

Pull-down resistor

High output level

4

k

V

– 1.0

V

I

= 10 mA, V = 4.75 to 5.25 V

OH DD

DD

(8 total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])

V

Low output level

–

0.75

V

I

= 25 mA, V = 4.75 to 5.25 V

OL

OL DD

(8 total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5]))

I

High level source current

Low level sink current

10

25

–

mA

V

= V – 1.0 V, see the limitations

OH DD

OH

of the total current in the note for V

OH

V

= 0.75 V, see the limitations of the

OL

total current in the note for V

OL

V

Input low level

–

2.1

–

0.8

V

= 3.0 to 5.25

IL

IH

H

DD

Input high level

Input hysteresis

60

1

–

mV

nA

pF

I

Input leakage (absolute value)

Capacitive load on pins as input

–

Gross tested to 1 µA

IL

C

–

3.5

10

Package and pin dependent

Temp = 25 °C

IN

C

Capacitive load on pins as output

–

3.5

10

pF

Package and pin dependent

Temp = 25 °C

OUT

Table 7. 2.7-V DC GPIO Specifications

Symbol Description

Min

4

Typ

5.6

–

Max

Units

k

Notes

R

Pull-up resistor

8

–

PU

PD

OH

R

Pull-down resistor

High output level

4

V

– 0.4

V

I

= 2.5 mA (6.25 Typ), V = 2.4 to

OH DD

3.0 V (16 mA maximum, 50 mA Typ

combined I budget)

DD

OH

V

Low output level

–

0.75

–

V

I

= 10 mA, V = 2.4 to 3.0 V (90 mA

OL

OL DD

maximum combined I budget)

OL

I

High level source current

Low level sink current

2.5

10

mA

V

= V – 0.4 V, see the limitations

OH DD

OH

of the total current in the note for V

OH

–

V

= 0.75 V, see the limitations of the

OL

total current in the note for V

OL

V

Input low level

–

2.0

–

0.75

–

V

= 2.4 to 3.0

IL

IH

H

DD

Input high level

Input hysteresis

90

1

–

mV

nA

pF

I

Input leakage (absolute value)

Capacitive load on pins as input

–

Gross tested to 1 µA

IL

C

–

3.5

10

Package and pin dependent

Temp = 25 °C

IN

C

Capacitive load on pins as output

–

3.5

10

pF

Package and pin dependent

Temp = 25 °C

OUT

Document Number: 38-12025 Rev. AD

Page 21 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

DC Operational Amplifier Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively.

A

Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 8. 5-V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

10

Max

15

–

Units

mV

Notes

V

Input offset voltage (absolute value)

Average input offset voltage drift

OSOA

TCV

–

µV/°C

pA

OSOA

I

Input leakage current (Port 0 analog pins 7-to-1)

Input leakage current (Port 0, Pin 0 analog pin)

Input capacitance (Port 0 analog pins)

–

200

50

–

Gross tested to 1 µA

EBOA

EBOA00

–

nA

C

–

4.5

9.5

pF

Package and pin dependent.

Temp = 25 °C

INOA

V

Common mode voltage range

0.0

–

V

– 1.0

DD

V

CMOA

G

Open loop gain

–

80

10

–

dB

µA

OLOA

I

Amplifier supply current

30

SOA

Table 9. 3.3-V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

10

Max

15

–

Units

mV

Notes

V

Input offset voltage (absolute value)

Average input offset voltage drift

OSOA

TCV

–

µV/°C

pA

OSOA

I

Input leakage current (Port 0 analog pins)

Input leakage current (Port 0, Pin 0 analog pin)

Input capacitance (Port 0 analog pins)

–

200

50

–

Gross tested to 1 µA

EBOA

EBOA00

–

nA

C

–

4.5

9.5

pF

Package and pin dependent.

Temp = 25 °C

INOA

V

Common mode voltage range

Open loop gain

0

–

V

– 1.0

DD

V

CMOA

G

80

10

–

dB

µA

OLOA

I

Amplifier supply current

30

SOA

Table 10. 2.7-V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

10

Max

15

–

Units

mV

Notes

V

Input offset voltage (absolute value)

Average input offset voltage drift

OSOA

TCV

–

µV/°C

pA

OSOA

I

Input leakage current (Port 0 analog pins)

Input leakage current (Port 0, Pin 0 analog pin)

Input capacitance (Port 0 analog pins)

–

200

50

–

Gross tested to 1 µA

EBOA

EBOA00

–

nA

C

–

4.5

9.5

pF

Package and pin dependent.

Temp = 25 °C

INOA

V

Common mode voltage range

Open loop gain

0

–

V

– 1.0

DD

V

CMOA

G

80

10

–

dB

µA

OLOA

I

Amplifier supply current

30

SOA

Document Number: 38-12025 Rev. AD

Page 22 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

DC Switch Mode Pump Specifications

Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters

A

are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Figure 12. Basic Switch Mode Pump Circuit

D1

Vdd

V_PUMP

L₁

SMP

Vss

+

C1

V_BAT

Battery

PSoC

Table 11. DC Switch Mode Pump (SMP) Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V

5 V output voltage from pump

4.75

3.00

2.45

5.0

5.25

V

Configured as in Note 20

Average, neglecting ripple

SMP trip voltage is set to 5.0 V

PUMP5V

3.3 V output voltage from pump

2.6 V output voltage from pump

Available output current

3.25

2.55

3.60

2.80

Configured as in Note 20

Average, neglecting ripple.

SMP trip voltage is set to 3.25 V

PUMP3V

PUMP2V

PUMP

Configured as in Note 20

Average, neglecting ripple.

SMP trip voltage is set to 2.55 V

I

Configured as in Note 20

V

= 1.8 V, V

= 1.5 V, V

= 1.3 V, V

= 5.0 V

= 3.25 V

= 2.55 V

5

8

–

mA

SMP trip voltage is set to 5.0 V

SMP trip voltage is set to 3.25 V

SMP trip voltage is set to 2.55 V

BAT

PUMP

V

Input voltage range from battery

1.8

1.0

1.2

–

5.0

3.3

2.8

–

V

Configured as in Note 20

BAT5V

SMP trip voltage is set to 5.0 V

Input voltage range from battery

Configured as in Note 20

SMP trip voltage is set to 3.25 V

BAT3V

Input voltage range from battery

Configured as in Note 20

SMP trip voltage is set to 2.55 V

BAT2V

Minimum input voltage from battery to start pump

Configured as in Note 20

BATSTART

0 C  T  100. 1.25 V at

A

T = –40 °C

A

V

Line regulation (over Vi range)

Load regulation

–

5

–

%V

Configured as in Note 20

PUMP_Line

PUMP_Load

PUMP_Ripple

O

V

is the “V Value for PUMP Trip”

O

DD

specified by the VM[2:0] setting in

the DC POR and LVD Specification,

Table 13 on page 24

%V

Configured as in Note 20

O

V

is the “V Value for PUMP Trip”

O

DD

specified by the VM[2:0] setting in

the DC POR and LVD Specification,

Table 13 on page 24

Output voltage ripple (depends on cap/load)

Efficiency

–

100

50

–

mVpp Configured as in Note 20

Load is 5 mA

E

35

%

Configured as in Note 20

Load is 5 mA. SMP trip voltage is set

to 3.25 V

3

Note

20. L₁= 2 mH inductor, C₁= 10 mF capacitor, D₁= Schottky diode. See Figure 12 on page 23.

Document Number: 38-12025 Rev. AD

Page 23 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 11. DC Switch Mode Pump (SMP) Specifications (continued)

Symbol

Description

Min

Typ

Max

Units

Notes

For I load = 1mA, V

E

Efficiency

35

80

–

%

= 2.55 V,

PUMP

2

V

= 1.3 V,

BAT

10 µH inductor, 1 µF capacitor, and

Schottky diode

F

Switching frequency

Switching duty cycle

–

1.3

50

–

MHz

%

PUMP

DC

PUMP

DC Analog Mux Bus Specifications

Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters

A

are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 12. DC Analog Mux Bus Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

2.4 V V 2.7 V

R

Switch resistance to common analog bus

–

400

800



V

 2.7 V

DD

SW

DD

Resistance of initialization switch to V

–

800



VDD

DD

DC POR and LVD Specifications

Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters

A

are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 13. DC POR and LVD Specifications

Symbol

Description

value for PPOR trip

Min

Typ

Max

Units

Notes

V

must be greater than or equal to

DD

V

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

–

2.36

2.82

4.55

2.40

2.95

4.70

V

2.5 V during startup, the reset from

the XRES pin, or reset from

watchdog

PPOR0

PPOR1

PPOR2

V

value for LVD trip

DD

[21]

[22]

V

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

2.40

2.85

2.95

3.06

4.37

4.50

4.62

4.71

2.45

2.92

3.02

3.13

4.48

4.64

4.73

4.81

2.51

2.99

V

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

3.09

3.20

4.55

4.75

4.83

4.95

V

value for pump trip

DD

[23]

V

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

2.45

2.96

3.03

3.18

4.54

4.62

4.71

4.89

2.55

3.02

3.10

3.25

4.64

4.73

4.82

5.00

2.62

V

PUMP0

PUMP1

PUMP2

PUMP3

PUMP4

PUMP5

PUMP6

PUMP7

3.09

3.16

[24]

3.32

4.74

4.83

4.92

5.12

Notes

21. Always greater than 50 mV above V_PPOR(PORLEV = 00) for falling supply.

22. Always greater than 50 mV above V_PPOR(PORLEV = 01) for falling supply.

23. Always greater than 50 mV above V_LVD0

24. Always greater than 50 mV above V_LVD3

.

Document Number: 38-12025 Rev. AD

Page 24 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

DC Programming Specifications

Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters

A

are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 14. DC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

V

for programming and erase

4.5

5

5.5

V

This specification applies to the

functional requirements of external

programmer tools

DDP

DD

Low V for verify

2.4

5.1

2.7

2.5

5.2

2.6

5.3

V

This specification applies to the

functional requirements of external

programmer tools

DDLV

DDHV

DD

High V for verify

This specification applies to the

functional requirements of external

programmer tools

DD

Supply voltage for flash write operation

5.25

This specification applies to this

device when it is executing internal

flash writes

DDIWRITE

I

Supply current during programming or verify

Input low voltage during programming or verify

–

5

–

25

0.8

–

mA

V

DDP

V

ILP

Input high voltage during programming or

verify

2.2

V

IHP

I

Input current when applying V to P1[0] or

–

0.2

1.5

mA

V

Driving internal pull-down resistor

ILP

IHP

ILP

P1[1] during programming or verify

Input current when applying V

to P1[0] or

IHP

P1[1] during programming or verify

V

Output low voltage during programming or

verify

V

+ 0.75

OLV

SS

Output high voltage during programming or

verify

V

– 1.0

V

OHV

DD

[25]

Flash

Flash endurance (per block)

50,000

–

Erase/write cycles per block

Erase/write cycles

ENPB

ENT

DR

[26]

Flash endurance (total)

1,800,000

10

Flash data retention

Years

DC I²C Specifications

Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters

A

are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

[27]

Table 15. DC I²C Specifications

Symbol

Description

Min

Typ

–

Max

Units

Notes

V

Input low level

Input high level

–

0.3 × V

V

2.4 V V 3.6 V

ILI2C

DD

–

0.25 × V

–

4.75 V V 5.25 V

DD

0.7 × V

–

2.4 V V 5.25 V

IHI2C

DD

Notes

25. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V,

and 4.75 V to 5.25 V.

26. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36×2

blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and ensure that no

single block ever sees more than 50,000 cycles). For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result

to the temperature argument before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC^®Flash) for more information.

27. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I²C GPIO pins also meet the above specs.

Document Number: 38-12025 Rev. AD

Page 25 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC Electrical Characteristics

AC Chip-Level Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively.

A

Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 16. 5-V and 3.3-V AC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

[28]

[29,30]

F

IMO frequency for 24 MHz

23.4

24

24.6

MHz Trimmed for 5 V or 3.3 V

operation using factory trim

values. See Figure 14 on

IMO24

page 20. SLIMO mode = 0

[28]

[29,30]

[29]

IMO frequency for 6 MHz

5.52

6

6.48

MHz Trimmed for 5 V or 3.3 V

operation using factory trim

values. See Figure 14 on

IMO6

CPU1

page 20. SLIMO mode = 1

CPU frequency (5 V nominal)

CPU frequency (3.3 V nominal)

0.091

24

24.6

MHz 24 MHz only for

SLIMO mode = 0

[30]

F

0.091

0

12

48

12.3

MHz SLIMO mode = 0

CPU2

BLK5

0

[29,31]

Digital PSoC block frequency (5 V nominal)

49.2

MHz Refer to AC Digital Block

Specifications on page 29

[31]

F

Digital PSoC block frequency (3.3 V nominal)

ILO frequency

0

15

5

24

32

–

24.6

MHz

kHz

BLK33

32K1

64

ILO untrimmed frequency

100

kHz

After a reset and before the

M8C starts to run, the ILO is

not trimmed. See the system

resets section of the PSoC

Technical Reference Manual

for details on this timing

32K_U

t

External reset pulse width

24 MHz duty cycle

10

40

–

50

–

60

80

–

s

%

XRST

DC24M

DC

ILO duty cycle

20

50

%

ILO

Step24M

Fout48M

24 MHz trim step size

48 MHz output frequency

–

50

kHz

[29,30]

46.8

48.0

49.2

MHz Trimmed. Using factory trim

values

F

Maximum frequency of signal on row input or

row output.

–

12.3

250

100

MHz

MAX

SR

Power supply slew rate

V/ms

ms

V

slew rate during

POWER_UP

POWERUP

DD

power-up

t

Time from end of POR to CPU executing code

16

Power-up from 0 V. See the

System Resets section of the

PSoC Technical Reference

Manual

[32]

t

24-MHz IMO cycle-to-cycle jitter (RMS)

–

200

300

700

900

ps

jit_IMO

24-MHz IMO long term N cycle-to-cycle jitter

N = 32

[32]

(RMS)

[32]

24-MHz IMO period jitter (RMS)

–

100

400

ps

Notes

28. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

29. 4.75 V < V_DD< 5.25 V.

30. 3.0 V < V_DD< 3.6 V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation

at 3.3 V.

31. See the individual user module datasheets for information on maximum frequencies for user modules.

32. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at

www.cypress.com under Application Notes for more information.

Document Number: 38-12025 Rev. AD

Page 26 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 17. 2.7-V AC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

[33]

0

[34, 35]

F

IMO frequency for 12 MHz

11.04

12

12.96

MHz Trimmed for 2.7 V operation

using factory trim values. See

Figure 14 on page 20. SLIMO

mode = 1

IMO12

[33]

[34, 35]

[34]

IMO frequency for 6 MHz

5.52

6

6.48

MHz Trimmed for 2.7 V operation

using factory trim values. See

Figure 14 on page 20. SLIMO

mode = 1

IMO6

CPU1

F

CPU frequency (2.7 V nominal)

0.093

0

3

3.15

MHz 12 MHz only for

SLIMO mode = 0

[34,35]

Digital PSoC block frequency (2.7 V nominal)

12

12.5

MHz Refer to AC Digital Block

Specifications on page 29

BLK27

F

ILO frequency

8

5

32

–

96

kHz

32K1

ILO untrimmed frequency

100

kHz

After a reset and before the

M8C starts to run, the ILO is

not trimmed. See the System

Resets section of the PSoC

Technical Reference Manual

for details on this timing

32K_U

t

External reset pulse width

IILO duty cycle

10

20

–

50

–

µs

%

XRST

DC

80

ILO

F

Maximum frequency of signal on row input or

row output.

12.3

MHz

MAX

SR

Power supply slew rate

–

250

100

V/ms

ms

V

slew rate during

POWER_UP

DD

power-up

t

Time from end of POR to CPU executing code

16

Power-up from 0 V. See the

System Resets section of the

PSoC Technical Reference

Manual.

POWERUP

[36]

t

12 MHz IMO cycle-to-cycle jitter (RMS)

–

400

600

1000

1300

ps

jit_IMO

12 MHz IMO long term N cycle-to-cycle jitter

N = 32

[36]

(RMS)

[36]

12 MHz IMO period jitter (RMS)

–

100

500

ps

Notes

33. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datasheet temperature range is ±5%.

34. 2.4 V < V_DD< 3.0 V.

35. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” available at http://www.cypress.com for information on

maximum frequency for user modules.

36. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at

www.cypress.com under Application Notes for more information.

Document Number: 38-12025 Rev. AD

Page 27 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC General Purpose I/O Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively.

A

Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 18. 5-V and 3.3-V AC GPIO Specifications

Symbol

Description

GPIO operating frequency

Min

0

Typ

–

Max

12

18

–

Units

Notes

F

MHz Normal strong mode

GPIO

TRiseF

TFallF

TRiseS

TFallS

Rise time, normal strong mode, Cload = 50 pF

Fall time, normal strong mode, Cload = 50 pF

Rise time, slow strong mode, Cload = 50 pF

Fall time, slow strong mode, Cload = 50 pF

3

–

ns

V

= 4.5 to 5.25 V, 10% to 90%

= 3 to 5.25 V, 10% to 90%

DD

2

–

7

27

22

7

–

Table 19. 2.7 V AC GPIO Specifications

Symbol

Description

GPIO operating frequency

Min

0

Typ

–

Max

3

Units

Notes

F

MHz Normal strong mode

GPIO

TRiseF

TFallF

TRiseS

TFallS

Rise time, normal strong mode, Cload = 50 pF

Fall time, normal strong mode, Cload = 50 pF

Rise time, slow strong mode, Cload = 50 pF

Fall time, slow strong mode, Cload = 50 pF

6

–

50

ns

V

= 2.4 to 3.0 V, 10% to 90%

DD

6

–

50

18

40

120

Figure 13. GPIO Timing Diagram

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

AC Operational Amplifier Specifications

Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively. Typical parameters

A

are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 20. AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

2.4 V < V <3.0 V

T

Comparator mode response time, 50 mV

overdrive

–

100

200

ns

V

 3.0 V

DD

COMP

DD

Document Number: 38-12025 Rev. AD

Page 28 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC Digital Block Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively.

A

Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 21. 5-V and 3.3-V AC Digital Block Specifications

Function

Description

Min

Typ

Max

Unit

Notes

All functions Block input clock frequency

V

 4.75 V

–

49.2

24.6

MHz

DD

< 4.75 V

DD

Timer

Input clock frequency

No capture, V 4.75 V

–

49.2

24.6

–

MHz

ns

DD

No capture, V < 4.75 V

DD

With capture

[37]

Capture pulse width

Input clock frequency

50

Counter

Dead Band

No enable input, V  4.75 V

–

49.2

24.6

–

MHz

ns

DD

No enable input, V < 4.75 V

DD

With enable input

Enable input pulse width

Kill pulse width

[37]

50

Asynchronous restart mode

Synchronous restart mode

Disable mode

20

–

ns

[37]

50

[37]

Input clock frequency

V

 4.75 V

–

49.2

24.6

MHz

DD

V

< 4.75 V

–

DD

CRCPRS

(PRS

Input clock frequency

V

 4.75 V

–

49.2

24.6

MHz

DD

Mode)

< 4.75 V

CRCPRS

(CRC

Mode)

Input clock frequency

SPIM

SPIS

Input clock frequency

–

8.2

MHz

The SPI serial clock (SCLK) frequency is equal to

the input clock frequency divided by 2.

Input clock (SCLK) frequency

–

4.1

–

MHz

ns

The input clock is the SPI SCLK in SPIS mode.

[37]

Width of SS_negated between

transmissions

50

Transmitter

Receiver

Input clock frequency

The baud rate is equal to the input clock frequency

divided by 8.

V

 4.75 V, 2 stop bits

 4.75 V, 1 stop bit

< 4.75 V

–

49.2

24.6

MHz

DD

Input clock frequency

The baud rate is equal to the input clock frequency

divided by 8.

V

 4.75 V, 2 stop bits

–

49.2

24.6

MHz

DD

 4.75 V, 1 stop bit

< 4.75 V

Note

37. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document Number: 38-12025 Rev. AD

Page 29 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 22. 2.7-V AC Digital Block Specifications

Function

Description

Min

Typ

Max

Units

Notes

All

functions

Block input clock frequency

–

12.7

MHz

2.4 V < V < 3.0 V

DD

[38]

Timer

Capture pulse width

100

–

ns

Input clock frequency, with or without capture

Enable input pulse width

Input clock frequency, no enable input

Input clock frequency, enable input

Kill pulse width:

–

100

–

12.7

–

MHz

ns

Counter

12.7

MHz

–

Dead Band

Asynchronous restart mode

Synchronous restart mode

Disable mode

20

100

–

ns

–

ns

Input clock frequency

12.7

MHz

CRCPRS

(PRS Mode)

Input clock frequency

–

CRCPRS

Input clock frequency

–

12.7

6.35

MHz

(CRC Mode)

SPIM

The SPI serial clock (SCLK)

frequency is equal to the input

clock frequency divided by 2.

SPIS

Input clock (SCLK) frequency

Width of SS_ Negated between transmissions

Input clock frequency

–

100

–

4.1

–

MHz

ns

Transmitter

Receiver

12.7

MHz

The baud rate is equal to the input

clock frequency divided by 8.

Input clock frequency

–

12.7

MHz

The baud rate is equal to the input

clock frequency divided by 8.

AC External Clock Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T  85 °C, or 3.0 V to 3.6 V and –40 °C  T  85 °C, respectively. Typical parameters are measured at 5 V,

A

3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 23. 5-V AC External Clock Specifications

Symbol

Description

Min

Typ

–

Max

24.6

5300

–

Units

MHz

ns

Notes

F

–

Frequency

High period

Low period

0.093

20.6

150

OSCEXT

–

ns

Power-up IMO to switch

–

µs

Note

38. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Document Number: 38-12025 Rev. AD

Page 30 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 24. 3.3-V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

F

Frequency with CPU clock divide by 1

0.093

–

12.3

MHz Maximum CPU frequency is 12 MHz

at 3.3 V. With the CPU clock divider

set to 1, the external clock must

adhere to the maximum frequency

and duty cycle requirements

OSCEXT

Frequency with CPU clock divide by 2 or

greater

0.186

–

24.6

MHz If the frequency of the external clock

is greater than 12 MHz, the CPU clock

divider must be set to 2 or greater. In

this case, the CPU clock divider

ensures that the fifty percent duty

cycle requirement is met

OSCEXT

–

High period with CPU clock divide by 1

Low period with CPU clock divide by 1

Power-up IMO to switch

41.7

150

–

5300

ns

µs

–

Table 25. 2.7-V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

0

F

Frequency with CPU clock divide by 1

0.093

–

3.08

MHz Maximum CPU frequency is 3 MHz at

2.7 V. With the CPU clock divider set

to 1, the external clock must adhere to

the maximum frequency and duty

cycle requirements

OSCEXT

Frequency with CPU clock divide

by 2 or greater

0.186

–

6.35

MHz If the frequency of the external clock

is greater than 3 MHz, the CPU clock

divider must be set to 2 or greater. In

this case, the CPU clock divider

ensures that the fifty percent duty

cycle requirement is met

OSCEXT

–

High period with CPU clock divide by 1

Low period with CPU clock divide by 1

Power-up IMO to switch

160

150

–

5300

ns

µs

–

Document Number: 38-12025 Rev. AD

Page 31 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

AC Programming Specifications

Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and

–40 °C  T  85 °C, or 3.0 V to 3.6 V and –40 °C  T  85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V

A

at 25 °C and are for design guidance only.

Table 26. AC Programming Specifications

Symbol

Description

Rise time of SCLK

Fall time of SCLK

Min

1

Typ

–

Max

20

–

Units

ns

Notes

T

F

T

RSCLK

1

–

ns

FSCLK

Data setup time to falling edge of SCLK

Data hold time from falling edge of SCLK

Frequency of SCLK

40

0

–

ns

SSCLK

–

ns

HSCLK

SCLK

–

8

MHz

ms

ns

Flash erase time (block)

–

10

40

–

ERASEB

WRITE

Flash block write time

–

Data out delay from falling edge of SCLK

Flash erase time (Bulk)

–

45

50

70

–

3.6  V

DD

DSCLK

DSCLK3

DSCLK2

ERASEALL

–

ns

3.0  V  3.6

DD

–

ns

2.4  V  3.0

DD

–

20

ms

Erase all blocks and protection

fields at once

[39]

T

Flash block erase + flash block write time

–

100

200

ms

0 °C  Tj  100 °C

–40 °C  Tj  0 °C

PROGRAM_HOT

PROGRAM_COLD

[39]

2

AC I C ^[40]Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to

5.25 V and –40 °C  T  85 °C, 3.0 V to 3.6 V and –40 °C  T  85 °C, or 2.4 V to 3.0 V and –40 °C  T  85 °C, respectively.

A

Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.

Table 27. AC Characteristics of the I²C SDA and SCL Pins for V_DD3.0 V

Standard Mode

Fast Mode

Symbol

Description

SCL clock frequency

Units

Min

0

Max

100

–

Min

Max

400

–

F

T

0

kHz

µs

SCLI2C

Hold time (repeated) start condition. After this

period, the first clock pulse is generated

4.0

0.6

HDSTAI2C

T

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated start condition

Data hold time

4.7

4.0

4.7

0

–

1.3

0.6

0

–

µs

ns

µs

ns

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

–

[41]

Data setup time

250

4.0

4.7

–

100

–

Setup time for stop condition

Bus free time between a stop and start condition

0.6

1.3

0

–

Pulse width of spikes suppressed by the input

filter.

50

SPI2C

Notes

39. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.

Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC^®Flash) for more information.

40. Errata: The I²C block exhibits occasional data and bus corruption errors when the I²C master initiates transactions while the device is transitioning in to or out of sleep

mode.

41. A Fast-Mode I²C-bus device may be used in a Standard-Mode I²C-bus system, but it must meet the requirement T_SU;DAT 250 ns. This is automatically the case if

the device does not stretch the LOW period of the SCL signal. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line T_rmax+ T_SU;DAT= 1000 + 250 = 1250 ns (according to the Standard-Mode I²C-bus specification) before the SCL line is released.

Document Number: 38-12025 Rev. AD

Page 32 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Table 28. 2.7-V AC Characteristics of the I²C SDA and SCL Pins (Fast Mode not Supported)

Standard Mode

Fast Mode

Symbol

Description

SCL clock frequency

Units

Min

Max

100

–

Min

–

Max

–

F

T

0

kHz

µs

SCLI2C

Hold time (repeated) start condition. After this

period, the first clock pulse is generated.

4.0

–

HDSTAI2C

T

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated start condition

Data hold time

4.7

4.0

4.7

0

–

µs

ns

µs

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

Data setup time

250

4.0

4.7

Setup time for stop condition

Bus free time between a stop and start

condition

T

Pulse width of spikes are suppressed by the

input filter.

–

ns

SPI2C

Figure 14. Definition for Timing for Fast/Standard Mode on the I²C Bus

I2C_SDA

I2C_SCL

T_SUDATI2C

T_HDSTAI2C

T_SPI2C

T_SUSTAI2C

T_BUFI2C

T_HDDATI2C

T_HIGHI2CT_LOWI2C

T_SUSTOI2C

P

S

Sr

Repeated START Condition

STOP Condition

START Condition

Document Number: 38-12025 Rev. AD

Page 33 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Packaging Information

This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of

the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.

Figure 15. 16-pin SOIC (150 Mils) Package Outline, 51-85068

51-85068 *E

Document Number: 38-12025 Rev. AD

Page 34 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Figure 16. 20-pin SSOP (210 Mils) Package Outline, 51-85077

51-85077 *E

Figure 17. 28-pin SSOP (210 Mils) Package Outline, 51-85079

51-85079 *E

Document Number: 38-12025 Rev. AD

Page 35 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Figure 18. 32-pin QFN (5 × 5 × 1.0 mm) Package Outline, 001-30999

001-30999 *D

Important Note For information on the preferred dimensions for mounting QFN packages, see the Application Note EROS - Design

Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices available at http://www.cypress.com.

Document Number: 38-12025 Rev. AD

Page 36 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) LQ32A 1.3 × 2.7 E-Pad (Sawn Type) Package Outline, 001-48913

001-48913 *D

Figure 20. 56-pin SSOP (300 Mils) Package Outline, 51-85062

51-85062 *F

Document Number: 38-12025 Rev. AD

Page 37 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Thermal Impedances

Table 29. Thermal Impedances per Package

[42]

Package

16-pin SOIC

Typical 

JA

JC

123 °C/W

117 °C/W

96 °C/W

27 °C/W

22 °C/W

48 °C/W

55 °C/W

41 °C/W

39 °C/W

15 °C/W

12 °C/W

24 °C/W

20-pin SSOP

28-pin SSOP

[43]

32-pin QFN

5 × 5 mm 0.60 Max

5 × 5 mm 1.00 Max

[43]

56-pin SSOP

Solder Reflow Specifications

Table 30 shows the solder reflow temperature limits that must not be exceeded.

Table 30. Solder Reflow Specifications

Package

Maximum Peak Temperature (T_C)

Maximum Time above T_C– 5 °C

30 seconds

16-pin SOIC

260 °C

20-pin SSOP

28-pin SSOP

32-pin QFN

56-pin SSOP

30 seconds

Notes

42. T_J= T_A+ Power × 

JA

43. To achieve the thermal impedance specified for the QFN package, refer to Application Note EROS - Design Guidelines for Cypress Quad Flat No Extended Lead

(QFN) Packaged Devices available at http://www.cypress.com.

44. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu

paste. Refer to the solder manufacturer specifications.

Document Number: 38-12025 Rev. AD

Page 38 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Evaluation Tools

Development Tool Selection

All evaluation tools can be purchased from the Cypress Online

Store.

This section presents the development tools available for all

current PSoC device families including the CY8C21x34 family.

CY3210-MiniProg1

Software

The CY3210-MiniProg1 kit allows you to program PSoC devices

through the MiniProg1 programming unit. The MiniProg is a

small, compact prototyping programmer that connects to the PC

through a provided USB 2.0 cable. The kit includes:

PSoC Designer

At the core of the PSoC development software suite is

PSoC Designer, used to generate PSoC firmware applications.

PSoC Designer

http://www.cypress.com and includes a free C compiler.

is

available

free

of

charge

at

■ MiniProg programming unit

■ MiniEval socket programming and evaluation board

■ 28-pin CY8C29466-24PXI PDIP PSoC device sample

■ 28-pin CY8C27443-24PXI PDIP PSoC device sample

■ PSoC Designer software CD

PSoC Programmer

Flexible enough to be used on the bench in development, yet

suitable for factory programming, PSoC Programmer works

either as a standalone programming application or operates

directly from PSoC Designer. PSoC Programmer software is

compatible with both PSoC ICE-Cube In-Circuit Emulator and

PSoC MiniProg. PSoC programmer is available free of charge at

http://www.cypress.com.

■ Getting Started guide

■ USB 2.0 cable

CY3210-PSoCEval1

Development Kits

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, and plenty of bread-

boarding space to meet all of your evaluation needs. The kit

includes:

All development kits can be purchased from the Cypress Online

Store.

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with

PSoC Designer. This kit supports in-circuit emulation, and the

software interface allows you to run, halt, and single step the

processor, and view the content of specific memory locations.

Advance emulation features also supported through PSoC

Designer. The kit includes:

■ Evaluation board with LCD module

■ MiniProg programming unit

■ Two 28-pin CY8C29466-24PXI PDIP PSoC device samples

■ PSoC Designer software CD

■ Getting Started guide

■ PSoC Designer software CD

■ ICE-Cube in-circuit emulator

■ ICE Flex-Pod for CY8C29x66 family

■ Cat-5 adapter

■ USB 2.0 cable

CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features

a

■ Mini-Eval programming board

■ 110 ~ 240 V power supply, Euro-Plug adapter

■ iMAGEcraft C compiler

development board for the CY8C24794-24LFXI PSoC device.

The board includes both USB and capacitive sensing

development and debugging support. This evaluation board also

includes an LCD module, potentiometer, LEDs, an enunciator

and plenty of breadboarding space to meet all of your evaluation

needs. The kit includes:

■ ISSP cable

■ USB 2.0 cable and Blue Cat-5 cable

■ Two CY8C29466-24PXI 28-PDIP chip samples

■ PSoCEvalUSB board

■ LCD module

■ MIniProg programming unit

■ Mini USB cable

■ PSoC Designer and example projects CD

■ Getting Started guide

■ Wire pack

Document Number: 38-12025 Rev. AD

Page 39 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Device Programmers

All device programmers can be purchased from the Cypress Online Store.

CY3216 Modular Programmer

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3216 Modular Programmer kit features a modular

programmer and the MiniProg1 programming unit. The modular

programmer includes three programming module cards and

supports multiple Cypress products. The kit includes:

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production-programming environment.

Note CY3207ISSP needs special software and is not compatible

with PSoC Programmer. The kit includes:

■ Modular programmer base

■ Three programming module cards

■ MiniProg programming unit

■ PSoC Designer software CD

■ Getting Started guide

■ CY3207 programmer unit

■ PSoC ISSP software CD

■ 110 ~ 240 V power supply, Euro-Plug adapter

■ USB 2.0 cable

Accessories (Emulation and Programming)

Table 31. Emulation and Programming Accessories

[45]

[46]

Part Number

CY8C21234-24SXI

CY8C21334-24PVXI

CY8C21534-24PVXI

Pin Package

16-pin SOIC

Flex-Pod Kit

CY3250-21X34

Foot Kit

Adapter

CY3250-16SOIC-FK

CY3250-20SSOP-FK

CY3250-28SSOP-FK

Adapters can be found at

http://www.emulation.com.

20-pin SSOP

28-pin SSOP

Notes

45. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

46. Foot kit includes surface mount feet that can be soldered to the target PCB.

Document Number: 38-12025 Rev. AD

Page 40 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Ordering Information

[47]

16-Pin (150-Mil) SOIC

CY8C21234-24SXI

CY8C21234-24SXIT

8 K

512 Yes –40 °C to +85 °C

4

12 12

0

No

[47]

16-Pin (150-Mil) SOIC

(Tape and Reel)

[47]

20-Pin (210-Mil) SSOP

CY8C21334-24PVXI

CY8C21334-24PVXIT

8 K

512

No

–40 °C to +85 °C

4

16 16

0

Yes

20-Pin (210-Mil) SSOP

(Tape and Reel)

[47]

28-Pin (210-Mil) SSOP

CY8C21534-24PVXI

CY8C21534-24PVXIT

8 K

512

No

–40 °C to +85 °C

4

24 24

0

Yes

28-Pin (210-Mil) SSOP

(Tape and Reel)

[47]

32-Pin (5 × 5 mm 1.00 max)

Sawn QFN

CY8C21434-24LTXI

CY8C21434-24LTXIT

CY8C21434-24LQXI

CY8C21434-24LQXIT

8 K

512

No

–40 °C to +85 °C

4

28 28

0

Yes

32-Pin (5 × 5 mm 1.00 max)

[48]

Sawn QFN

(Tape and Reel)

32-Pin (5 × 5 mm 0.60 max)

Thin Sawn QFN

32-Pin (5 × 5 mm 0.60 max)

Thin Sawn QFN

(Tape and Reel)

[47]

32-Pin (5 × 5 mm 1.00 max)

Sawn QFN

CY8C21634-24LTXI

CY8C21634-24LTXIT

8 K

512 Yes –40 °C to +85 °C

4

26 26

0

Yes

[48]

32-Pin (5 × 5 mm 1.00 max)

[48]

Sawn QFN

(Tape and Reel)

[47]

56-Pin OCD SSOP

CY8C21001-24PVXI

CY8C21434-12X14I

8 K

512 Yes –40 °C to +85 °C

4

26 26

0

Yes

Please contact sales office or Field Applications Engineer (FAE) for more

information.

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Notes

47. All Digital I/O Pins also connect to the common analog mux.

48. Refer to the section 32-pin Part Pinout on page 11 for pin differences.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Ordering Code Definitions

CY 8 C 21 xxx -24 xx

Package Type:

PX = PDIP Pb-free

SX = SOIC Pb-free

Thermal Rating:

C = Commercial

I = Industrial

PVX = SSOP Pb-free

E = Extended

LFX/LKX/LTX/LCX/LQX = QFN Pb-free

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Cypress

Company ID: CY =

Document Number: 38-12025 Rev. AD

Page 42 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Acronyms

Table 32 lists the acronyms that are used in this document.

Table 32. Acronyms Used in this Datasheet

Acronym

AC

Description

alternating current

Acronym

Description

million instructions per second

on-chip debug

MIPS

OCD

PCB

PDIP

PGA

PLL

ADC

API

analog-to-digital converter

application programming interface

complementary metal oxide semiconductor

central processing unit

printed circuit board

CMOS

CPU

CRC

CT

plastic dual-in-line package

programmable gain amplifier

phase-locked loop

cyclic redundancy check

continuous time

POR

PPOR

PRS

power on reset

DAC

DC

digital-to-analog converter

direct current

precision power on reset

pseudo-random sequence

Programmable System-on-Chip

pulse width modulator

quad flat no leads

®

DTMF

ECO

dual-tone multi-frequency

external crystal oscillator

PSoC

PWM

QFN

EEPROM electrically erasable programmable read-only

memory

GPIO

ICE

general purpose I/O

RTC

SAR

real time clock

in-circuit emulator

successive approximation

switched capacitor

IDE

integrated development environment

internal low speed oscillator

internal main oscillator

input/output

SC

ILO

SLIMO

SMP

SOIC

slow IMO

IMO

I/O

switch-mode pump

small-outline integrated circuit

serial peripheral interface

static random access memory

supervisory read only memory

shrink small-outline package

universal asynchronous receiver / transmitter

universal serial bus

TM

IrDA

ISSP

LCD

LED

LPC

LVD

MAC

MCU

infrared data association

in-system serial programming

liquid crystal display

light-emitting diode

SPI

SRAM

SROM

SSOP

UART

USB

low power comparator

low voltage detect

multiply-accumulate

WDT

watchdog timer

microcontroller unit

XRES

external reset

Reference Documents

CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,

CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC^®Programmable System-on-Chip Technical

Reference Manual (TRM) (001-14463)

Design Aids – Reading and Writing PSoC^®Flash - AN2015 (001-40459)

Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.

Document Number: 38-12025 Rev. AD

Page 43 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document Conventions

Units of Measure

Table 33 lists the units of measures.

Table 33. Units of Measure

Symbol

kB

Unit of Measure

Symbol

µH

Unit of Measure

1024 bytes

decibels

micro henry

microsecond

millisecond

nanosecond

picosecond

microvolt

dB

µs

°C

degree Celsius

microfarad

femto farad

picofarad

ms

µF

ns

fF

ps

pF

µV

kHz

MHz

rt-Hz

k

kilohertz

mV

mVpp

nV

millivolts

megahertz

root hertz

kilo ohm

millivolts peak-to-peak

nano volt

V

volt



ohm

µW

W

microwatt

watt

µA

microampere

milliampere

nano ampere

pico ampere

millihenry

mA

nA

mm

ppm

%

millimeter

parts per million

percent

pA

mH

Numeric Conventions

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).

Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended

lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.

Glossary

active high

1. A logic signal having its asserted state as the logic 1 state.

2. A logic signal having the logic 1 state as the higher voltage of the two states.

analog blocks

The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.

These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.

analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts

(ADC)

a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.

Application

programming

interface (API)

A series of software routines that comprise an interface between a computer application and lower level services

and functions (for example, user modules and libraries). APIs serve asbuilding blocks for programmers that create

software applications.

asynchronous

A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.

bandgap

reference

A stable voltage reference design that matches the positive temperature coefficient of VT with the negative

temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.

bandwidth

1. The frequency range of a message or information processing system measured in hertz.

2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is

sometimes represented more specifically as, for example, full width at half maximum.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary (continued)

bias

1. A systematic deviation of a value from a reference value.

2. The amount by which the average of a set of values departs from a reference value.

3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to

operate the device.

block

buffer

1. A functional unit that performs a single function, such as an oscillator.

2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or

an analog PSoC block.

1. A storage area for data that is used to compensate for a speed difference, when transferring data from one

device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which

data is written.

2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received

from an external device.

3. An amplifier used to lower the output impedance of a system.

bus

1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing

patterns.

2. A set of signals performing a common function and carrying similar data. Typically represented using vector

notation; for example, address[7:0].

3. One or more conductors that serve as a common connection for a group of related devices.

clock

The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to

synchronize different logic blocks.

comparator

compiler

An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy

predetermined amplitude requirements.

A program that translates a high level language, such as C, into machine language.

configuration

space

In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.

crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less

sensitive to ambient temperature than other circuit components.

cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift

check (CRC)

register. Similar calculations may be used for a variety of other purposes such as data compression.

data bus

A bi-directional set of signals used by a computer to convey information from a memory location to the central

processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.

debugger

A hardware and software system that allows you to analyze the operation of the system under development. A

debugger usually allows the developer to step through the firmware one step at a time, set break points, and

analyze memory.

dead band

A period of time when neither of two or more signals are in their active state or in transition.

digital blocks

The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,

pseudo-random number generator, or SPI.

digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)

(DAC) converter performs the reverse operation.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary (continued)

duty cycle

emulator

The relationship of a clock period high time to its low time, expressed as a percent.

Duplicates (provides an emulation of) the functions of one system with a different system, so that the second

system appears to behave like the first system.

External Reset

(XRES)

An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop

and return to a pre-defined state.

Flash

An electrically programmable and erasable, non-volatile technology that provides you the programmability and

data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is

OFF.

Flash block

The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash

space that may be protected. A Flash block holds 64 bytes.

frequency

gain

The number of cycles or events per unit of time, for a periodic function.

The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually

expressed in dB.

2

I C

A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated

Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in

the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building

control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high

with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.

ICE

The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging

device activity in a software environment (PSoC Designer).

input/output (I/O) A device that introduces data into or extracts data from a system.

interrupt

A suspension of a process, such as the execution of a computer program, caused by an event external to that

process, and performed in such a way that the process can be resumed.

interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many

routine (ISR)

interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends

with the RETI instruction, returning the device to the point in the program where it left normal program execution.

jitter

1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on

serial data streams.

2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between

successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.

low-voltagedetect A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold.

(LVD)

M8C

An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by

interfacing to the Flash, SRAM, and register space.

master device

A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in

width, the master device is the one that controls the timing for data exchanges between the cascaded devices

and an external interface. The controlled device is called the slave device.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary (continued)

microcontroller

An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a

microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the

realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This

in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for

general-purpose computation as is a microprocessor.

mixed-signal

modulator

noise

The reference to a circuit containing both analog and digital techniques and components.

A device that imposes a signal on a carrier.

1. A disturbance that affects a signal and that may distort the information carried by the signal.

2. The random variations of one or more characteristics of any entity such as voltage, current, or data.

oscillator

parity

A circuit that may be crystal controlled and is used to generate a clock frequency.

A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the

digits of the binary data either always even (even parity) or always odd (odd parity).

Phase-locked

loop (PLL)

An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference

signal.

pinouts

The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their

physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between

schematic and PCB design (both being computer generated files) and may also involve pin names.

port

A group of pins, usually eight.

Power on reset

(POR)

A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware

reset.

®

PSoC

Cypress Semiconductor’s PSoC is a registered trademark and Programmable System-on-Chip™ is a trademark

of Cypress.

PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.

pulse width

An output in the form of duty cycle which varies as a function of the applied measurand

modulator (PWM)

RAM

An acronym for random access memory. A data-storage device from which data can be read out and new data

can be written in.

register

reset

A storage device with a specific capacity, such as a bit or byte.

A means of bringing a system back to a know state. See hardware reset and software reset.

ROM

An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot

be written in.

serial

1. Pertaining to a process in which all events occur one after the other.

2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or

channel.

settling time

The time it takes for an output signal or value to stabilize after the input has changed from one value to another.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Glossary (continued)

shift register

slave device

A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.

A device that allows another device to control the timing for data exchanges between two devices. Or when

devices are cascaded in width, the slave device is the one that allows another device to control the timing of data

exchanges between the cascaded devices and an external interface. The controlling device is called the master

device.

SRAM

SROM

An acronym for static random access memory. A memory device where you can store and retrieve data at a high

rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged

until it is explicitly altered or until power is removed from the device.

An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate

circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,

operating from Flash.

stop bit

A signal following a character or block that prepares the receiving device to receive the next character or block.

synchronous

1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.

2. A system whose operation is synchronized by a clock signal.

tri-state

A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any

value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,

allowing another output to drive the same net.

UART

A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.

user modules

Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower

level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming

Interface) for the peripheral function.

user space

The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal

program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during

the initialization phase of the program.

V

A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.

A name for a power net meaning "voltage source." The most negative power supply signal.

DD

SS

watchdog timer

A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.

Document Number: 38-12025 Rev. AD

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CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Errata

®

This section describes the errata for the PSoC Programmable System-on-Chip CY8C21234. Details include errata trigger conditions,

scope of impact, available workarounds, and silicon revision applicability.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

Ordering Information

CY8C21234-24SXI

CY8C21234-24SXIT

CY8C21334-24PVXI

CY8C21334-24PVXIT

CY8C21534-24PVXI

CY8C21534-24PVXIT

CY8C21434-24LFXI

CY8C21434-24LFXIT

CY8C21434-24LKXI

CY8C21434-24LKXIT

CY8C21634-24LFXI

CY8C21634-24LFXIT

CY8C21434-24LTXI

CY8C21434-24LTXIT

CY8C21434-24LQXI

CY8C21434-24LQXIT

CY8C21634-24LTXI

CY8C21634-24LTXIT

CY8C21001-24PVXI

CY8C21234

CY8C21234 Qualification Status

Product Status: Production

Document Number: 38-12025 Rev. AD

Page 49 of 55

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CY8C21334, CY8C21234

CY8C21234 Errata Summary

The following table defines the errata applicability to available CY8C21234 family devices. An "X" indicates that the errata pertains to

the selected device.

Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.

Items

Part Number

Silicon Revision

Fix Status

No fix is currently planned.

[1.]. Internal Main Oscillator (IMO)

Tolerance Deviation at Temperature

Extremes

CY8C21234

A

[2]. I2C Errors

CY8C21234

A

No fix is currently planned.

1. Internal Main Oscillator (IMO) Tolerance Deviation at Temperature Extremes

■ Problem Definition

Asynchronous Digital Communications Interfaces may fail framing beyond 0 °C to 70 °C. This problem does not affect

end-product usage between 0 °C and 70 °C.

■ Parameters Affected

The IMO frequency tolerance. The worst case deviation when operated below 0 °C and above +70 °C and within the upper

and lower datasheet temperature range is ±5%.

■ Trigger Condition(S)

The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the datasheet limit of ±2.5% when

operated beyond the temperature range of 0 °C to +70 °C.

■ Scope of Impact

This problem may affect UART, IrDA, and FSK implementations.

■ Workaround

Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.

■ Fix Status

No fix is currently planned.

2. I²C Errors

■ Problem Definition

2

The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is

transitioning in to or out of sleep mode.

■ Parameters Affected

Affects reliability of I C communication to device, between I C master, and third party I C slaves.

■ Trigger Condition(S)

2

Triggered by transitions into and out of the device's sleep mode.

■ Scope of Impact

This problem may affect UART, IrDA, and FSK implementations.

■ Workaround

2

Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I C block from the

2

bus prior to going to sleep modes. I C transactions during sleep are supported by a protocol in which the master wakes the

2

device prior to the I C transaction

■ Fix Status

Will not be fixed.

Document Number: 38-12025 Rev. AD

Page 50 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document History Page

Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC^®Programmable System-on-Chip™

Document Number: 38-12025

Orig. of

Change

Submission

Date

Description of Change

Rev.

ECN

**

227340

235992

HMT

SFV

See ECN New silicon and document (Revision **).

*A

See ECN Updated Overview and Electrical Spec. chapters, along with revisions to the

24-Pin pinout part. Revised the register mapping tables. Added a SSOP 28-Pin

part.

*B

*C

248572

277832

SFV

See ECN Changed title to include all part #s. Changed 28-Pin SSOP from CY8C21434

to CY8C21534. Changed pin 9 on the 28-Pin SSOP from SMP pin to Vss pin.

Added SMP block to architecture diagram. Update Electrical Specifications.

Added another 32-Pin MLF part: CY8C21634.

HMT

See ECN Verify datasheet standards from SFV memo. Add Analog Input Mux to appli-

cable pin outs. Update PSoC Characteristics table. Update diagrams and

specs. Final.

*D

*E

*F

285293

301739

329104

HMT

See ECN Update 2.7 V DC GPIO spec. Add Reflow Peak Temp. table.

See ECN DC Chip-Level Specification changes. Update links to new CY.com Portal.

See ECN Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature.

Update Electrical Specifications. Update Reflow Peak Temp. table. Add 32

MLF E-PAD dimensions. Add ThetaJC to Thermal Impedance table. Fix 20-Pin

package order number. Add CY logo. Update CY copyright.

*G

352736

HMT

See ECN Add new color and logo. Add URL to preferred dimensions for mounting MLF

packages. Update Transmitter and Receiver AC Digital Block Electrical Speci-

fications.

*H

*I

390152

413404

430185

HMT

See ECN Clarify MLF thermal pad connection info. Replace 16-Pin 300-MIL SOIC with

correct 150-MIL.

See ECN Update 32-Pin QFN E-Pad dimensions and rev. *A. Update CY branding and

QFN convention.

*J

See ECN Add new 32-Pin 5x5 mm 0.60 thickness QFN package and diagram,

CY8C21434-24LKXI. Update thermal resistance data. Add 56-Pin SSOP

on-chip debug non-production part, CY8C21001-24PVXI. Update typical and

recommended Storage Temperature per industrial specs. Update copyright

and trademarks.

*K

677717

HMT

See ECN Add CapSense SNR requirement reference. Add new Dev. Tool section. Add

CY8C20x34 to PSoC Device Characteristics table. Add Low Power

Comparator (LPC) AC/DC electrical spec. tables. Update rev. of 32-Lead (5x5

mm 0.60 MAX) QFN package diagram.

*L

*M

*N

2147847

2273246

2618124

UVS /

PYRS

02/27/08

04/01/08

12/09/08

Added 32-Pin QFN Sawn pin diagram, package diagram, and ordering

information.

UVS /

AESA

Added 32 pin thin sawn package diagram.

OGNE /

PYRS

Added Note in Ordering Information section.

Changed title from PSoC Mixed-Signal Array to PSoC

Programmable System-on-Chip

*O

2684145

SNV /

AESA

04/06/2009 Updated 32-Pin Sawn QFN package dimension for CY8C21434-24LTXIT

Updated Getting Started, Development Tools, and Designing with PSoC

Designer Sections

*P

2693024

2720594

DPT /

PYRS

04/16/2009 Updated 32-Pin Sawn QFN package diagram

*Q

BRW

06/22/09

Corrected ohm symbol and parenthesis in figure caption (Fig.25)

Removed references to mixed-sginal array from the text.

Updated Development Tools Selection section.

Document Number: 38-12025 Rev. AD

Page 51 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document History Page (continued)

Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC^®Programmable System-on-Chip™

Document Number: 38-12025

Orig. of

Change

Submission

Date

Description of Change

Rev.

ECN

*R

2762499

JVY

09/11/2009 Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as

follows:

Modified F

and T

specifications.

IMO6

RAMP

WRITE

Replaced T

(time) specification with SR

(slew rate)

POWER_UP

specification.

Added note [11] to Flash Endurance specification.

Added I , I , DC , F

, T

, and

OH OL

ILO 32K_U POWERUP ERASEALL PROGRAM_HOT

specifications.

T

PROGRAM_COLD

*S

2900687

MAXK /

NJF

03/30/2010 Updated The Analog Multiplexer System.

Updated Cypress website links.

Added T

and T

parameters in Absolute Maximum Ratings.

BAKETEMP

BAKETIME

Removed DC Low Power Comparator section.

Updated 5-V and 3.3-V AC Chip-Level Specifications.

Removed AC Low Power Comparator and AC Analog Mux Bus sections.

Updated note in Packaging Information and package diagrams.

Added 56 SSOP values for Thermal Impedances, Solder Reflow Specifica-

tions.

Removed Third Party Tools and Build a PSoC Emulator into your Board.

Updated Ordering Code Definitions.

Removed inactive parts from Ordering Information

Removed obsolete package spec 001-06392.

Updated links in Sales, Solutions, and Legal Information.

*T

2937578

3005573

VMAD

NJF

05/26/2010 Updated content to match current style guide and data sheet template.

No technical updates.

*U

09/02/10

Added PSoC Device Characteristics table.

2

Added DC I C Specifications table.

Added F

max limit.

32K_U

Added Tjit_IMO specification, removed existing jitter specifications.

Updated Units of Measure, Acronyms, Glossary, and References sections.

Updated solder reflow specifications.

No specific changes were made to AC Digital Block Specifications table and

2

I C Timing Diagram. They were updated for clearer understanding.

Template and styles update.

*V

3068269

3281271

ARVM

VMAD

10/21/2010 Removed pruned parts CY8C21434-24LKXI and CY8C21434-24LKXIT from

Ordering Information.

*W

08/23/2011 Under Table 20 on page 28 “Notes” section, the text “2.4 V < V < 3.0 V” is

CC

changed to “2.4 V < V < 3.0 V”.

DD

Updated Solder Reflow Specifications.

Changed package diagram from 51-85188 *D to 001-30999 *C for QFN32

package.

*X

*Y

3383568

3659297

GIR

10/05/2011 The text “Pin must be left floating” is included under Description of NC pin in

Pin Definitions on page 14.

Changed spec 001-30999 from 32-Pin (5 × 5 mm 0.93 Max) Sawn QFN to

32-Pin (5 × 5 mm 1.0 Max) Sawn QFN

Removed pruned parts CY8C21434-24LCXI and CY8C21434-24LCXIT from

the Ordering Information table.

YLIU

07/26/2012 Updated Packaging Information (Removed spec 001-44368).

Document Number: 38-12025 Rev. AD

Page 52 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document History Page (continued)

Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC^®Programmable System-on-Chip™

Document Number: 38-12025

Orig. of

Change

Submission

Date

Description of Change

Rev.

ECN

*Z

3902039

VNJ

02/12/2013 Updated Electrical Specifications (Updated AC Electrical Characteristics

(UpdatedAC Chip-Level Specifications (Updated Table 16 (Changed minimum

value of F

parameter from 5.5 MHz to 5.52 MHz, changed maximum value

IMO6

of F

parameter from 6.5 MHz to 6.48 MHz), updated Table 17 (Changed

IMO6

minimum value of F

parameter from 11.5 MHz to 11.04 MHz, changed

parameter from 12.7 MHz to 12.96 MHz, changed

IMO12

maximum value of F

IMO12

minimum value of F

parameter from 5.5 MHz to 5.52 MHz, changed

parameter from 6.5 MHz to 6.48 MHz)))).

IMO6

maximum value of F

Updated Packaging Information:

spec 51-85068 – Changed revision from *D to *E.

spec 001-30999 – Changed revision from *C to *D.

spec 001-48913 – Changed revision from *B to *C.

spec 51-85062 – Changed revision from *E to *F.

AA

AB

3993249

4076892

SLAN

05/07/2013 Added Errata.

07/25/2013 Added Errata footnotes (Notes 1, 2, 3, 4, 5, 8, 28, 33, 40).

Updated Features:

Added Note 1 and referred in “Internal ±2.5% 24- / 48-MHz main oscillator”.

2

Added Note 2 and referred in “I C” under “Additional system resources”.

Updated PSoC Functional Overview:

Updated The PSoC Core:

Added Note 3 and referred in “24 MHz”.

2

Added Note 4 and referred in “I C” under “System resources provide these

additional capabilities”.

Updated The Digital System:

2

Added Note 4 and referred in “I C slave and multi-master”.

Updated Additional System Resources:

Added Note 5 and referred in “I C”.

2

Updated Development Tools:

2

Added Note 8 and referred in “I C” under “Built-in support for communication

interfaces”.

Updated Electrical Specifications:

Updated AC Electrical Characteristics:

Updated AC Chip-Level Specifications:

Added Note 28 and referred in “F

Added Note 33 and referred in “F

” and “F

” parameters in Table 16.

” parameters in Table 17.

IMO24

IMO12

IMO6

Updated AC I2C [40] Specifications:

Added Note 40 and referred in the heading.

Updated in new template.

Completing Sunset Review.

AC

4143112

DCHE

10/01/2013 Updated Packaging Information:

spec 001-48913 – Changed revision from *C to *D.

Updated Ordering Information (Updated part numbers).

Updated Reference Documents:

Removed references of spec 001-14503 and spec 001-17397 as these specs

are obsolete.

Document Number: 38-12025 Rev. AD

Page 53 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Document History Page (continued)

Document Title: CY8C21634, CY8C21534, CY8C21434, CY8C21334, CY8C21234, PSoC^®Programmable System-on-Chip™

Document Number: 38-12025

Orig. of

Change

Submission

Date

Description of Change

Rev.

ECN

AD

4338103

PRKU

04/15/2014 Updated Pin Information:

Updated Pin Definitions (corresponding to CY8C21234):

Added Note 9 and referred the same note in the description of pin 6 and pin 8.

Updated Pin Definitions (corresponding to CY8C21334):

Added Note 11 and referred the same note in the description of pin 5 and pin 10.

Updated Pin Definitions (corresponding to CY8C21534):

Added Note 13 and referred the same note in the description of pin 9 and pin 14.

Updated Pin Definitions (corresponding to CY8C21434/CY8C21634):

Added Note 16 and referred the same note in the description of pin 7, pin 12

and pin 32.

Updated Pin Definitions (corresponding to CY8C21001):

Added Note 18 and referred the same note in the description of pin 17, pin 18

and pin 28.

Updated Packaging Information:

Updated “Important Note” below Figure 18.

Updated Thermal Impedances:

Updated Note 43 referred in Table 29.

Document Number: 38-12025 Rev. AD

Page 54 of 55

CY8C21634, CY8C21534, CY8C21434

CY8C21334, CY8C21234

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Lighting & Power Control

Community | Forums | Blogs | Video | Training

Technical Support

Memory

cypress.com/go/memory

cypress.com/go/psoc

cypress.com/go/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12025 Rev. AD

Revised April 15, 2014

Page 55 of 55

®

PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation.

2

Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided

2

that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.

All products and company names mentioned in this document may be the trademarks of their respective holders.


型号：	CY8C21434-12X14I
厂家：	CYPRESS
描述：	Multifunction Peripheral, CMOS, 时钟
文件：	总55页 (文件大小：1531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C21434-12X14I [CYPRESS]

相关型号：

CY8C21434-24AX

CY8C21434-24C

CY8C21434-24E

CY8C21434-24I

CY8C21434-24LCXI

CY8C21434-24LCXIT

CY8C21434-24LFX

CY8C21434-24LFXI

CY8C21434-24LFXI

CY8C21434-24LFXIT

CY8C21434-24LFXIT

CY8C21434-24LKXI