CY8C21434-24LFXI [ROCHESTER]
MULTIFUNCTION PERIPHERAL, QCC32, 5 X 5 MM, 0.93 MM HEIGHT, LEAD FREE, MO-220, QFN-32;
| 型号： | CY8C21434-24LFXI |
| 厂家： | 
Rochester Electronics |
| 描述： | MULTIFUNCTION PERIPHERAL, QCC32, 5 X 5 MM, 0.93 MM HEIGHT, LEAD FREE, MO-220, QFN-32 时钟 微控制器 |
| 文件： | 总47页 (文件大小：2058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
PSoC® Programmable System-on-Chip
■ Versatile Analog Mux
❐ Common Internal Analog Bus
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds up to 24 MHz
❐ Low power at high speed
❐ 2.4V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐ Simultaneous Connection of I/O Combinations
❐ Capacitive Sensing Application Capability
■ Additional System Resources
❐ I2C Master, Slave and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC® Blocks)
❐ Four Analog Type “E” PSoC Blocks Provide:
• Two Comparators with DAC References
• Single or Dual 10-Bit 28 Channel ADC
❐ 4 Digital PSoC Blocks Provide:
❐ On-Chip Precision Voltage Reference
Logic Block Diagram
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 8K Flash Program Storage 50,000 Erase/Write Cycles
❐ 512 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Complete Development Tools
❐ Free Development Software
(PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24 and 48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ Configurable Interrupt on All GPIO
Cypress Semiconductor Corporation
Document Number: 38-12025 Rev. *R
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 10, 2009
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The Digital System
PSoC Functional Overview
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user modules. Digital peripheral configurations include the
following.
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple tradi-
tional MCU-based system components with one low cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and program-
mable interconnect. This architecture enables the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
■ PWMs (8 to 32 bit)
■ PWMs with Dead band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
The PSoC architecture, shown in Figure 1, consists of four main
areas: the Core, the System Resources, the Digital System, and
the Analog System. Configurable global bus resources allow
combining all the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose I/O (GPIO) are also included.
The GPIO provide access to the global digital and analog inter-
connects.
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave and multi-master
■ Cyclical Redundancy Checker/Generator (8-bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The PSoC Core
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 4.
System Resources provide the following additional capabilities:
■ Digital clocks for increased flexibility.
Figure 1. Digital System Block Diagram
■ I2C functionality to implement an I2C master and slave.
Port 3
Port 1
Port 2
Port 0
■ An internal voltage reference, MultiMaster, that provides an
absolute value of 1.3V to a number of PSoC subsystems.
DigitalClocks
FromCore
ToAnalog
System
To SystemBus
■ A switch mode pump (SMP) that generates normal operating
voltages off a single battery cell.
■ Various system resets supported by the M8C.
DIGITAL SYSTEM
The Digital System consists of an array of digital PSoC blocks
that may be configured into any number of digital peripherals.
The digital blocks are connected to the GPIO through a series of
global buses that can route any signal to any pin, freeing designs
from the constraints of a fixed peripheral controller.
DigitalPSoCBlockArray
Row 0
4
4
DBB00
DBB01
DCB02
DCB03
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to
10 bits of precision.
8
8
8
8
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Document Number: 38-12025 Rev. *R
Page 2 of 46
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The Analog Multiplexer System
The Analog System
The Analog Mux Bus can connect to every GPIO pin. Pins may
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
The Analog System consists of 4 configurable blocks that allow
the creation of complex analog signal flows. Analog peripherals
are very flexible and may be customized to support specific
application requirements. Some of the common PSoC analog
functions for this device (most available as user modules) are:
■ Analog-to-digital converters (single or dual, with 8-bit or 10-bit
resolution)
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Pin-to-pin comparator
■ Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
■ Track pad, finger sensing.
■ 1.3V reference (as a System Resource)
■ Chip-wide mux that allows analog input from any I/O pin.
■ Crosspoint connection between any I/O pin combinations.
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x34 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT Type E block and one SC Type E block. Refer
to the PSoC Technical Reference Manual for detailed infor-
mation on the CY8C21x34’s Type E analog blocks.
When designing capacitive sensing applications, refer to the
signal-to-noise system level requirement found in Application
Note
AN2403
on
the
Cypress
web
site
at
http://www.cypress.com.
Additional System Resources
Figure 2. Analog System Block Diagram
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
Array Input
Configuration
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
ACI0[1:0]
ACI1[1:0]
All IO
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
X
X
AC OL 1MU X
X
X
An al o g MuxBus
■ An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
X
Array
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
ACE00
ACE01
ASE11
ASE10
■ Versatile analog multiplexer system.
Document Number: 38-12025 Rev. *R
Page 3 of 46
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For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. Table 1 lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted in this table.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
CY8C29x66 upto 4
64
16 12
4
4
4
4
12 2K
32K
CY8C27x43 upto 2
44
8
12
12 256 16K
Bytes
Training
CY8C24x94 56
1
4
4
48
12
2
2
2
2
6
6
1K
16K
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CY8C24x23A upto 1
24
256 4K
Bytes
[1]
[1]
[2]
CY8C21x34 upto 1
28
4
4
0
28
8
0
0
0
2
2
0
4
4
3
512 8K
Bytes
Cypros Consultants
CY8C21x23 16
1
256 4K
Bytes
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
CY8C20x34 upto 0
28
28
512 8K
Bytes
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
For in depth information, along with detailed programming infor-
mation, see the PSoC Technical Reference Manual for
CY8C21x34 PSoC devices.
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense.
Document Number: 38-12025 Rev. *R
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Code Generation Tools
Development Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
PSoC Designer Software Subsystems
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication inter-
faces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
On-Chip Controllers that match your system requirements.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional Integrated Development
Environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
Hybrid Designs
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 38-12025 Rev. *R
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Organize and Connect
Designing with PSoC Designer
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
Select Components
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I C-bus, for example), and the logic to control how they interact
with one another (called valuators).
2
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 38-12025 Rev. *R
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Units of Measure
Document Conventions
A units of measure table is located in the Electrical Specifications
section. Table 2 on page 7 lists all the abbreviations used to
measure the PSoC devices.
Acronyms Used
The following table lists the acronyms that are used in this
document.
Numeric Naming
Table 2. Acronyms Used
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
EEPROM
external crystal oscillator
electrically erasable programmable read-only
memory
FSR
GPIO
GUI
full scale range
general purpose I/O
graphical user interface
human body model
in-circuit emulator
HBM
ICE
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
I/O
IPOR
LSb
imprecise power on reset
least-significant bit
low voltage detect
LVD
MSb
PC
most-significant bit
program counter
PLL
phase-locked loop
power on reset
POR
PPOR
PSoC
PWM
SC
precision power on reset
Programmable System-on-Chip
pulse width modulator
switched capacitor
slow IMO
SLIMO
SMP
SRAM
switch mode pump
static random access memory
Document Number: 38-12025 Rev. *R
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Pin Information
The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with
a “P”) is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of
Digital I/O.
16-Pin Part Pinout
Figure 3. CY8C21234 16-Pin PSoC Device
A, I,M, P0[7]
A, I,M, P0[5]
A, I,M, P0[3]
A, I,M, P0[1]
SMP
Vdd
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P0[6], A,I, M
P0[4], A,I, M
P0[2], A,I, M
P0[0], A,I, M
P1[4],EXTCLK,M
P1[2],M
SOIC
Vss
M,I2C SCL,P1[1]
Vss
P1[0],I2CSDA,M
Table 3. Pin Definitions - CY8C21234 16-Pin (SOIC)
Type
Pin No.
Name
Description
Digital
I/O
Analog
I, M
1
P0[7]
Analog column mux input.
Analog column mux input.
2
I/O
I, M
I, M
I, M
P0[5]
P0[3]
P0[1]
SMP
Vss
3
I/O
Analog column mux input, integrating input.
Analog column mux input, integrating input.
Switch Mode Pump (SMP) connection to required external components.
Ground connection.
4
I/O
5
Power
Power
I/O
6
2
[3]
7
M
P1[1]
Vss
I C Serial Clock (SCL), ISSP-SCLK
.
8
Power
I/O
Ground connection.
2
[3]
9
M
P1[0]
P1[2]
P1[4]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I C Serial Data (SDA), ISSP-SDATA ..
10
11
12
13
14
15
16
I/O
M
I/O
M
Optional External Clock Input (EXTCLK).
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
I/O
I, M
I, M
I, M
I, M
I/O
I/O
I/O
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details.
Document Number: 38-12025 Rev. *R
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20-Pin Part Pinout
Figure 4. CY8C21334 20-Pin PSoC Device
A, I,M, P0[7]
A, I,M, P0[5]
A, I,M, P0[3]
A, I,M, P0[1]
Vss
Vdd
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
P0[6], A,I, M
P0[4], A,I, M
P0[2], A,I, M
P0[0], A,I, M
XRES
P1[6],M
P1[4],EXTCLK,M
P1[2],M
SSOP
M,I2C SCL,P1[7]
M,I2C SDA,P1[5]
M,P1[3]
M,I2C
SCL,P1[1]
Vss
P1[0],I2C SDA,M
10
Table 4. Pin Definitions - CY8C21334 20-Pin (SSOP)
Type
Pin No.
Name
Description
Digital
I/O
Analog
I, M
1
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Analog column mux input.
Analog column mux input.
2
I/O
I, M
I, M
I, M
3
I/O
Analog column mux input, integrating input.
Analog column mux input, integrating input.
Ground connection.
4
I/O
5
Power
I/O
2
6
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I C Serial Clock (SCL).
2
7
I/O
I C Serial Data (SDA).
8
I/O
2
[3]
9
I/O
I C Serial Clock (SCL), ISSP-SCLK
.
10
11
12
13
14
15
16
17
18
19
20
Power
I/O
Ground connection.
2
[3]
M
M
M
M
P1[0]
P1[2]
P1[4]
P1[6]
I C Serial Data (SDA), ISSP-SDATA
.
I/O
I/O
Optional External Clock Input (EXTCLK).
I/O
Input
I/O
XRES Active high external reset with internal pull down.
I, M
I, M
I, M
I, M
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
I/O
I/O
I/O
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Document Number: 38-12025 Rev. *R
Page 9 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
28-Pin Part Pinout
Figure 5. CY8C21534 28-Pin PSoC Device
A, I,M, P0[7]
A, I,M, P0[5]
A, I,M, P0[3]
A, I,M, P0[1]
M,P2[7]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P0[6], A,I, M
P0[4], A,I, M
P0[2], A,I, M
P0[0], A,I, M
P2[6],M
M,P2[5]
M, P2[3]
M, P2[1]
P2[4],M
P2[2],M
SSOP
Vss
P2[0],M
XRES
P1[6],M
M,I2C SCL,P1[7]
M,I2C SDA,P1[5]
M,P1[3]
P1[4],EXTCLK,M
P1[2],M
P1[0],I2CSDA,M
M,I2C SCL,P1[1]
Vss
Table 5. Pin Definitions - CY8C21534 28-Pin (SSOP)
Type
Pin No.
Name
Description
Digital
I/O
Analog
I, M
1
2
3
4
5
6
7
8
9
P0[7]
Analog column mux input.
I/O
I, M
I, M
I, M
M
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
Analog column mux input and column output.
I/O
Analog column mux input and column output, integrating input.
Analog column mux input, integrating input.
I/O
I/O
I/O
M
I/O
I, M
I, M
Direct switched capacitor block input.
Direct switched capacitor block input.
Ground connection.
I/O
Power
I/O
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I C Serial Clock (SCL).
2
I/O
I C Serial Data (SDA).
I/O
2
[3]
I/O
I C Serial Clock (SCL), ISSP-SCLK
.
Power
I/O
Ground connection.
2
[3]
M
M
M
M
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I C Serial Data (SDA), ISSP-SDATA .
Optional External Clock Input (EXTCLK).
I/O
I/O
I/O
Input
I/O
Active high external reset with internal pull down.
Direct switched capacitor block input.
I, M
I, M
M
I/O
Direct switched capacitor block input.
I/O
I/O
M
I/O
I, M
I, M
I, M
I, M
Analog column mux input.
Analog column mux input.
Analog column mux input
Analog column mux input.
Supply voltage.
I/O
I/O
I/O
Power
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
Document Number: 38-12025 Rev. *R
Page 10 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
32-Pin Part Pinout
Figure 6. CY8C21434 32-Pin PSoC Device
Figure 7. CY8C21634 32-Pin PSoC Device
Figure 8. CY8C21434 32-Pin Sawn PSoC Device Sawn
Figure 9. CY8C21634 32-Pin Sawn PSoC Device Sawn
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
1
2
3
4
5
6
7
8
P0[0], A, I, M
A, I, M, P0[1]
24
1
2
3
4
5
6
7
8
P0[0], A, I, M
24
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
23 P2[6], M
22 P2[4], M
P2[2], M
20 P2[0], M
P3[2], M
23 P2[6], M
22 P2[4], M
P2[2], M
20 P2[0], M
P3[2], M
21
21
QFN
(Top View)
QFN
(Top View)
19
19
M, P3[1]
M, 12C SCL, P1[7]
Vss
18 P3[0], M
17 XRES
18 P3[0], M
17 XRES
M, 12C SCL, P1[7]
Document Number: 38-12025 Rev. *R
Page 11 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
[4]
Table 6. Pin Definitions - CY8C21434/CY8C21634 32-Pin (QFN)
Type
Analog
I, M
Pin
No.
Name
P0[1]
Description
Digital
I/O
1
2
3
4
5
6
6
Analog column mux input, integrating input.
I/O
M
M
M
M
M
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
SMP
I/O
I/O
I/O
I/O
In CY8C21434 part.
Power
Switch Mode Pump (SMP) connection to required external components in
CY8C21634 part.
7
7
8
9
I/O
M
P3[1]
Vss
In CY8C21434 part.
Power
I/O
Ground connection in CY8C21634 part.
2
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I C Serial Clock (SCL).
2
I/O
I C Serial Data (SDA).
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
2
[3]
I/O
I C Serial Clock (SCL), ISSP-SCLK
.
Power
I/O
Ground connection.
2
[3]
M
M
M
M
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I C Serial Data (SDA), ISSP-SDATA
I/O
I/O
Optional External Clock Input (EXTCLK).
I/O
Input
I/O
Active high external reset with internal pull down.
M
I/O
M
I/O
M
I/O
M
I/O
M
I/O
M
I/O
I, M
I, M
I, M
I, M
Analog column mux input.
Analog column mux input.
Analog column mux input.
Analog column mux input.
Supply voltage.
I/O
I/O
I/O
Power
I/O
I, M
I, M
I, M
P0[7]
P0[5]
P0[3]
Vss
Analog column mux input.
Analog column mux input.
Analog column mux input, integrating input.
Ground connection.
I/O
I/O
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 38-12025 Rev. *R
Page 12 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Figure 10. CY8C21001 56-Pin PSoC Device
Vss
56
55
Vdd
1
2
AI, P0[7]
AI, P0[5]
AI, P0[3]
P0[6], AI
P0[4], AI
P0[2], AI
3
4
5
6
54
53
AI, P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
P0[0], AI
P2[6]
52
51
P2[4]
P2[2]
P2[0]
NC
7
8
9
50
49
48
10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
NC
NC
NC
NC
11
12
13
P3[2]
P3[0]
CCLK
HCLK
XRES
NC
OCDE
OCDO
SMP
14
SSOP
15
16
17
Vss
Vss
NC
NC
NC
18
19
20
P3[3]
P3[1]
NC
NC
21
22
23
NC
NC
P1[6]
I2C SCL, P1[7]
P1[4], EXTCLK
P1[2]
I2C SDA, P1[5]
24
25
33
32
NC
P1[3]
P1[0], I2C
NC
SDA, SDATA
26
27
28
31
30
SCLK, I2C SCL, P1[1]
Vss
NC
29
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP)
Type
Pin No.
Pin Name
Description
Digital
Power
Analog
1
Vss
Ground connection.
Analog column mux input.
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
3
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
4
5
6
7
8
I
I
Direct switched capacitor block input.
Direct switched capacitor block input.
No connection.
9
10
11
12
13
14
15
16
17
18
NC
No connection.
NC
No connection.
NC
No connection.
OCD
OCDE
OCDO
SMP
Vss
OCD even data I/O.
OCD
OCD odd data output.
Power
Power
Power
Switch Mode Pump (SMP) connection to required external components.
Ground connection.
Vss
Ground connection.
Document Number: 38-12025 Rev. *R
Page 13 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) (continued)
Type
Pin No.
19
Pin Name
Description
Digital
I/O
Analog
P3[3]
P3[1]
NC
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
No connection.
NC
No connection.
2
I/O
I/O
P1[7]
P1[5]
NC
I C Serial Clock (SCL).
2
I C Serial Data (SDA).
No connection.
I/O
P1[3]
P1[1]
Vss
I
.
FMTEST
2
[3]
I/O
Crystal Input (XTALin), I C Serial Clock (SCL), ISSP-SCLK ..
Power
Ground connection.
No connection.
NC
NC
No connection.
2
[3]
I/O
I/O
I/O
I/O
P1[0]
P1[2]
P1[4]
P1[6]
NC
Crystal Output (XTALout), I C Serial Data (SDA), ISSP-SDATA ..
V
.
FMTEST
Optional External Clock Input (EXTCLK).
No connection.
NC
No connection.
NC
No connection.
NC
No connection.
NC
No connection.
NC
No connection.
Input
OCD
OCD
I/O
XRES
HCLK
CCLK
P3[0]
P3[2]
NC
Active high external reset with internal pull down.
OCD high-speed clock output.
OCD CPU clock output.
I/O
No connection.
No connection.
NC
I/O
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I/O
I/O
I/O
I/O
I
I
I
I
Analog column mux input.
I/O
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
I/O
I/O
Power
Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Document Number: 38-12025 Rev. *R
Page 14 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Register Reference
This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, refer the PSoC Technical Reference
Manual.
Register Conventions
The register conventions specific to this section are listed in Table 8.
Table 8. Register Conventions
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into
two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user
is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and must not be accessed.
Document Number: 38-12025 Rev. *R
Page 15 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Table 9. Register Map 0 Table: User Space
Name
PRT0DR
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
40
Name
ASE10CR0
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
C0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
PRT0IE
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
ASE11CR0
RW
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
CUR_PP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
STK_PP
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
IDX_PP
RW
RW
RW
RW
#
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
AMX_IN
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RC
W
W
RW
#
AMUXCFG
PWM_CR
RES_WDT
#
CMP_CR0
CMP_CR1
#
W
RW
#
RW
DEC_CR0
DEC_CR1
RW
RW
#
ADC0_CR
ADC1_CR
#
#
W
RW
#
#
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
W
RW
#
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
DAC_D
RW
#
CPU_SCR1
CPU_SCR0
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12025 Rev. *R
Page 16 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Table 10. Register Map 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
Name
ASE10CR0
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
ASE11CR0
RW
GDI_O_IN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
GDI_E_IN
GDI_O_OU
GDI_E_OU
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
CLK_CR1
ABF_CR0
AMD_CR0
CMP_GO_EN
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
ADC0_TR
ADC1_TR
RW
RW
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
CLK_CR3
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
RW
RW
RW
RW
RW
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
ACE00CR1
ACE00CR2
RW
RW
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
ACE01CR1
ACE01CR2
RW
RW
CPU_F
RL
FLS_PR1
RW
DAC_CR
RW
#
CPU_SCR1
CPU_SCR0
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12025 Rev. *R
Page 17 of 46
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Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up to date electrical specifications,
visit the web site http://www.cypress.com/psoc.
o
o
o
Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C as specified, except where noted.
A
J
Refer Table 23 on page 27 for the electrical specifications on the IMO using SLIMO mode.
Figure 11. Voltage versus CPU Frequency
Figure 14. IMO Frequency Trim Options
5.25
4.75
5.25
4.75
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
2.40
SLIMO
Mode=1
SLIMO
Mode=0
3.00
2.40
SLIMO SLIMO
Mode=1 Mode=1
93 kHz
12 MHz
CPUFrequency
24 MHz
3 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMOFrequency
Table 11 lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol
Unit of Measure
degree Celsius
Symbol
μW
mA
ms
mV
nA
Unit of Measure
microwatts
o
C
dB
fF
decibels
milli-ampere
milli-second
milli-volts
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
ns
kilohertz
nV
kilohm
Ω
ohm
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
megahertz
megaohm
pA
picoampere
picofarad
pF
microampere
microfarad
microhenry
microsecond
microvolts
pp
peak-to-peak
parts per million
picosecond
samples per second
ppm
ps
sps
σ
V
sigma: one standard deviation
volts
microvolts root-mean-square
Document Number: 38-12025 Rev. *R
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Absolute Maximum Ratings
Symbol Description
Min
Typ
Max
Units
Notes
o
T
Storage Temperature
-55
25
+100
C
Higher storage temperatures
STG
reduce data retention time. Recom-
mended storage temperature is
o
o
+25 C ± 25 C. Extended duration
o
storage temperatures above 65 C
degrade reliability.
o
T
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
–
–
–
+85
C
A
Vdd
-0.5
+6.0
V
V
V
Vss -
0.5
Vdd +
0.5
IO
V
DC Voltage Applied to Tri-state
Vss -
0.5
–
Vdd +
0.5
V
IOZ
I
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
-25
2000
–
–
–
–
+50
–
mA
V
MIO
ESD
LU
Human Body Model ESD.
200
mA
Operating Temperature
Symbol
Description
Min
-40
-40
Typ
–
Max
+85
Units
Notes
o
T
Ambient Temperature
Junction Temperature
C
o
A
T
–
+100
C
The temperature rise from ambient
to junction is package specific. See
Table 38 on page 40. The user must
limit the power consumption to
comply with this requirement.
J
Document Number: 38-12025 Rev. *R
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DC Electrical Characteristics
DC Chip-Level Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 12. DC Chip-Level Specifications
Symbol
Description
Min
2.40
–
Typ
–
Max
5.25
4
Units
Notes
Vdd
Supply Voltage
V
See Table 21 on page 25.
I
I
I
Supply Current, IMO = 24 MHz
3
mA Conditions are Vdd = 5.0V,
DD
o
T = 25 C, CPU = 3 MHz, 48 MHz
disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
A
Supply Current, IMO = 6 MHz using SLIMO
Mode.
–
–
–
1.2
1.1
2.6
2
1.5
4.
mA Conditions are Vdd = 3.3V,
DD3
DD27
o
T = 25 C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
A
Supply Current, IMO = 6 MHz using SLIMO
Mode.
mA Conditions are Vdd = 2.55V,
o
T = 25 C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
A
VC2 = 23.4 kHz, VC3 = 0.091 kHz.
o
o
I
I
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator active.
Mid temperature range.
μA
Vdd = 2.55V, 0 C ≤ T ≤ 40 C.
A
SB27
o
o
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and internal slow oscillator active.
–
2.8
5
μA
V
Vdd = 3.3V, -40 C ≤ T ≤ 85 C.
SB
A
V
V
Reference Voltage (Bandgap)
Reference Voltage (Bandgap)
Analog Ground
1.28
1.16
1.30
1.30
1.32
1.33
Trimmed for appropriate Vdd.
Vdd = 3.0V to 5.25V.
REF
V
Trimmed for appropriate Vdd. Vdd =
2.4V to 3.0V.
REF27
AGND
V
V
V
REF
V
REF
REF
- 0.003
+ 0.003
DC General Purpose I/O Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 13. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Min
4
Typ
5.6
5.6
–
Max
Units
kΩ
kΩ
Notes
R
Pull up Resistor
8
8
–
PU
PD
OH
R
Pull down Resistor
High Output Level
4
V
Vdd -
1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
V
Low Output Level
–
–
–
0.75
–
V
IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
OL
I
I
High Level Source Current
10
mA
V
= Vdd-1.0V, see the limitations
OH
OH
of the total current in the note for
VOH
Low Level Sink Current
Input Low Level
25
–
–
–
–
mA
V
V
=0.75V, seethelimitationsofthe
OL
OL
total current in the note for VOL
V
0.8
Vdd = 3.0 to 5.25.
IL
Document Number: 38-12025 Rev. *R
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Table 13. 5V and 3.3V DC GPIO Specifications (continued)
Symbol Description
Min
2.1
–
Typ
–
Max
Units
V
Notes
Vdd = 3.0 to 5.25.
V
Input High Level
Input Hysteresis
IH
H
V
I
60
1
–
–
mV
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
nA Gross tested to 1 μA.
pF
IL
C
–
3.5
10
Package and pin dependent.
IN
o
Temp = 25 C.
C
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 C.
OUT
o
Table 14. 2.7V DC GPIO Specifications
Symbol Description
Min
4
Typ
5.6
5.6
–
Max
Units
kΩ
kΩ
Notes
R
Pull up Resistor
8
8
–
PU
PD
OH
R
Pull down Resistor
High Output Level
4
V
Vdd -
0.4
V
IOH = 2.5 mA (6.25 Typ), Vdd = 2.4
to 3.0V (16 mA maximum, 50 mA Typ
combined IOH budget).
V
Low Output Level
–
–
0.75
V
IOL = 10 mA, Vdd = 2.4 to 3.0V (90
mA maximum combined IOL
budget).
OL
I
I
High Level Source Current
Low Level Sink Current
2.5
10
–
–
–
–
mA
mA
V
= Vdd-0.4V, see the limitations of
OH
OH
the total current in the note for VOH
V
= 0.75V, see the limitations of the
OL
OL
total current in the note for VOL
V
V
V
I
Input Low Level
–
2.0
–
–
–
0.75
–
V
V
Vdd = 2.4 to 3.0.
IL
IH
H
Input High Level
Vdd = 2.4 to 3.0.
Input Hysteresis
90
1
–
mV
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
–
nA Gross tested to 1 μA.
pF
IL
C
–
3.5
10
Package and pin dependent.
IN
o
Temp = 25 C.
C
Capacitive Load on Pins as Output
–
3.5
10
pF
Package and pin dependent.
Temp = 25 C.
OUT
o
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 15. 5V DC Operational Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
Notes
V
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
mV
OSOA
o
TCV
–
μV/ C
OSOA
I
I
Input Leakage Current (Port 0 Analog Pins 7:1)
Input Leakage Current (Port 0, Pin 0 Analog pin)
Input Capacitance (Port 0 Analog Pins)
–
200
50
–
pA
nA
pF
Gross tested to 1 μA.
EBOA
EBOA00
–
–
Gross tested to 1 μA.
C
–
4.5
9.5
Package and pin dependent.
INOA
o
Temp = 25 C.
V
Common Mode Voltage Range
0.0
–
Vdd - 1
V
CMOA
G
I
Open Loop Gain
–
–
80
10
–
dB
OLOA
Amplifier Supply Current
30
μA
SOA
Document Number: 38-12025 Rev. *R
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Table 16. 3.3V DC Operational Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
Notes
V
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
mV
OSOA
o
TCV
–
μV/ C
OSOA
EBOA
EBOA00
I
I
–
200
50
–
pA
nA
Gross tested to 1 μA.
Gross tested to 1 μA.
Input Leakage Current (Port 0, Pin 0 Analog
pin)
–
–
C
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 C.
INOA
o
V
Common Mode Voltage Range
Open Loop Gain
0
–
–
–
Vdd - 1
V
CMOA
G
I
80
10
–
dB
μA
OLOA
Amplifier Supply Current
30
SOA
Table 17. 2.7V DC Operational Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
Notes
V
Input Offset Voltage (absolute value)
Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
mV
OSOA
o
TCV
–
μV/ C
OSOA
EBOA
EBOA00
I
I
–
200
50
–
pA
nA
Gross tested to 1 μA.
Gross tested to 1 μA.
Input Leakage Current (Port 0, Pin 0 Analog
pin)
–
–
C
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 C.
INOA
o
V
Common Mode Voltage Range
Open Loop Gain
0
–
–
–
Vdd - 1
V
CMOA
G
I
80
10
–
dB
μA
OLOA
Amplifier Supply Current
30
SOA
DC Low Power Comparator Specifications
Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V at 25°C and are for design guidance only.
Table 18. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
Low power comparator (LPC) reference
voltage range
0.2
–
Vdd - 1
V
REFLPC
I
LPC supply current
LPC voltage offset
–
–
10
40
30
μA
mV
SLPC
V
2.5
OSLPC
Document Number: 38-12025 Rev. *R
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DC Switch Mode Pump Specifications
Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 19. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
[5]
V
V
V
5V Output Voltage from Pump
4.75
5.0
5.25
3.60
2.80
V
Configuration of footnote.
PUMP5V
Average, neglecting ripple.
SMP trip voltage is set to 5.0V.
[5]
3.3V Output Voltage from Pump
2.6V Output Voltage from Pump
Available Output Current
3.00
2.45
3.25
2.55
V
V
Configuration of footnote.
PUMP3V
PUMP2V
PUMP
Average, neglecting ripple.
SMP trip voltage is set to 3.25V.
[5]
Configuration of footnote.
Average, neglecting ripple.
SMP trip voltage is set to 2.55V.
[5]
I
Configuration of footnote.
V
V
V
= 1.8V, V
= 1.5V, V
= 1.3V, V
= 5.0V
= 3.25V
= 2.55V
5
8
8
–
–
–
–
–
–
mA
mA
mA
SMP trip voltage is set to 5.0V.
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 2.55V.
BAT
BAT
BAT
PUMP
PUMP
PUMP
[5]
V
V
V
V
Input Voltage Range from Battery
Input Voltage Range from Battery
Input Voltage Range from Battery
1.8
1.0
1.0
1.2
–
–
–
–
–
5
5.0
3.3
2.8
–
V
V
V
V
Configuration of footnote.
BAT5V
SMP trip voltage is set to 5.0V.
[5]
Configuration of footnote.
BAT3V
SMP trip voltage is set to 3.25V.
[5]
Configuration of footnote.
BAT2V
SMP trip voltage is set to 2.55V.
[5]
Minimum Input Voltage from Battery to Start
Pump
Configuration of footnote.
BATSTART
o
o
0 C ≤ T ≤ 100. 1.25V at T = -40 C.
A
A
[5]
ΔV
Line Regulation (over Vi range)
Load Regulation
–
%V
Configuration of footnote.
V is
O
PUMP_Line
PUMP_Load
PUMP_Rippl
O
the “Vdd Value for PUMP Trip”
specified by the VM[2:0] setting in
the DC POR and LVD Specification,
Table 21 on page 25.
[5]
ΔV
–
5
–
%V
Configuration of footnote.
V is
O
O
the “Vdd Value for PUMP Trip”
specified by the VM[2:0] setting in
the DC POR and LVD Specification,
Table 21 on page 25.
[5]
ΔV
e
Output Voltage Ripple (depends on cap/load)
Efficiency
–
100
50
–
–
mVpp Configuration of footnote. Load is
5 mA.
[5]
E
35
%
Configuration of footnote.
Load is 5 mA. SMP trip voltage is set
to 3.25V.
3
2
E
Efficiency
35
80
–
%
For I load = 1mA, V
BAT
= 2.55V,
PUMP
V
= 1.3V,
10 uH inductor, 1 uF capacitor, and
Schottky diode.
F
Switching Frequency
Switching Duty Cycle
–
–
1.3
50
–
–
MHz
%
PUMP
DC
PUMP
Document Number: 38-12025 Rev. *R
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Figure 15. Basic Switch Mode Pump Circuit
D1
Vdd
VPUMP
L1
SMP
Vss
+
C1
VBAT
Battery
PSoC
DC Analog Mux Bus Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 20. DC Analog Mux Bus Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
R
Switch Resistance to Common Analog Bus
–
–
400
800
Ω
Ω
Vdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
SW
R
Resistance of Initialization Switch to Vdd
–
–
800
Ω
VDD
Note
5. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 15.
Document Number: 38-12025 Rev. *R
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DC POR and LVD Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 21. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Min
Typ
Max
Units
Notes
Vdd must be greater than or equal
to 2.5V during startup, reset from
the XRES pin, or reset from
Watchdog.
V
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
PPOR0
PPOR1
PPOR2
V
–
V
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
[6]
V
V
V
V
V
V
V
V
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51
2.99
V
V
V
V
V
V
V
V
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
[7]
3.09
3.20
4.55
4.75
4.83
4.95
Vdd Value for PUMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
[8]
V
V
V
V
V
V
V
V
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62
3.09
3.16
V
V
V
V
V
V
V
V
PUMP0
PUMP1
PUMP2
PUMP3
PUMP4
PUMP5
PUMP6
PUMP7
[9]
3.32
4.74
4.83
4.92
5.12
Notes
6. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.
7. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.
8. Always greater than 50 mV above VLVD0
.
.
9. Always greater than 50 mV above VLVD3
Document Number: 38-12025 Rev. *R
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DC Programming Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 22. DC Programming Specifications
Symbol
Vdd
Description
Min
2.70
–
Typ
–
Max
Units
V
Notes
Supply Voltage for Flash Write Operations
–
IWRITE
I
Supply Current During Programming or
Verify
5
25
mA
DDP
V
V
Input Low Voltage During Programming or
Verify
–
2.2
–
–
–
–
–
–
–
0.8
–
V
V
ILP
Input High Voltage During Programming or
Verify
IHP
I
I
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
0.2
1.5
mA
mA
V
Driving internal pull down resistor.
Driving internal pull down resistor.
ILP
Input Current when Applying Vihp to P1[0]
or P1[1] During Programming or Verify
–
IHP
V
V
Output Low Voltage During Programming or
Verify
–
Vss +
0.75
OLV
OutputHighVoltageDuringProgrammingor Vdd - 1.0
Vdd
V
OHV
Verify
[10]
Flash
Flash
Flash
Flash Endurance (per block)
50,000
1,800,000
10
–
–
–
–
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.
ENPB
ENT
DR
[11]
Flash Endurance (total)
Flash Data Retention
Years
Notes
10. The 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4V to 3.0V, 3.0V to
3.6V and 4.75V to 5.25V.
11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to
the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more
information.
Document Number: 38-12025 Rev. *R
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AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 23. 5V and 3.3V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
[12,13,14]
F
F
F
Internal Main Oscillator Frequency for 24
MHz
23.4
24
24.6
MHz Trimmed for 5V or 3.3V
operation using factory trim
values. See Figure 14 on
page 18. SLIMO mode = 0.
IMO24
[12,13,14]
[12,13]
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.5
MHz Trimmed for 5V or 3.3V
operation using factory trim
values. See Figure 14 on
page 18. SLIMO mode = 1.
IMO6
CPU1
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
0.93
24
24.6
MHz 24 MHz only for SLIMO
mode = 0.
[13,14]
F
F
0.93
0
12
48
12.3
MHz
CPU2
BLK5
0
[12,13,15]
Digital PSoC Block Frequency (5V Nominal)
49.2
MHz Refer to AC Digital Block
Specifications on page 31.
[13,15]
F
Digital PSoC Block Frequency (3.3V
Nominal)
0
24
24.6
MHz
BLK33
F
F
Internal Low Speed Oscillator Frequency
15
5
32
–
64
–
kHz
32K1
Internal Low Speed Oscillator (ILO)
Untrimmed Frequency
kHz After a reset and before the
m8c starts to run, the ILO is
not trimmed. See the
32K_U
System Resets section of
the PSoC Technical
Reference Manual for
details on this timing.
Jitter32k
Jitter32k
32 kHz RMS Period Jitter
–
–
100
1400
–
200
–
ns
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
T
10
40
20
–
–
μs
%
XRST
DC24M
50
60
80
–
DC
Internal Low Speed Oscillator Duty Cycle
24 MHz Trim Step Size
50
%
ILO
Step24M
Fout48M
50
kHz
[12,14]
48 MHz Output Frequency
46.8
48.0
49.2
MHz Trimmed. Using factory trim
values.
Jitter24M1
24 MHz Peak-to-Peak Period Jitter (IMO)
–
–
600
–
ps
F
Maximum frequency of signal on row input
or row output.
12.3
250
100
MHz
MAX
SR
Power Supply Slew Rate
–
–
–
V/ms Vdd slew rate during power
up.
POWER_UP
T
Time from end of POR to CPU executing
code
16
ms
Power up from 0V. See the
System Resets section of
the PSoC Technical
POWERUP
Reference Manual.
Notes
12. 4.75V < Vdd < 5.25V.
13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
14. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
15. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 38-12025 Rev. *R
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Table 24. 2.7V AC Chip-Level Specifications
Symbol Description
Internal Main Oscillator Frequency for 12 MHz 11.5
Min
Typ
Max
Units
Notes
0
[16,17,18]
F
12
12.7
MHz Trimmed for 2.7V
operation using factory
trim values. See Figure
14 on page 18. SLIMO
mode = 1.
IMO12
[16,17,18]
F
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.5
MHz Trimmed for 2.7V
operation using factory
trim values. See Figure
14 on page 18. SLIMO
mode = 1.
IMO6
[16,17]
F
F
CPU Frequency (2.7V Nominal)
0.093
0
3
3.15
MHz 24 MHz only for SLIMO
mode = 0.
CPU1
[16,17,18]
Digital PSoC Block Frequency (2.7V Nominal)
12
12.5
MHz Refer to AC Digital Block
Specifications on page
31.
BLK27
F
F
Internal Low Speed Oscillator Frequency
8
5
32
–
96
–
kHz
32K1
Internal Low Speed Oscillator (ILO) Untrimmed
Frequency
kHz After a reset and before
the m8c starts to run, the
ILO is not trimmed. See
the System Resets
32K_U
section of the PSoC
Technical Reference
Manual for details on
timing this
Jitter32k
Jitter32k
32 kHz RMS Period Jitter
–
–
150
1400
–
200
–
ns
32 kHz Peak-to-Peak Period Jitter
External Reset Pulse Width
T
10
20
–
–
μs
%
XRST
DC
Internal Low Speed Oscillator Duty Cycle
50
80
ILO
F
Maximum frequency of signal on row input or
row output.
–
12.3
250
100
MHz
MAX
SR
Power Supply Slew Rate
–
–
–
V/ms Vdd slew rate during
power up.
POWER_UP
T
Time from end of POR to CPU executing code
16
ms
Power up from 0V. See
the System Resets
section of the PSoC
Technical Reference
Manual.
POWERUP
Figure 16. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
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Figure 17. 32 kHz Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
Notes
16. 2.4V < Vdd < 3.0V.
17. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
18. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.
Document Number: 38-12025 Rev. *R
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AC General Purpose I/O Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 25. 5V and 3.3V AC GPIO Specifications
Symbol
Description
Min
0
Typ
–
Max
12
18
18
–
Units
Notes
F
GPIO Operating Frequency
MHz Normal Strong Mode
GPIO
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25V, 10% - 90%
2
–
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
7
27
22
7
–
Table 26. 2.7V AC GPIO Specifications
Symbol
Description
Min
0
Typ
–
Max
3
Units
Notes
F
GPIO Operating Frequency
MHz Normal Strong Mode
GPIO
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
6
–
50
ns
ns
ns
ns
Vdd = 2.4 to 3.0V, 10% - 90%
6
–
50
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
18
18
40
40
120
120
Figure 18. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 27. AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
T
Comparator Mode Response Time, 50 mV
Overdrive
100
200
ns
ns
Vdd ≥ 3.0V.
2.4V < Vcc < 3.0V.
COMP
AC Low Power Comparator Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V at 25°C and are for design guidance only.
Table 28. AC Low Power Comparator Specifications
Symbol
Description
LPC response time
Min
Typ
Max
Units
Notes
T
–
–
50
μs
≥ 50 mV overdrive comparator
reference set within V
RLPC
.
REFLPC
Document Number: 38-12025 Rev. *R
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AC Analog Mux Bus Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 29. AC Analog Mux Bus Specifications
Symbol
Description
Min
Typ
Max
3.17
Units
Notes
F
Switch Rate
–
–
MHz
SW
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 30. 5V and 3.3V AC Digital Block Specifications
Function
All
Functions
Description
Min
Typ
Max
49.2
24.6
–
Units
Notes
Maximum Block Clocking Frequency (> 4.75V)
Maximum Block Clocking Frequency (< 4.75V)
Capture Pulse Width
MHz 4.75V < Vdd < 5.25V.
MHz 3.0V < Vdd < 4.75V.
[19]
Timer
50
–
–
–
–
–
–
ns
Maximum Frequency, No Capture
Maximum Frequency, With or Without Capture
Enable Pulse Width
–
–
49.2
24.6
–
MHz 4.75V < Vdd < 5.25V.
MHz
Counter
50
–
ns
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
49.2
24.6
MHz 4.75V < Vdd < 5.25V.
MHz
–
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
20
50
50
–
–
–
–
–
–
–
–
ns
Synchronous Restart Mode
Disable Mode
ns
–
ns
Maximum Frequency
49.2
49.2
MHz 4.75V < Vdd < 5.25V.
MHz 4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
–
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
–
–
24.6
8.2
MHz
SPIM
Maximum Input Clock Frequency
MHz Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS
Maximum Input Clock Frequency
–
50
–
–
–
–
4.1
–
MHz
ns
Width of SS_ Negated Between Transmissions
Transmitter Maximum Input Clock Frequency
24.6
MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
49.2
MHz Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Receiver
Maximum Input Clock Frequency
–
–
–
–
24.6
49.2
MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
MHz Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
Note
19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12025 Rev. *R
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Table 31. 2.7V AC Digital Block Specifications
Function
All
Description
Min
Typ
Max
Units
Notes
Maximum Block Clocking Frequency
12.7
MHz 2.4V < Vdd < 3.0V.
Functions
[20]
Timer
Capture Pulse Width
100
–
–
–
–
–
–
ns
Maximum Frequency, With or Without Capture
Enable Pulse Width
–
100
–
12.7
–
MHz
ns
Counter
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
12.7
12.7
MHz
MHz
–
Dead Band
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
20
100
100
–
–
–
–
–
–
–
–
ns
ns
–
ns
Maximum Frequency
12.7
12.7
MHz
MHz
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
12.7
6.35
MHz
SPIM
MHz Maximum data rate at 3.17
MHz due to 2 x over clocking.
SPIS
Maximum Input Clock Frequency
–
100
–
–
–
–
4.1
–
MHz
ns
Width of SS_ Negated Between Transmissions
Maximum Input Clock Frequency
Transmitter
Receiver
12.7
MHz Maximum data rate at 1.59
MHz due to 8 x over clocking.
Maximum Input Clock Frequency
–
–
12.7
MHz Maximum data rate at 1.59
MHz due to 8 x over clocking.
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C
A
A
and are for design guidance only.
Table 32. 5V AC External Clock Specifications
Symbol
Description
Min
0.093
20.6
20.6
150
Typ
–
Max
24.6
5300
–
Units
MHz
ns
F
–
–
–
Frequency
High Period
Low Period
OSCEXT
–
–
ns
Power Up IMO to Switch
–
–
μs
Note
20. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12025 Rev. *R
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Table 33. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
F
Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz Maximum CPU frequency is 12
MHz at 3.3V. With the CPU clock
divider set to 1, the external clock
must adhere to the maximum
frequency and duty cycle
OSCEXT
requirements.
F
Frequency with CPU Clock divide by 2 or
greater
0.186
–
24.6
MHz Ifthefrequencyoftheexternalclock
is greater than 12 MHz, the CPU
clock divider must be set to 2 or
greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
OSCEXT
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
41.7
41.7
150
–
–
–
5300
ns
ns
μs
–
–
Table 34. 2.7V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
0
F
Frequency with CPU Clock divide by 1
0.093
–
3.08
MHz Maximum CPU frequency is 3 MHz
at 2.7V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
OSCEXT
F
Frequency with CPU Clock divide by 2 or
greater
0.186
–
6.35
MHz Ifthefrequencyoftheexternalclock
is greater than 3 MHz, the CPU
clock divider must be set to 2 or
greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
OSCEXT
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
160
160
150
–
–
–
5300
ns
ns
μs
–
–
Document Number: 38-12025 Rev. *R
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AC Programming Specifications
Table 35 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for
A
A
design guidance only.
Table 35. AC Programming Specifications
Symbol Description
Rise Time of SCLK
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
T
T
T
T
F
T
T
T
T
T
T
RSCLK
Fall Time of SCLK
1
–
ns
FSCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
SSCLK
HSCLK
SCLK
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
10
40
–
–
ERASEB
WRITE
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
–
45
50
70
–
3.6 < Vdd
DSCLK
DSCLK3
DSCLK2
ERASEALL
–
–
ns
3.0 ≤ Vdd ≤ 3.6
2.4 ≤ Vdd ≤ 3.0
Erase all Blocks and
protection fields at once
–
–
ns
–
20
ms
[21]
T
T
Flash Block Erase + Flash Block Write Time
Flash Block Erase + Flash Block Write Time
–
–
–
–
100
200
ms
ms
0°C <= Tj <= 100°C
-40°C <= Tj <= 0°C
PROGRAM_HOT
PROGRAM_COLD
[21]
2
AC I C Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 36. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Min
0
Max
100
–
Min
0
Max
F
T
400
–
kHz
SCLI2C
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
0.6
μs
HDSTAI2C
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
LOWI2C
HIGHI2C
SUSTAI2C
Set-up Time for a Repeated START
Condition
T
T
T
T
Data Hold Time
0
–
–
–
–
0
–
–
–
–
μs
ns
μs
μs
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
[22]
Data Set-up Time
250
4.0
4.7
100
Set-up Time for STOP Condition
0.6
1.3
Bus Free Time Between a STOP and
START Condition
T
Pulse Width of spikes are suppressed by the
input filter.
–
–
0
50
ns
SPI2C
Notes
21. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
22. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12025 Rev. *R
Page 34 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Table 37. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Min
Max
100
–
Min
–
Max
–
F
T
0
kHz
SCLI2C
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
–
–
μs
HDSTAI2C
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
–
–
–
–
–
–
–
–
–
μs
μs
μs
LOWI2C
HIGHI2C
SUSTAI2C
Set up Time for a Repeated START
Condition
T
T
T
T
Data Hold Time
0
–
–
–
–
–
–
–
–
–
–
–
–
μs
ns
μs
μs
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
Data Set-up Time
250
4.0
4.7
Set up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
T
Pulse Width of spikes are suppressed by the
input filter.
–
–
–
–
ns
SPI2C
Figure 19. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Document Number: 38-12025 Rev. *R
Page 35 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Packaging Information
This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the drawings located at http://www.cypress.com/design/MR10161.
Figure 20. 16-Pin (150-Mil) SOIC
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
0.016[0.406]
X 45°
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068 *B
Figure 21. 20-Pin (210-Mil) SSOP
51-85077 *C
Document Number: 38-12025 Rev. *R
Page 36 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Figure 22. 28-Pin (210-Mil) SSOP
51-85079 *C
Figure 23. 32-Pin (5x5 mm 0.60 MAX) QFN
E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)
001-06392 *A
Document Number: 38-12025 Rev. *R
Page 37 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Figure 24. 32-Pin (5x5 mm) QFN
51-85188 *C
Figure 25. 32-Pin (5 X 5 X 0.4MM) QFN (SAWN 1.85 X 2.85) EPAD
001-44368 *A
Document Number: 38-12025 Rev. *R
Page 38 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Figure 26. 32-Pin Thin Sawn QFN Package
001-48913 *A
Figure 0-1. 32-Pin Sawn QFN Package
001-30999 *B
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Document Number: 38-12025 Rev. *R
Page 39 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Figure 27. 56-Pin (300-Mil) SSOP
51-85062 *C
Thermal Impedances
Table 38. Thermal Impedances per Package
[23]
Package
Typical θJA
Typical θ
JC
o
o
16 SOIC
20 SSOP
28 SSOP
123 C/W
55 C/W
o
o
117 C/W
41 C/W
o
o
96 C/W
39 C/W
[24]
o
o
32 QFN
32 QFN
5x5 mm 0.60 MAX
5x5 mm 0.93 MAX
27 C/W
15 C/W
[24]
o
o
22 C/W
12 C/W
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 39. Solder Reflow Peak Temperature
[25]
Package
Minimum Peak Temperature
Maximum Peak Temperature
o
o
16 SOIC
20 SSOP
28 SSOP
32 QFN
240 C
260 C
o
o
240 C
260 C
o
o
240 C
260 C
o
o
240 C
260 C
Notes
23. TJ = TA + Power x θ
JA
24. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane
25. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 38-12025 Rev. *R
Page 40 of 46
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CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Evaluation Tools
Development Tool Selection
All evaluation tools can be purchased from the Cypress Online
Store.
This section presents the development tools available for all
current PSoC device families including the CY8C21x34 family.
CY3210-MiniProg1
Software
The CY3210-MiniProg1 kit allows a user to program PSoC
devices through the MiniProg1 programming unit. The MiniProg
is a small, compact prototyping programmer that connects to the
PC through a provided USB 2.0 cable. The kit includes:
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer
is
available
free
of
charge
at
■ MiniProg Programming Unit
http://www.cypress.com/psocdesigner and includes a free C
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or operates
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
■ Getting Started Guide
■ USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ PSoC Designer Software CD
■ ICE-Cube In-Circuit Emulator
■ USB 2.0 Cable
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features
a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■ Mini-Eval Programming Board
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
■ PSoCEvalUSB Board
■ LCD Module
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
■ MIniProg Programming Unit
■ Mini USB Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
Document Number: 38-12025 Rev. *R
Page 41 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
CY3207ISSP In-System Serial Programmer (ISSP)
Device Programmers
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
Note CY3207ISSP needs special software and is not compatible
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
with PSoC Programmer. The kit includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ Modular Programmer Base
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ 3 Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
Accessories (Emulation and Programming)
Table 40. Emulation and Programming Accessories
[26]
[27]
Part #
Pin Package
16 SOIC
Flex-Pod Kit
CY3250-21X34
Foot Kit
Adapter
CY8C21234-24S
CY3250-16SOIC-FK
CY3250-20SSOP-FK
CY3250-32QFN-FK
CY3250-28SSOP-FK
CY3250-32QFN-FK
Adapters can be found at
http://www.emulation.com.
CY8C21334-24PVXI
CY8C21434-24LFXI
CY8C21534-24PVXI
CY8C21634-24LFXI
20 SSOP
32 QFN
28 SSOP
32 QFN
CY3250-21X34
CY3250-21X34QFN
CY3250-21X34
CY3250-21X34QFN
Third-Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and production. Specific details for each of these tools
can be found at http://www.cypress.com under Design
Resources> Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note AN2323 “Debugging - Build a PSoC
Emulator into Your Board”.
Notes
26. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
27. Foot kit includes surface mount feet that can be soldered to the target PCB.
Document Number: 38-12025 Rev. *R
Page 42 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Ordering Information
[28]
16 Pin (150-Mil) SOIC
CY8C21234-24SXI
CY8C21234-24SXIT
8K
8K
512 Yes -40°C to +85°C
512 Yes -40°C to +85°C
4
4
4
4
12
12
12
12
0
0
No
No
[28]
16 Pin (150-Mil) SOIC
(Tape and Reel)
[28]
[28]
20 Pin (210-Mil) SSOP
CY8C21334-24PVXI
CY8C21334-24PVXIT
8K
8K
512 No
512 No
-40°C to +85°C
-40°C to +85°C
4
4
4
4
16
16
16
16
0
0
Yes
Yes
20 Pin (210-Mil) SSOP
(Tape and Reel)
[28]
[28]
28 Pin (210-Mil) SSOP
CY8C21534-24PVXI
CY8C21534-24PVXIT
8K
8K
512 No
512 No
-40°Cto +85°C
-40°C to +85°C
4
4
4
4
24
24
24
24
0
0
Yes
Yes
28 Pin (210-Mil) SSOP
(Tape and Reel)
[28]
[28]
[28]
[28]
[28]
[28]
[28]
[28]
32 Pin (5x5 mm 0.93 MAX)
CY8C21434-24LFXI
8K
8K
8K
8K
8K
8K
8K
8K
512 No
512 No
512 No
512 No
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
28
28
28
28
26
26
28
28
28
28
28
28
26
26
28
28
0
0
0
0
0
0
0
0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
[28]
QFN
32Pin(5x5mm0.93MAX)QFN CY8C21434-24LFXIT
b (Tape and Reel)
32Pin(5x5mm0.60MAX)QFN CY8C21434-24LKXI
[29]
32Pin(5x5mm0.60MAX)QFN CY8C21434-24LKXIT
[29]
(Tape and Reel)
32Pin(5x5mm0.93MAX)QFN CY8C21634-24LFXI
512 Yes -40°C to +85°C
512 Yes -40°C to +85°C
[29]
32Pin(5x5mm0.93MAX)QFN CY8C21634-24LFXIT
[29]
(Tape and Reel)
32 Pin (5x5 mm 1.00 MAX)
SAWN QFN
CY8C21434-24LTXI
CY8C21434-24LTXIT
512 No
512 No
-40°C to +85°C
-40°C to +85°C
32 Pin (5x5 mm 1.00 MAX)
[29]
SAWN QFN
Reel)
(Tape and
a
a
32 Pin (5x5 mm 0.40 MAX)
CY8C21434-24LCXI
CY8C21434-24LCXIT
8K
8K
512 No
512 No
-40°C to +85°C
-40°C to +85°C
4
4
4
4
28
28
28
0
0
Yes
Yes
[29]
SAWN QFN
32 Pin (5x5 mm 0.40 MAX)
28
[29]
SAWN QFN
(Tape and Reel)
[28]
[28]
32 Pin (5x5 mm 0.60 MAX)
THIN SAWN QFN
CY8C21434-24LQXI
CY8C21434-24LQXIT
8K
8K
512 No
512 No
-40°C to +85°C
-40°C to +85°C
4
4
4
4
28
28
28
0
0
Yes
Yes
32 Pin (5x5 mm 0.60 MAX)
THIN SAWN QFN
(Tape and Reel)
28
[28]
[28]
32 Pin (5x5 mm 0.93 MAX)
CY8C21634-24LTXI
CY8C21634-24LTXIT
8K
8K
512 Yes -40°C to +85°C
512 Yes -40°C to +85°C
4
4
4
4
26
26
26
0
0
Yes
Yes
[29]
SAWN QFN
32 Pin (5x5 mm 0.93 MAX)
26
[29]
SAWN QFN
(Tape and Reel)
[28]
56 Pin OCD SSOP
CY8C21001-24PVXI
8K
512 Yes -40°C to +85°C
4
4
26
26
0
Yes
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Notes
28. All Digital I/O Pins also connect to the common analog mux.
29. Refer to the section 32-Pin Part Pinout on page 11 for pin differences.
Document Number: 38-12025 Rev. *R
Page 43 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12025 Rev. *R
Page 44 of 46
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CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Document History Page
Document Title: CY8C21234/CY8C21334/CY8C21434/CY8C21534/CY8C21634 PSoC® Programmable System-on-Chip
Document Number: 38-12025
Orig. of
Change
Submission
Date
Revision ECN No.
Description of Change
New silicon and document (Revision **).
**
227340
235992
HMT
See ECN
See ECN
*A
*B
SFV
Updated Overview and Electrical Spec. chapters, along with revisions to the
24-pin pinout part. Revised the register mapping tables. Added a SSOP
28-pin part.
248572
277832
SFV
See ECN
See ECN
Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434
to CY8C21534. Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin.
Added SMP block to architecture diagram. Update Electrical Specifications.
Added another 32-pin MLF part: CY8C21634.
*C
HMT
Verify data sheet standards from SFV memo. Add Analog Input Mux to appli-
cable pin outs. Update PSoC Characteristics table. Update diagrams and
specs. Final.
*D
*E
*F
285293
301739
329104
HMT
HMT
HMT
See ECN
See ECN
See ECN
Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table.
DC Chip-Level Specification changes. Update links to new CY.com Portal.
Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature.
Update Electrical Specifications. Update Reflow Peak Temp. table. Add 32
MLF E-PAD dimensions. Add ThetaJC to Thermal Impedance table. Fix
20-pin package order number. Add CY logo. Update CY copyright.
*G
352736
HMT
See ECN
Add new color and logo. Add URL to preferred dimensions for mounting MLF
packages. Update Transmitter and Receiver AC Digital Block Electrical
Specifications.
*H
*I
390152
413404
430185
HMT
HMT
HMT
See ECN
See ECN
See ECN
Clarify MLF thermal pad connection info. Replace 16-pin 300-MIL SOIC with
correct 150-MIL.
Update 32-pin QFN E-Pad dimensions and rev. *A. Update CY branding and
QFN convention.
*J
Add new 32-pin 5x5 mm 0.60 thickness QFN package and diagram,
CY8C21434-24LKXI. Update thermal resistance data. Add 56-pin SSOP
on-chip debug non-production part, CY8C21001-24PVXI. Update typical and
recommended Storage Temperature per industrial specs. Update copyright
and trademarks.
*K
*L
677717
HMT
See ECN
Add CapSense SNR requirement reference. Add new Dev. Tool section. Add
CY8C20x34 to PSoC Device Characteristics table. Add Low Power
Comparator (LPC) AC/DC electrical spec. tables. Update rev. of32-Lead (5x5
mm 0.60 MAX) QFN package diagram.
2147847 UVS/PYRS
2273246 UVS/AESA
02/27/08
04/01/08
Added 32-Pin QFN Sawn pin diagram, package diagram, and ordering infor-
mation.
*M
*N
Added 32 pin thin sawn package diagram.
2618124 OGNE/PYRS 12/09/08
Added Note in Ordering Information section.
Changed title from PSoC Mixed-Signal Array to PSoC
Programmable System-on-Chip
*O
2684145 SNV/AESA
04/06/2009
Updated 32-Pin Sawn QFN package dimension for CY8C21434-24LTXIT
Updated Getting Started, Development Tools, and Designing with PSoC
Designer Sections
*P
2693024 DPT/PYRS
2720594 BRW
04/16/2009
06/22/09
Updated 32-Pin Sawn QFN package diagram
*Q
Corrected ohm symbol and paranthesis in figure caption (Fig.25)
Removed references to mixed-sginal array from the text
Updated Development Tools Selection section
Document Number: 38-12025 Rev. *R
Page 45 of 46
[+] Feedback
CY8C21634/CY8C21534
CY8C21434/CY8C21334/CY8C21234
Document Title: CY8C21234/CY8C21334/CY8C21434/CY8C21534/CY8C21634 PSoC® Programmable System-on-Chip
Document Number: 38-12025
*R
2762499 JVY
09/11/2009
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified F
Replaced T
cation.
and T
specifications.
IMO6
WRITE
(time) specification with SR
(slew rate) specifi-
RAMP
POWER_UP
Added note [11] to Flash Endurance specification.
Added IOH, IOL, DC , F
, T
, T
, T
, and
ILO 32K_U POWERUP ERASEALL PROGRAM_HOT
T
specifications.
PROGRAM_COLD
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
Clocks & Buffers
Wireless
Memories
Image Sensors
© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12025 Rev. *R
Revised September 10, 2009
Page 46 of 46
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their
respective holders.
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相关型号：
CY8C21434-24LFXIT
MULTIFUNCTION PERIPHERAL, QCC32, 5 X 5 MM, 0.93 MM HEIGHT, LEAD FREE, MO-220, QFN-32
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