CY8C21345_1105 [CYPRESS]
PSoC Programmable System-on-Chip Low power at high speed; 的PSoC可编程系统级芯片的低功耗高速型号: | CY8C21345_1105 |
厂家: | CYPRESS |
描述: | PSoC Programmable System-on-Chip Low power at high speed |
文件: | 总34页 (文件大小:935K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY8C21345
CY8C22345, CY8C22545
®
PSoC Programmable System-on-Chip
■ Programmable pin configurations:
❐ 25 mA sink, 10 mA source on all GPIOs
Features
■ Powerful Harvard-architecture processor:
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Pull-up, pull-down, high Z, Strong, or open-drain drive modes
on all GPIOs
❐ Up to 38 analog inputs on GPIOs
❐ Configurable interrupt on all GPIOs
❐ 3.0 V to 5.25 V operating voltage
❐ Industrial temperature range: -40°C to +85°C
■ Advanced peripherals (PSoC® Blocks)
❐ Six analog type “E” PSoC blocks provide:
• Single or dual 8-Bit ADC
• Comparators (up to four)
❐ Up to eight digital PSoC blocks provide:
• 8 to 32-Bit Timers, counters, and PWMs
■ Additional system resources:
❐ I2C™ slave, master, and multimaster to 400 kHz
❐ Supports hardware addressing feature
❐ Watchdog and sleep timers
❐ User configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-Chip precision voltage reference
❐ Supports RTC block into digital peripheral logic
• One shot, multi shot mode support in timers and PWMs
• PWM with deadband support in one digital block
• Shift register, CRC, and PRS modules
• Full duplex UART
Top Level Block Diagram
Analog
Drivers
Port 4
Port 3
Port 2 Port 1 Port 0
• Multiple SPI masters or slaves, variable data length
Support: 8- to 16-Bit
PSoC Core
• Can be connected to all GPIO pins
❐ Complex peripherals by combining blocks
❐ Shift function support for FSK detection
❐ Powerful synchronize feature support. Analog module
operations can be synchronized by digital blocks or external
signals.
Global Digital Interconnect
Global Analog Interconnect
Flash 16K
SRAM
1K
SROM
Sleep and
Watchdog
CPU Core (M8C)
■ High speed 10-bit SAR ADC with sample and hold optimized for
embedded control
Interrupt
Controller
■ Precision, programmable clocking:
❐ Internal ± 5% 24/48 MHz oscillator across the industrial
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
temperature range
ANALOG SYSTEM
❐ High accuracy 24 MHz with optional 32 kHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal/external oscillator for watchdog and sleep
DIGITAL SYSTEM
Digital Block Array
Analog Input
Muxing(L,R)
Analog
Ref
=
DBC DBC DCC DCC
ROW 1
■ Flexible on-chip memory:
❐ Up to 16 KB flash program storage 50,000 erase/write cycles
❐ Up to 1-KB SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Analog Block Array
CTE CTE CTE CTE
SCE SCE
DBC DBC DCC DCC
ROW 2
CapSense
Digital Resource
10-bit SAR
ADC
■ Optimized CapSense® resource:
❐ Two IDAC support up to 640 µA source current to replace
external resistor
❐ Two dedicated clock resources for CapSense:
• CSD_CLK: 1/2/4/8/16/32/128/256 derive from SYSCLK
• CNT_CLK: 1/2/4/8 Derive from CSD_CLK
POR and LVD
System Resets
Internal
Voltage
Ref.
I2C
Digital
Clocks
MACs
❐ Dedicated 16-bit timers/counters for capsense scanning
❐ Support dual CSD channels simultaneous scanning
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-43084 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 23, 2011
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Contents
PSoC Functional Overview ..............................................3
PSoC Core ..................................................................3
Digital System .............................................................3
Analog System ............................................................4
Additional System Resources .....................................4
PSoC Device Characteristics ......................................5
Getting Started ..................................................................5
Application Notes ........................................................5
Development Kits ........................................................5
Training .......................................................................5
CYPros Consultants ....................................................5
Solutions Library ..........................................................5
Technical Support .......................................................5
Development Tools ..........................................................6
PSoC Designer Software Subsystems ........................6
Designing with PSoC Designer .......................................7
Select User Modules ...................................................7
Configure User Modules ..............................................7
Organize and Connect ................................................7
Generate, Verify, and Debug .......................................7
Pinouts ..............................................................................8
CY8C22345, CY8C21345 28-Pin SOIC ......................8
CY8C22545 44-Pin TQFP ...........................................9
Registers .........................................................................10
Register Conventions ................................................10
Register Mapping Tables ..........................................10
Electrical Specifications ................................................13
Absolute Maximum Ratings .......................................14
Operating Temperature ............................................14
DC Electrical Characteristics .....................................15
AC Electrical Characteristics .....................................19
Packaging Information ...................................................25
Thermal Impedances ................................................26
Solder Reflow Specifications .....................................26
Ordering Information ......................................................26
Ordering Code Definitions ........................................26
Acronyms ........................................................................27
Acronyms Used .........................................................27
Reference Documents ....................................................27
Document Conventions .................................................28
Units of Measure .......................................................28
Numeric Conventions ................................................28
Glossary ..........................................................................28
Document History Page .................................................33
Sales, Solutions, and Legal Information ......................34
Worldwide Sales and Design Support .......................34
Products ....................................................................34
PSoC Solutions .........................................................34
Document Number: 001-43084 Rev. *M
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Digital System
PSoC Functional Overview
The Digital System is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that may be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
The PSoC family consists of many On-Chip Controller devices.
These devices are designed to replace multiple traditional
MCU-based system components with one low cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, and programmable
interconnects. This architecture enables the user to create
customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
Figure 1. Digital System Block Diagram
Port 3
Port 1
Port 4
Port 2
Port 0
To System Bus
Digital Clocks
From Core
To Analog
System
The PSoC architecture, shown in Figure 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. Configurable global busing allows the combining of
all the device resources into a complete custom system. The
PSoC family can have up to five I/O ports connecting to the
global digital and analog interconnects, providing access to eight
digital blocks and six analog blocks.
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
DBC00
DBC01 DCC02 DCC03
4
8
8
PSoC Core
8
8
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
Row 1
DBC01 DCC02 DCC03
DBC00
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with 21 vectors,
to simplify the programming of real time embedded events.
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16 KB of Flash for program storage, 1K
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
Digital peripheral configurations are:
■ PWMs (8 to 32-Bit)
■ PWMs with Dead band (8 to 32-Bit)
■ Counters (8 to 32-Bit)
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator). The 24 MHz
IMO can also be doubled to 48 MHz for use by the digital system.
A low power 32 kHz ILO (internal low speed oscillator) is
provided for the Sleep timer and WDT. If crystal accuracy is
required, the ECO (32.768 kHz external crystal oscillator) is
available for use as a Real Time Clock (RTC), and can optionally
generate a crystal-accurate 24 MHz system clock using a PLL.
The clocks, together with programmable clock dividers (as a
System Resource), provide the flexibility to integrate almost any
timing requirement into the PSoC device.
■ Timers (8 to 32-Bit)
■ UART 8 Bit with Selectable Parity (Up to Two)
■ SPI Master and Slave (Up to Two)
■ Shift Register (1 to 32-Bit)
■ I2C Slave and Master (One Available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32-Bit)
■ IrDA (Up to Two)
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
■ Pseudo Random Sequence Generators (8 to 32-Bit)
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides a choice of
system resources for your application. Family resources are
shown in Table 1 on page 5.
Document Number: 001-43084 Rev. *M
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Analog System
Additional System Resources
The Analog System consists of a 10-bit SAR ADC and six
configurable blocks.
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a MAC, low voltage
detection, and power on reset. The merits of each system
resource are:
The programmable 10-bit SAR ADC is an optimized ADC that
can be run up to 200 ksps with ± 1.5 LSB DNL and ± 2.5 LSB INL
(true for VDD ≥ 3.0 V and Vref ≥ 3.0 V). External filters are
required on ADC input channels for antialiasing. This ensures
that any out-of-band content is not folded into the input signal
band.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Reconfigurable analog resources allow creating complex analog
signal flows. Analog peripherals are very flexible and may be
customized to support specific application requirements. Some
of the more common PSoC analog functions (most available as
user modules) are:
■ Additional Digital resources and clocks optimized for CSD.
■ Support “RTC” block into digital peripheral logic.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■ Analog-to-Digital converters (Single or Dual, with 8-bit
resolution)
■ Pin-to-pin Comparator
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
■ Single ended comparators with absolute (1.3 V) reference or
5-bit DAC reference
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ 1.3 V reference (as a System Resource)
Analog blocks are provided in columns of four, which include
CT-E (Continuous Time) and SC-E (Switched Capacitor) blocks.
These devices provide limited functionality Type “E” analog
blocks.
■ An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
Figure 2. Analog System Block Diagram
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI1[1:0]
ACI1[1:0]
ACE00
ASE10
ACE01
ASE11
ACE10
ACE11
Block Array
AmuxL
AmuxR
P0[0:7]
ACI2[3:0]
10 bit SAR ADC
Analog Reference
Interface to
Reference
Digital System
Generators
AGND
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-43084 Rev. *M
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3
analog blocks. The following table lists the resources available for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Analog
Analog
SRAM
Size
Flash
Size
Outputs Columns Blocks
[1]
CY8C29x66
CY8C28xxx
up to 64
up to 44
4
16
up to 12
up to 44
4
4
12
2 K
1 K
32 K
16 K
up to 3
up to 12
up to 4
up to 6
up to
12 + 4
[2]
CY8C27x43
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
2
1
1
1
2
1
1
1
0
0
8
4
4
4
8
4
4
4
0
0
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
4
2
2
2
0
0
0
0
0
0
4
2
2
2
4
4
2
2
0
0
12
6
256
1 K
16 K
16 K
4 K
[1]
CY8C24x94
[1]
CY8C24x23A
6
256
CY8C23x33
4
256
8 K
[1]
[2]
CY8C22x45
CY8C21x45
CY8C21x34
6
1 K
16 K
8 K
[1]
[1]
[2]
6
512
[2]
4
512
8 K
[2]
CY8C21x23
up to
8
4
256
4 K
[1]
[2,3]
CY8C20x34
CY8C20xx6
up to 28
up to 36
3
512
8 K
[2,3]
3
up to 2 K
up to 32 K
Getting Started
For in-depth information, along with detailed programming
covers a wide variety of topics and skill levels to assist you in
your designs.
details, see the PSoC® Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Solutions Library
Development Kits
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Technical Support
Training
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
Notes
1. Automotive qualified devices available in this group.
2. Limited analog functionality.
®
3. Two analog blocks and one CapSense block.
Document Number: 001-43084 Rev. *M
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Development Tools
PSoC Designer™ is the revolutionary integrated design
Code Generation Tools
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■ Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■ Extensive user module catalog
■ Integrated source-code editor (C and assembly)
■ Free C compiler with no size restrictions or time limits
■ Built-in debugger
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
■ In-circuit emulation
■ Built-in support for communication interfaces:
❐ Hardware and software I2C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/trans-
mitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are ADCs, DACs, amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this allows you to use more than 100 percent of PSoC's
resources for an application.
Document Number: 001-43084 Rev. *M
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
module parameter, and other information you may need to
successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
1. Select User Modules.
Generate, Verify, and Debug
2. Configure User Modules.
3. Organize and Connect.
4. Generate, Verify, and Debug.
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each 8 bits of resolution. The user module parameters permit
you to establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabil-
ities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint, and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events. These include
monitoring address and data bus values, memory locations, and
external signals.
Document Number: 001-43084 Rev. *M
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Pinouts
This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”)
is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
CY8C22345, CY8C21345 28-Pin SOIC
Table 2. Pin Definitions
Type
Figure 3. Pin Diagram
Pin No.
Pin Name
Description
Digital Analog
1
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I, MR
I, ML
I, ML
I, ML
I, ML
ML
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
Integration Capacitor for MR
Integration Capacitor for ML
AI, MR, P0[7]
AI, ML, P0[5]
AI, ML, P0[3]
AI, ML, P0[1]
AI, ML, P2[7]
ADC_Ext_Vref, ML, P2[5]
ML, P2[3]
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
P2[4], MR
3
4
5
To Compare Column 0
SOIC
6
Optional ADC External Vref
ML, P2[1]
P2[2], MR
Vss
P2[0], MR
7
ML
I2C SCL, ML, P1[7]
I2C SDA, ML, P1[5]
ML, P1[3]
XRES
8
ML
P1[6], MR
P1[4], MR, EXTCLK
P1[2], MR
9
Power
Ground Connection
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
I2C SCL, ML, P1[1]
Vss
P1[0], MR, I2C SDATA
10
11
12
13
I/O
I/O
I/O
I/O
ML
ML
ML
ML
P1[7]
P1[5]
P1[3]
P1[1]
I2C Serial Clock (SCL),
ISSP-SCLK[4]
14
15
Power
Vss
Ground Connection
I/O
MR
P1[0]
I2C Serial Clock (SCL),
ISSP-SDATA[4]
16
17
I/O
I/O
MR
MR
P1[2]
P1[4]
Optional External Clock Input
(EXT-CLK)
18
19
I/O
MR
P1[6]
Input
XRES
Active High Pin Reset with
Internal Pull Down
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MR
MR
MR
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I, MR
I, MR
I, MR
I, MR
I, MR
To Compare Column 1
Power
Supply Voltage
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.
Note
4. ISSP pin which is not Hi-Z at POR.
Document Number: 001-43084 Rev. *M
Page 8 of 34
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CY8C21345
CY8C22345, CY8C22545
CY8C22545 44-Pin TQFP
Table 3. Pin Definitions
Type
Figure 4. Pin Diagram
Pin No.
Pin Name
Description
Digital
I/O
Analog
1
2
ML
ML
ML
P2[5]
P2[3]
P2[1]
Vdd
Optional ADC External Vref
I/O
3
I/O
4
Power
Power
Supply Voltage
5
I/O
I/O
I/O
ML
ML
ML
P4[5]
P4[3]
P4[1]
Vss
6
ADC_Ext_Vref, ML, P2[5]
1
2
3
4
5
33
P2[4], MR
P2[2], MR
P2[0], MR
7
ML, P2[3]
ML, P2[1]
Vdd
32
31
8
Ground Connection
30 Vss
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ML
ML
ML
ML
ML
ML
ML
ML
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
ML, P4[5]
P4[4], MR
29
28
27
26
25
10
11
12
13
14
15
16
ML, P4[3]
P4[2], MR
P4[0], MR
6
7
8
9
TQFP
ML, P4[1]
Vss
ML, P3[7]
XRES
P3[6], MR
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
ML, P3[5]
ML, P3[3]
10
11
24 P3[4], MR
23
P3[2], MR
Crystal(XTALin), I2CSerialClock (SCL),
[4]
TC SCLK
17
18
Power
Vss
Ground Connection
I/O
I/O
MR
MR
P1[0]
Crystal (XTALout), I2C Serial Data
]
[4
(SDA), TC SDATA
19
P1[2]
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
MR
MR
MR
MR
MR
MR
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Optional External Clock Input (EXTCLK)
Input
Active High Pin Reset with Internal Pull
Down
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I/O
I/O
MR
MR
MR
P4[0]
P4[2]
P4[4]
Vss
Power
Ground Connection
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MR
MR
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
MR
I, MR
I, MR
I, MR
I, MR
I, MR
To Compare Column 1
Power
Supply Voltage
I/O
I/O
I/O
I/O
I/O
I, MR
I, ML
I, ML
I, ML
I, ML
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
Integration Capacitor for MR
Integration Capacitor for ML
To Compare Column 0
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.
Document Number: 001-43084 Rev. *M
Page 9 of 34
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CY8C21345
CY8C22345, CY8C22545
Registers
This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer the PSoC
Programmable System-on Chip Technical Reference Manual.
Register Conventions
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is also referred to as I/O space and is
broken into two parts. The XIO bit in the Flag register determines
which bank the user is currently in. When the XIO bit is set, the
user is said to be in the “extended” address space or the
“configuration” registers.
Table 4. Abbreviations
Convention
Description
RW
R
Read and write register or bit(s)
Read register or bit(s)
W
L
Write register or bit(s)
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 001-43084 Rev. *M
Page 10 of 34
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CY8C21345
CY8C22345, CY8C22545
Table 5. Register Map Bank 0 Table: User Space
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
PRT0DR
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72*
73*
74
75
76*
77*
78
79
7A
7B
7C
7D
7E
7F
#
ASC10CR0*
80*
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
RW
RW
#
PRT0IE
W
81
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
RW
#
82
83
#
ASD11CR0*
84*
85
W
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
RW
#
86
87
#
88
PWMVREF0
PWMVREF1
IDAC_MODE
PWM_SRC
TS_CR0
W
89
#
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
RW
#
8A
8B
8C
8D
8E
8F
90
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
W
TS_CMPH
TS_CMPL
TS_CR1
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
RW
#
CSD0_DR0_L
CSD0_DR1_L
CSD0_CNT_L
CSD0_CR0
CSD0_DR0_H
CSD0_DR1_H
CSD0_CNT_H
CSD0_CR1
CSD1_DR0_L
CSD1_DR1_L
CSD1_CNT_L
CSD1_CR0
CSD1_DR0_H
CSD1_DR1_H
CSD1_CNT_H
CSD_CR1
R
CUR PP
W
91
STK_PP
PRT4GS
PRT4DM2
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
R
92
PRV PP
#
93
IDX_PP
R
94
MVR_PP
W
95
MVW_PP
I2C0_CFG
I2C0_SCR
I2C0_DR
I2C0_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
R
96
RW
R
97
98
RW
#
W
99
R
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
#
R
W
R
RW
RW
RW
RW
RW
#
DBC00DR0
DBC00DR1
DBC00DR2
DBC00CR0
DBC01DR0
DBC01DR1
DBC01DR2
DBC01CR0
DCC02DR0
DCC02DR1
DCC02DR2
DCC02CR0
DCC03DR0
DCC03DR1
DCC03DR2
DCC03CR0
DBC10DR0
DBC10DR1
DBC10DR2
DBC10CR0
DBC11DR0
DBC11DR1
DBC11DR2
DBC11CR0
DCC12DR0
DCC12DR1
DCC12DR2
DCC12CR0
DCC13DR0
DCC13DR1
DCC13DR2
DCC13CR0
AMX_IN
W
AMUX_CFG
PWM_CR
RW
#
ARF_CR
RES_WDT
DEC_DH
#
CMP_CR0
RW
RW
RW
RW
W
W
ASY_CR
#
DEC_DL
RW
#
CMP_CR1
RW
RW
#
DEC _CR0*
DEC_CR1*
MUL0_X
#
ADC0_CR
ADC1_CR
SADC_DH
SADC_DL
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
W
W
#
W
MUL0_Y
W
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU A
R
R
R
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
W
RW
#
#
RDI0RI
W
RDI0SYN
RDI0IS
CPU_T1
#
RW
#
ACB00CR1*
ACB00CR2*
CPU_T2
#
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RDI0DSM
RDI1RI
CPU_X
#
#
CPU PCL
CPU_PCH
CPU_SP
#
W
#
RW
#
ACB01CR1*
ACB01CR2*
#
CPU_F
I
#
CPU_TST0
CPU_TST1
CPU_TST2
CPU TST3
DAC1_D
RW
RW
RW
#
W
RDI1SYN
RDI1IS
RW
#
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
RDI1DSM
#
RW
RW
#
W
DAC0_D
RW
#
CPU_SCR1
CPU_SCR0
#
Shaded fields are Reserved and must not be accessed.
# Access is bit specific. * has a different meaning.
Document Number: 001-43084 Rev. *M
Page 11 of 34
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CY8C21345
CY8C22345, CY8C22545
Table 6. Register Map Bank 1 Table: Configuration Space
Name
Addr (1,Hex) Access Name
Addr (1,Hex) Access Name
Addr (1,Hex) Access Name
Addr (1,Hex) Access
PRT0DM0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
RW
RW
RW
ASC10CR0*
80*
81
82
83
84*
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
RW
RW
RW
RW
RW
RW
RW
RW
#
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
1
2
3
4
RW
RW
RW
ASD11CR0*
5
6
7
8
RW
RW
RW
9
RW
RW
RW
#
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
CMP0CR1
CMP0CR2
RW
RW
RW
RW
RW
RW
RW
RW
#
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
VDAC50CR0
CMP1CR1
CMP1CR2
VDAC51CR0
CSCMPCR0
CSCMPGOEN
CSLUTCR0
CMPCOLMUX
CMPPWMCR
CMPFLTCR
CMPCLK1
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
DAC_CR1#
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CMPCLK0
DBC00FN
DBC00IN
CLK_CR0
GDI_O_IN_CR A0
GDI_E_IN_CR A1
CLK_CR1
DBC00OU
DBC00CR1
DBC01FN
DBC01IN
ABF_CR0
GDI_O_OU_CR A2
GDI_E_OU_CR A3
AMD_CR0
CMP_GO_EN
RTC_H
A4
A5
A6
A7
A8
A9
AA
VLT_CMP
ADC0_TR*
ADC1_TR*
V2BG_TR
IMO_TR
CMP_GO_EN1 65
RTC_M
RW
RW
RW
W
DBC01OU
DBC01CR1
DCC02FN
DCC02IN
DCC02OU
DBC02CR1
AMD_CR1
ALT_CR0
ALT_CR1
CLK_CR2
66
67
68
69
6A
6B
RTC_S
RTC_CR
SADC_CR0
SADC_CR1
SADC_CR2
ILO_TR
W
BDG_TR
RW
W
CLK_CR3
SADC_CR3TRI AB
M
ECO_TR
DCC03FN
DCC03IN
DCC03OU
DBC03CR1
DBC10FN
DBC10IN
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
6C
6D
6E
6F
70
71
72
73
74
75
76*
77*
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SADC_CR4
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
MUX_CR4
MUX_CR5
MUX_CR6
MUX_CR7
CPU A
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
#
I2C0_AD
RDI0RI
RDI0SYN
RDI0IS
CPU_T1
CPU_T2
CPU_X
#
DBC10OU
DBC10CR1
DBC11FN
DBC11IN
ACB00CR1*
ACB00CR2*
#
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RDI0DSM
RDI1RI
#
CPU_PCL
CPU_PCH
CPU_SP
CPU_F
#
#
DBC11OU
DBC11CR1
DCC12FN
DCC12IN
DCC12OU
DBC12CR1
DCC13FN
DCC13IN
DCC13OU
DBC13CR1
ACB01CR1*
ACB01CR2*
#
I
FLS_PR0
FLS TR
RW
W
RW
RDI1SYN
RDI1IS
FLS_PR1
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
RDI1DSM
FAC_CR0
SW
RW
#
DAC_CR0#
CPU_SCR1
CPU_SCR0
#
Shaded fields are Reserved and must not be accessed.
# Access is bit specific. * has a different meaning.
Document Number: 001-43084 Rev. *M
Page 12 of 34
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CY8C21345
CY8C22345, CY8C22545
Electrical Specifications
This section presents the DC and AC electrical specifications of this PSoC device family. For the latest electrical specifications, check
the most recent data sheet by visiting http://www.cypress.com.
Specifications are valid for -40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted. Specifications for devices running at greater than
A
J
12 MHz are valid for -40°C ≤ T ≤ 70°C and T ≤ 82°C.
A
J
Figure 5. Voltage versus Operating Frequency
5.25
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
Document Number: 001-43084 Rev. *M
Page 13 of 34
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CY8C21345
CY8C22345, CY8C22545
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
Min
Typ
Max
Units
Notes
-55
–
+100
°C
Higher storage tempera-
tures reduce data
retention time
TBAKETEMP Bake Temperature
-
125
-
See Package
label
oC
TBAKETIME
Bake Time
See package
label
72
Hours
TA
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
-0.5
–
–
–
–
–
–
+85
+6.0
°C
V
Vdd
VIO
Vss - 0.5
Vss - 0.5
-25
Vdd + 0.5
Vdd + 0.5
+50
V
VIOz
IMIO
ESD
DC Voltage Applied to Tristate
Maximum Current into any Port Pin
Electro Static Discharge Voltage
V
mA
V
2000
–
Human Body Model
ESD
LU
Latch up Current
–
–
200
mA
Operating Temperature
Table 8. Operating Temperature
Symbol
TA
TJ
Description
Min
-40
-40
Typ
–
Max
+85
Units
°C
Notes
Ambient Temperature
Junction Temperature
–
+100
°C
The temperature rise
from ambient to junction
is package specific. See
Table29onpage26. The
user must limit the power
consumption to comply
with this requirement.
Document Number: 001-43084 Rev. *M
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DC Electrical Characteristics
DC Chip Level Specifications
Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and -40°C
≤ TA ≤ 85°C, or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C, and are for
design guidance only, unless specified otherwise.
Table 9. DC Chip Level Specifications
Symbol
Vdd
Description
Min
3.0
–
Typ
–
Max
5.25
12
Units
Notes
Supply Voltage
Supply Current
V
See Table 16 on page 17
IDD
7
mA Conditions are Vdd = 5.0 V,
25°C, CPU = 3 MHz, 48 MHz disabled.
VC1 = 1.5 MHz
VC2 = 93.75 kHz
VC3 = 93.75 kHz
IDD3
Supply Current
–
4
7
mA Conditions are Vdd = 3.3 V
TA = 25°C, CPU = 3 MHz
48 MHz = Disabled
VC1 = 1.5 MHz, VC2 = 93.75 kHz
VC3 = 93.75 kHz
ISB
Sleep (Mode) Current with POR, LVD,
Sleep Timer, and WDT[5]
–
3
4
6.5
25
μA Conditions are with internal slow speed
oscillator, Vdd = 3.3 V
-40°C <= TA <= 55°C
ISBH
Sleep (Mode) Current with POR, LVD,
Sleep Timer, and WDT at high
temperature[5]
–
–
μA Conditions are with internal slow speed
oscillator, Vdd = 3.3 V
55°C < TA <= 85°C
ISBXTL
ISBXTLH
VREF
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and external crystal[5]
4
7.5
μA Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal.
Vdd = 3.3 V, -40°C <= TA <= 55°C
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and external crystal at
high temperature [5]
–
5
26
μA Conditions are with properly loaded,
1μW max, 32.768 kHz crystal.
Vdd = 3.3 V, 55°C < TA <= 85°C
Reference Voltage (Bandgap)
1.275
1.3
1.325
V
Trimmed for appropriate Vdd
DC GPIO Specifications
Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C, or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are
for design guidance only, unless otherwise specified.
Table 10. DC GPIO Specifications
Symbol
RPU
Description
Pull up Resistor
Min
Typ
5.6
5.6
–
Max
Units
kΩ
Notes
4
4
8
8
–
RPD
VOH
Pull down Resistor
High Output Level
kΩ
Vdd - 1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25 V
(80 mA maximum combined IOH
budget)
VOL
Low Output Level
–
–
–
0.75
–
V
IOL = 25 mA, Vdd = 4.75 to 5.25 V
(100 mA maximum combined IOL
budget)
IOH
High Level Source Current
10
mA VOH = Vdd-1.0 V, see the limitations of
the total current in the note for VOH.
Note
5. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 001-43084 Rev. *M
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Table 10. DC GPIO Specifications (continued)
Symbol Description
IOL Low Level Sink Current
Min
Typ
Max
Units
Notes
25
–
–
mA VOL = 0.75 V, see the limitations of the
total current in the note for VOL.
VIL
VIH
VH
IIL
Input Low Level
–
2.1
–
–
–
0.8
V
V
Vdd = 3.0 to 5.25
Vdd = 3.0 to 5.25
Input High Level
Input Hysterisis
60
1
–
–
mV
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
nA Gross tested to 1 μA
CIN
–
3.5
10
pF Package and pin dependent.
Temp = 25°C
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF Package and pin dependent.
Temp = 25°C
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and -40°C ≤ TA ≤ 85°C, 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and
are for design guidance only.
Table 11. 5 V DC Operational Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
mV
Notes
VOSOA
Input Offset Voltage (absolute value)
TCVOSOA Average Input Offset Voltage Drift
–
μV/°C
[6]
IEBOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
200
4.5
–
pA Gross tested to 1 μA
CINOA
–
9.5
pF Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0.0
–
Vdd - 1
V
Table 12. 3.3 V DC Operational Amplifier Specifications
Symbol
Description
Min
–
Typ
2.5
10
Max
15
–
Units
Notes
VOSOA
Input Offset Voltage (absolute value)
mV
TCVOSOA Average Input Offset Voltage Drift
–
μV/°C
[6]
IEBOA
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
–
200
4.5
–
pA Gross tested to 1 μA
CINOA
–
9.5
pF Package and pin dependent.
Temp = 25°C
VCMOA
Common Mode Voltage Range
0
–
Vdd – 1
V
DC Low Power Comparator Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C, 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5 V at 25°C and are for design
guidance only.
Table 13. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VREFLPC
Low power comparator (LPC) reference
voltage range
0.2
–
Vdd - 1
V
VOSLPC
LPC voltage offset
–
2.5
30
mV
Note
6. Atypical behavior: I
of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.
EBOA
Document Number: 001-43084 Rev. *M
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SAR10 ADC DC Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C, or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and are
for design guidance only.
Table 14. SAR10 ADC DC Specifications
Symbol
Vadcvref
Description
Min
Typ
Max Units
5.25
Notes
Reference voltage at pin P2[5] when configured
as ADC reference voltage
3.0
–
V
When VREF is buffered inside
ADC, the voltage level at P2[5]
(when configured as ADC
reference voltage) must be
always maintained to be at least
300mVlessthanthechipsupply
voltage level on Vdd pin.
(Vadcvref < Vdd)
Iadcvref
Current when P2[5] is configured as ADC VREF
-
–
0.5
mA Disables the internal voltage
reference buffer
INL at 10 bits Integral Nonlinearity
DNL at 10 bits Differential Nonlinearity
-2.5
-5.0
-1.5
-4.0
–
–
–
–
–
–
2.5
5.0
1.5
4.0
150
LSB For VDD ≥ 3.0 V and Vref ≥ 3.0 V
LSB For VDD < 3.0 V or Vref < 3.0 V
LSB For VDD≥ 3.0 V and Vref ≥ 3.0 V
LSB For VDD < 3.0 V or Vref < 3.0 V
ksps Resolution 10 bits
SPS
Sample per second
DC Analog Mux Bus Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and are for
design guidance only.
Table 15. DC Analog Mux Bus Specifications
Symbol
RSW
Rgnd
Description
Min
–
Typ
–
Max Units
Notes
Switch Resistance to Common Analog Bus
Resistance of Initialization Switch to gnd
400
800
Ω
Ω
Vdd ≥ 3.00
–
–
DC POR and LVD Specifications
Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and are for
design guidance only.
Table 16. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Min
Typ
Max Units
Notes
Vdd must be greater than or
equal to 3.0 V during startup,
reset from the XRES pin, or
reset from Watchdog.
VPPOR1
VPPOR2
–
2.82
4.55
2.95
4.70
V
V
Vdd Value for LVD Trip
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.95
3.06
4.37
4.50
4.62
4.71
3.02
3.13
4.48
4.64
4.73
4.81
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
Document Number: 001-43084 Rev. *M
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DC Programming Specifications
Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and are for
design guidance only.
Table 17. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
V
V
V
V
for programming and erase
4.5
5.0
5.5
V
This specification applies to the
functional requirements of
external programmer tools
DDP
DD
Low V for verify
3.0
5.1
3.0
3.1
5.2
–
3.2
5.3
V
V
V
This specification applies to the
functional requirements of
external programmer tools
DDLV
DD
High V for verify
This specification applies to the
functional requirements of
external programmer tools
DDHV
DD
Supply voltage for flash write operation
5.25
This specification applies to this
device when it is executing
internal flash writes
DDIWRITE
IDDP
VILP
Supply Current during Programming or Verify
–
–
5
–
25
mA
V
Input Low Voltage during Programming or
Verify
0.8
VIHP
IILP
Input High Voltage during Programming or
Verify
2.2
–
–
–
–
–
–
0.2
V
Input Current when Applying Vilp to P1[0] or
P1[1] during Programming or Verify
–
mA Driving internal pull down
resistor
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] during Programming or Verify
–
–
1.5
mA Driving internal pull down
resistor
VOLV
VOHV
Output Low Voltage during Programming or
Verify
Vss + 0.75
Vdd
V
Output High Voltage during Programming or
Verify
Vdd - 1.0
V
FlashENPB Flash Endurance (per block)[8]
FlashENT Flash Endurance (total)[7]
50,000
1,800,000
10
–
–
–
–
–
–
–
–
Erase/write cycles per block
Erase/write cycles
FlashDR
Flash Data Retention
Years
DC I2C Specifications
Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and are for
design guidance only.
Table 18. DC I2C Specifications
Parameter
Description
Min
Typ
–
Max
Units
Notes
[9]
V
Input low level
Input high level
–
–
0.3 × V
V
V
V
3.0 V ≤ V ≤ 3.6 V
ILI2C
DD
DD
–
0.25 × V
–
4.75 V ≤ V ≤ 5.25 V
DD
DD
[9]
V
0.7 × V
–
3.0 V ≤ V ≤ 5.25 V
IHI2C
DD
DD
Note
7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
8. The 50,000 cycle Flash endurance per block is guaranteed only if the Flash operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V
2
9. All GPIOs meet the DC GPIO V and V specifications found in the DC GPIO specifications sections.The I C GPIO pins also meet the above specs.
IL
IH
Document Number: 001-43084 Rev. *M
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AC Electrical Characteristics
AC Chip Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and -40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and
are for design guidance only.
Table 19. 5 V and 3.3 V AC Chip-Level Specifications
Symbol
Description
Min Min(%) Typ
Max
Max(%) Units
Notes
[10,11
,12]
F
Internal Main Oscillator Frequency for 24 MHz 22.8
–
24
–
MHz Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 5 on
page 13. SLIMO mode = 0 <
85
25.2
IMO24
[10,11,
12]
F
Internal Main Oscillator Frequency for 6 MHz
5.5
6
MHz Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 5 on
page 13.
8
6.5
8
IMO6
SLIMO mode = 0 < 85.
[10,11
]
F
F
F
F
CPU Frequency (5 V Nominal)
CPU Frequency (3.3 V Nominal)
0.089
0.089
0
–
–
–
–
24
12
48
24
–
–
–
–
MHz 24 MHz only for
SLIMO mode = 0.
24.6
CPU1
CPU2
BLK5
[11,12
]
MHz SLIMO mode = 0.
12.3
49.2
24.6
0
[10,11
,13]
Digital PSoC Block Frequency (5 V Nominal)
MHz Refer to Table 23 on page
21.
[11,13
]
Digital PSoC Block Frequency (3.3 V Nominal)
0
MHz
BLK33
F
F
Internal Low Speed Oscillator Frequency
15
5
–
–
32
–
85
100
–
–
kHz
32K1
Untrimmed Internal Low Speed Oscillator
Frequency
kHz The ILO is not adjusted with
the factory trim values until
after the CPU starts running.
See the “System Resets”
section in the Technical
32KU
Reference Manual.
T
External Reset Pulse Width
10
–
–
–
–
µs
XRST
DC24M
24 MHz Duty Cycle
40
20
–
–
–
50
50
60
80
–
–
–
%
%
DC
Internal Low Speed Oscillator Duty Cycle
48 MHz Output Frequency
ILO
F
46.8
48.0
49.2
MHz Trimmed. Utlizing factory
trim values.
OUT48M
F
Maximum frequency of signal on row input or
row output
–
–
–
–
–
–
–
–
–
12.3
250
100
–
–
–
MHz
MAX
SR
Power supply slew rate
V/ms Vdd slew rate during power
up.
POWERUP
T
Time from end of POR to CPU executing code
24 MHz IMO cycle-to-cycle jitter (RMS)
ms
ps
POWERUP
[14]
tjit_IMO
–
–
–
–
200
300
700
900
–
–
ps
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
N = 32
ps
ps
24 MHz IMO period jitter (RMS)
–
–
–
–
–
–
100
200
300
400
800
–
–
–
[14]
tjit_PLL
24 MHz IMO cycle-to-cycle jitter (RMS)
ps
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
1200
N = 32
ps
24 MHz IMO period jitter (RMS)
–
–
100
700
–
Notes
10. Valid only for 4.75 V < Vdd < 5.25 V.
11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
12. 3.0 V < Vdd < 3.6 V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3 V.
13. Refer to the individual user module data sheets for information on maximum frequencies for user modules.
14. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-43084 Rev. *M
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AC GPIO Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and are for
design guidance only.
Table 20. 5 V and 3.3 V AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
12
18
18
–
Units
Notes
GPIO Operating Frequency
MHz Normal Strong Mode
TRiseF
TFallF
TRiseS
TFallS
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25 V, 10% - 90%
2
–
Vdd = 4.5 to 5.25 V, 10% - 90%
Vdd = 3 to 5.25 V, 10% - 90%
Vdd = 3 to 5.25 V, 10% - 90%
7
27
22
7
–
Figure 6. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and are for
design guidance only.
Table 21. AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TCOMP
Comparator Mode Response Time, 50 mV
100
ns
Vdd ≥ 3.0 V
AC Low Power Comparator Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V at 25°C and are for design
guidance only.
Table 22. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
Typ
Max
Units
Notes
–
–
50
μs
≥ 50 mV overdrive comparator
reference set within VREFLPC
Document Number: 001-43084 Rev. *M
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AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and -40°C ≤ TA ≤ 85°C or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V, at 25°C and
are for design guidance only.
Table 23. AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
Notes
All functions Block Input Clock Frequency
Vdd ≥ 4.75 V
–
–
–
–
50.4[16] MHz
25.2[16] MHz
Vdd < 4.75 V
Timer
Input Clock Frequency
No Capture, Vdd ≥ 4.75 V
No Capture, Vdd < 4.75 V
With Capture
–
–
–
–
–
–
50.4[16] MHz
25.2[16] MHz
25.2[16] MHz
–
Capture Pulse Width
Input Clock Frequency
No Enable Input, Vdd ≥ 4.75 V
No Enable Input, Vdd < 4.75 V
With Enable Input
50[15]
–
ns
Counter
Dead Band
–
–
–
–
–
–
50.4[16] MHz
25.2[16] MHz
25.2[16] MHz
–
Enable Input Pulse Width
Kill Pulse Width
50[15]
–
ns
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
20
–
–
–
–
–
–
ns
ns
ns
50[15]
50[15]
Input Clock Frequency
Vdd ≥ 4.75 V
–
–
–
–
50.4[16] MHz
25.2[16] MHz
Vdd < 4.75 V
CRCPRS
(PRS Mode)
Input Clock Frequency
Vdd ≥ 4.75 V
–
–
–
–
–
–
50.4[16] MHz
25.2[16] MHz
25.2[16] MHz
Vdd < 4.75 V
CRCPRS
Input Clock Frequency
(CRC Mode)
SPIM
Input Clock Frequency
–
–
8.4[16]
MHz The SPI serial clock (SCLK)
frequency is equal to the input
clock frequency divided by 2.
SPIS
Input Clock (SCLK) Frequency
–
–
–
4.2[16]
–
MHz The input clock is the SPI SCLK
in SPIS mode.
Width of SS_Negated Between Transmissions 50[15]
Input Clock Frequency
ns
Transmitter
Receiver
Thebaudrateisequaltotheinput
clock frequency divided by 8.
Vdd ≥ 4.75 V, 2 Stop Bits
Vdd ≥ 4.75 V, 1 Stop Bit
Vdd < 4.75 V
–
–
–
–
–
–
50.4[16] MHz
25.2[16] MHz
25.2[16] MHz
Input Clock Frequency
Vdd ≥ 4.75 V, 2 Stop Bits
Vdd ≥ 4.75 V, 1 Stop Bit
Vdd < 4.75 V
Thebaudrateisequaltotheinput
clock frequency divided by 8.
–
–
–
–
–
–
50.4[16] MHz
25.2[16] MHz
25.2[16] MHz
Notes
15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
16. Accuracy derived from IMO with appropriate trim for V range.
DD
Document Number: 001-43084 Rev. *M
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AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and -40°C ≤ TA ≤ 85°C, or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V or 3.3 V at 25°C and
are for design guidance only.
Table 24. 5 V AC External Clock Specifications
Symbol
Description
Min
0.093
20.6
20.6
150
Typ
–
Max
24.6
5300
–
Units
MHz
ns
Notes
FOSCEXT
Frequency
High Period
Low Period
–
–
–
–
–
ns
Power Up IMO to Switch
–
–
μs
Table 25. 3.3 V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU Clock divide by 1
0.093
–
12.3
MHz Maximum CPU frequency is
12 MHz at 3.3 V. With the CPU
clock divider set to 1, the
external clock must adhere to
the maximum frequency and
duty cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or greater 0.186
–
24.6
MHz If the frequency of the external
clock is greater than 12 MHz,
the CPU clock divider must be
set to 2 or greater. In this case,
the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
41.7
41.7
150
–
–
–
5300
ns
ns
μs
–
–
SAR10 ADC AC Specifications
Table 26 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C, or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are
for design guidance only.
Table 26. SAR10 ADC AC Specifications
Symbol
Freq3
Freq5
Description
Input clock frequency 3 V
Input clock frequency 5 V
Min
–
Typ
–
Max
2.7
Units
MHz
MHz
Notes
–
–
2.7
Document Number: 001-43084 Rev. *M
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CY8C22345, CY8C22545
AC Programming Specifications
Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C, or 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V, or 3.3 V at 25°C and are
for design guidance only.
Table 27. AC Programming Specifications
Symbol
TRSCLK
Description
Rise Time of SCLK
Min
1
Typ
–
Max
20
20
–
Units
Notes
ns
TFSCLK
TSSCLK
THSCLK
FSCLK
Fall Time of SCLK
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
FSCLK3
TERASEB
TWRITE
TDSCLK
TDSCLK3
TERASEALL
Frequency of SCLK3
0
–
6
MHz VDD < 3.6 V
Flash Erase Time (Block)
–
10
40
–
–
ms
ms
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
–
55
65
–
ns 3.6 < Vdd; at 30 pF Load
–
–
ns 3.0 ≤ Vdd ≤ 3.6; at 30 pF Load
–
40
–
ns
ms
ms
TPROGRAM_HOT Flash Block Erase + Flash Block Write Time
TPROGRAM_COLD Flash Block Erase + Flash Block Write Time
–
100
200
–
–
Document Number: 001-43084 Rev. *M
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AC I2C Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
-40°C ≤ TA ≤ 85°C, and 3.0 V to 3.6 V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25°C
and are for design guidance only.
Table 28. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0 V
Standard Mode
Fast Mode
Symbol
FSCLI2C
Description
SCL Clock Frequency
Units
Notes
Min
0
Max
100
–
Min
0
Max
400
–
kHz
THDSTAI2C
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
0.6
μs
TLOWI2C
THIGHI2C
TSUSTAI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
Setup Time for a Repeated START
Condition
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
Data Hold Time
0
–
–
–
–
0
100[17]
0.6
–
–
–
–
μs
ns
μs
μs
Data Setup Time
250
4.0
4.7
Setup Time for STOP Condition
Bus Free Time Between a STOP and
START Condition
1.3
TSPI2C
Pulse Width of spikes are suppressed by
the Input Filter
–
–
0
50
ns
Figure 7. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
TSUSTAI2C
TBUFI2C
THDDATI2C
I2C_SCL
THIGHI2C TLOWI2C
TSUSTOI2C
P
S
S
Sr
Repeated START Condition
STOP Condition
START Condition
Note
17. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement T
≥ 250 ns must then be met. This is automatically the
SUDATI2C
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line t + T = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SUDATI2C
Document Number: 001-43084 Rev. *M
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Packaging Information
Figure 8. 28-Pin SOIC
51-85026 *F
Figure 9. 44-Pin TQFP
51-85064 *E
Document Number: 001-43084 Rev. *M
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Thermal Impedances
Table 29. Thermal Impedances per Package
[19]
Package
28 SOIC
44 TQFP
Typical θJA
68°C/W
61°C/W
Solder Reflow Specifications
Table 30 shows the solder reflow temperature limits that must not be exceeded.
Table 30. Solder Reflow Specifications
Maximum Peak Temperature
Package
Maximum Time above TC – 5 °C
30 seconds
30 seconds
(TC)
28 SOIC
44 TQFP
260 °C
260 °C
Ordering Information
The following table lists the key package features and ordering codes of this PSoC device family.
Table 31. PSoC Device Family Key Features and Ordering Information
Package
Ordering Code
28 SOIC
CY8C21345-24SXI
CY8C21345-24SXIT
CY8C22345-24SXI
CY8C22345-24SXIT
CY8C22545-24AXI
CY8C22545-24AXIT
8
512B
512B
1K
4
4
8
8
8
8
6
6
6
6
6
6
24 24[18]
24 24[18]
24 24[18]
24 24[18]
38 38[18]
38 38[18]
0
0
0
0
0
0
Y
Y
Y
Y
Y
Y
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
28 SOIC (Tape and Reel)
28 SOIC
8
16
16
16
16
28 SOIC (Tape and Reel)
44 TQFP
1K
1K
44 TQFP (Tape and Reel)
1K
Ordering Code Definitions
CY 8 C 2x xxx-SPxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
C = Commercial
I = Industrial
PVX = SSOP Pb-Free E = Extended
LFX/LTX = QFN Pb-Free
AX = TQFP Pb-Free
CPU Speed: 24 MHz
Part Number
Family Code (21, 22)
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Note
18. Ten direct inputs.
Document Number: 001-43084 Rev. *M
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Acronyms
Acronyms Used
Table 32 lists the acronyms that are used in this document.
Table 32. Acronyms Used in this Datasheet
Acronym
AC
Description
alternating current
Acronym
MAC
Description
multiply-accumulate
ADC
API
analog-to-digital converter
application programming interface
complementary metal oxide semiconductor
central processing unit
MCU
MIPS
PCB
microcontroller unit
million instructions per second
printed circuit board
CMOS
CPU
CRC
CSD
CT
PGA
PLL
programmable gain amplifier
phase-locked loop
cyclic redundancy check
capsense sigma delta
POR
PPOR
PRS
PSoC®
PWM
QFN
RTC
power on reset
continuous time
precision power on reset
pseudo-random sequence
Programmable System-on-Chip
pulse width modulator
quad flat no leads
DAC
DC
digital-to-analog converter
direct current
DNL
differential nonlinearity
ECO
EEPROM
external crystal oscillator
electrically erasable programmable read-only
memory
real time clock
FSK
GPIO
I/O
frequency-shift keying
general-purpose I/O
input/output
SAR
successive approximation
switched capacitor
SC
SLIMO
SOIC
SPI™
SRAM
SROM
SSOP
TQFP
UART
USB
slow IMO
ICE
in-circuit emulator
small-outline integrated circuit
serial peripheral interface
static random access memory
supervisory read only memory
shrink small-outline package
thin quad flat pack
IDE
integrated development environment
current DAC
IDAC
ILO
internal low speed oscillator
internal main oscillator
integral nonlinearity
IMO
INL
IrDA
ISSP
LPC
LSB
LVD
infrared data association
in-system serial programming
low power comparator
least-significant bit
universal asynchronous reciever / transmitter
universal serial bus
WDT
watchdog timer
XRES
external reset
low voltage detect
Reference Documents
CY8C22x45 and CY8C21345 PSoC® Programmable System-on-Chip™ Technical Reference Manual (TRM) (001-48461)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Notes
19. T = T + POWER x θ
J
A
JA
Document Number: 001-43084 Rev. *M
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Document Conventions
Units of Measure
Table 33 lists the units of measures.
Table 33. Units of Measure
Symbol
kB
Unit of Measure
Symbol
mV
nA
ns
Unit of Measure
1024 bytes
degree Celsius
kilohertz
millivolts
°C
nanoampere
nanosecond
ohm
kHz
kΩ
kilohm
W
LSB
MHz
µA
least significant bit
megahertz
microampere
microsecond
microvolts
%
percent
pF
picofarad
picosecond
samples per second
pikoampere
volts
ps
µs
sps
pA
V
µV
mA
mm
ms
milliampere
millimeter
µW
W
microwatts
watt
millisecond
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
(ADC)
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
API (Application A series of software routines that comprise an interface between a computer application and
Programming
Interface)
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
Document Number: 001-43084 Rev. *M
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Glossary (continued)
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
block
buffer
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
compiler
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
data bus
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows the user to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
Document Number: 001-43084 Rev. *M
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Glossary (continued)
digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-
(DAC)
to-digital (ADC) converter performs the reverse operation.
duty cycle
emulator
The relationship of a clock period high time to its low time, expressed as a percent.
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides users with the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is off.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency
gain
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows users to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware
routine (ISR)
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltagedetect A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a
(LVD)
selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
Document Number: 001-43084 Rev. *M
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Glossary (continued)
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
modulator
noise
The reference to a circuit containing both analog and digital techniques and components.
A device that imposes a signal on a carrier.
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
parity
A circuit that may be crystal controlled and is used to generate a clock frequency.
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
port
A group of pins, usually eight.
power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is
one type of hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-
Chip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
reset
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
Document Number: 001-43084 Rev. *M
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Glossary (continued)
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
shift register
slave device
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
SROM
An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, after a value has been
loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is
removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
VDD
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
Document Number: 001-43084 Rev. *M
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Document History Page
Document Title: CY8C21345, CY8C22345, CY8C22545 PSoC® Programmable System-on-Chip
Document Number: 001-43084
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2251907 PMP/AESA
2506377 EIJ/AESA
See ECN New Data sheet
*A
See ECN Changed data sheet status to “Preliminary”. Changed part numbers to
CY8C22x45. Updated data sheet template.
Added 56-Pin OCD information. Added: “You must put filters on intended ADC
input channels for anti-aliasing. This ensures that any out-of-band content is not
folded into the Input Signal Band." To Section Analog System on page 4.
Corrected Minimum Electro Static Discharge Voltage in Table 7 on page 14.
*B
2558750 PMP/AESA 08/28/2008 Updated Features on page 1, PSoC Core on page 3, Analog System on page 4.
Changed DBB to DBC, and DCB to DCC in Register Tables Table 5 on page 11
and Table 6 on page 12.
Removed INL at 8 bit reference in Table 14 on page 17.
Changed IDD3 value Table 16 on page 17 Typ:3.3 mA, Max 6 mA
Added “3.0 V < Vdd < 3.6 V and -40C < TA < 85C, IMO can guarantee 5%
accuracy only” to Table 19 on page 19.
Updated data sheet template.
*C
2606793 NUQ/AESA 11/19/2008 Updated data sheet status to “Final”. Updated block diagram on page 1.
Removed CY8C22045 56-Pin OCD information. Added part numbers
CY8C21345, CY8C22345, and CY8C22545. For more details, see CDT 31271.
*D
*E
2615697 PMP/AESA 12/03/2008 Confirmed CY8C22345 and CY8C21345 have same pinout on page 8.
Confirmed that IMO has 5% accuracy in Table 19 on page 19.
2631733 PMP/PYRS 01/07/2009 Updated Table 16. SAR10 ADC DC Specifications and Table 29 AC Programming
Specifications. Title changed to “CY8C21345, CY8C22345, CY8C22545 PSoC®
Programmable System-on-Chip™”
*F
2648800 JHU/AESA 01/28/2009 Updated INL, DNL information in Table 14 on page 17, Development Tools on
page 6, and TDSCLK parameter in Table 27 on page 23.
*G
*H
2658078 HMI/AESA
02/11/2009 Updated section Features on page 1.
2667311 JHU/AESA 03/16/2009 Added parameter “F32KU” and added Min% and Max % to parameter “FIMO6” in
Table 19 on page 19, according to updated SLIMO spec.
*I
2748976 JZHU/PYRS 08/06/2009 Updated F32K1 max rating in Table 19 on page 19.
*J
2786560
JZHU
10/23/2009 Added DCILO, TERASEALL, TPROGRAM_HOT, TPROGRAM_COLD, SRPOWERUP, IOH
,
and IOL parameters.
Added Tape and Reel parts in Ordering Information table
*K
*L
2901653
NJF
03/30/2010 Updated PSoC Designer Software Subsystems.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings
Modified Note 6 on page 17.
Added FOUT48M parameter in 5 V and 3.3 V AC Chip-Level Specifications.
Removed AC Analog Mux Bus Specifications.
Updated Ordering Code Definitions.
Updated links in Sales, Solutions, and Legal Information.
3114978
NJF
12/19/10
Added DC I2C Specifications.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated DC Programming Specifications.
Updated AC Digital Block Specifications.
Updated I2C Timing Diagram.
Added Solder Reflow Peak Temperature table.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Document Number: 001-43084 Rev. *M
Page 33 of 34
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CY8C21345
CY8C22345, CY8C22545
Document Title: CY8C21345, CY8C22345, CY8C22545 PSoC® Programmable System-on-Chip
Document Number: 001-43084
*M 3231771 BOBH/ECU
04/18/11
Updated analog inputs column in Table 31 on page 26 and included reference to
Note 18.
Updated the following sections: Getting Started, Development Tools, and
Designing with PSoC Designer as all the System level designs have been
de-emphasized.
Updated Table 30, “Solder Reflow Specifications,” on page 26.
Updated package diagrams:
51-85026 to *F
51-85064 to *E
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-43084 Rev. *M
Revised May 23, 2011
Page 34 of 34
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
2
2
2
Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided
2
that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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相关型号:
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Multifunction Peripheral, CMOS, 5 X 5 MM, 0.40 MM HEIGHT, LEAD FREE, MO-220, QFN-32
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