CY8C20246-24LKXIT [CYPRESS]
CapSense™ Applications; 的CapSense ™应用
| 型号： | CY8C20246-24LKXIT |
| 厂家： | 
CYPRESS |
| 描述： | CapSense™ Applications |
| 文件： | 总34页 (文件大小：662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C20x46, CY8C20x66
CapSense™ Applications
Features
■ Low Power CapSenseTM Block
■ Programmable Pin Configurations
❐ Configurable Capacitive Sensing Elements
❐ 25 mA Sink Current on All GPIO
❐ TSouupcphopratsdCs,oTmobuicnhaSticorneeonf sC,aapnSdePnrsoexBimuitttyonSse,nSsloidrsers,
❐ Pull Up, High Z, Open Drain Drive Modes on All GPIO
❐ CMOS Drive Mode on Ports 0 and 1
❐ Up to 36 Analog Inputs on GPIO
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running to 24 MHz
❐ Low Power at High Speed
❐ Interrupt Controller
❐ 1.71V to 5.5V Operating Voltage
❐ Temperature Range: – 40°C to +85°C
❐ Configurable Inputs on All GPIO
❐ Selectable, Regulated Digital IO on Port 1
❐ Configurable Input Threshold for Port 1
❐ 3.0V, 20 mA Total Port 1 Source Current
❐ 5 mA Source Current Mode on Ports 0 and 1
❐ Hot-Swap Capability on all Port1 GPIO
■ Flexible On-Chip Memory
❐ Two Program Storage Size Options
• CY8C20x46: 16K Flash
■ Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO Combinations
❐ High PSRR Comparator
• CY8C20x66: 32K Flash
❐ 50,000 Erase/Write Cycles
❐ 2048 Bytes SRAM Data Storage
❐ Partial Flash Updates
❐ Low Dropout Voltage Regulator for the Analog Array
■ Additional System Resources
❐ Flexible Protection Modes
❐ In-System Serial Programming (ISSP)
❐ I2C™ Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation Requires No Clock Stretching
■ Full-Speed USB (12 Maps)
• Implementation During Sleep Modes with
❐ Eight Uni-Directional Endpoints
Less Than 100 µA
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
• Hardware Address Detection
❐ SPI™ Master and SPI Slave
• Configurable Between 46.9 kHz – 12 MHz
❐ Three 16-Bit Timers
❐ Dedicated 512 Byte Buffer
❐ Internal 3.3V Output Regulator
❐ Available on 48-Pin QFN and 48-Pin SSOP packages only
❐ Operating voltage with USB enabled:
• 3.15 to 3.45V when supply voltage is around 3.3V
• 4.35 to 5.25V when supply voltage is around 5.0V
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
■ Package Options
■ Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
❐ 16-Pin 3x3 x 0.6 mm QFN
❐ 24-Pin 4x4 x 0.6 mm QFN
❐ 32-Pin 5x5 x 0.6 mm QFN
❐ 48-Pin 7x7 x 1.0 mm QFN (CY8C20x66 only)
❐ 48-Pin SSOP
■ Precision, Programmable Clocking
❐ Internal ± 5.0% 6/12/24 MHz Main Oscillator
❐ SInlteeerpnal Low Speed Oscillator at 32 kHz for Watchdog and
❐ Optional External 32 kHz Crystal
❐ 0.25% Accuracy for USB with No External Components
Cypress Semiconductor Corporation
Document Number: 001-12696 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 13, 2008
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Block Diagram
1.8/2.5/3V
LDO
PWRSYS
Port 4 Port 3
Port 2
Port 1
Port 0
(Regulator)
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
16K/32K Flash
2K SRAM
Supervisory ROM (SROM)
Nonvolatile Memory
Interrupt
Sleep and
Watchdog
Controller
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Analog
Reference
CapSense
Module
Two
Analog
Mux
Comparators
SYSTEM BUS
Internal
Voltage
POR
SPI
Three 16-Bit
I2C
System
Resets
Digital
Clocks
USB
and
Master/
Slave
Programmable
Timers
Slave
References
LVD
SYSTEM RESOURCES
Document Number: 001-12696 Rev. *C
Page 2 of 34
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CY8C20x46, CY8C20x66
®
Figure 1. Analog System Block Diagram
PSoC Functional Overview
The PSoC family consists of many Mixed-Signal Array with On-
Chip Controller devices. These devices are designed to replace
multiple traditional MCU-based components with one, low cost
single-chip programmable component. A PSoC device includes
configurable analog and digital blocks, as well as programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable IO are
included in a range of convenient pinouts.
The architecture for this device family, as illustrated above, is
comprised of three main areas: the Core, the CapSense Analog
System, and the System Resources (including a full-speed USB
port). A common, versatile bus allows connection between IO
and the analog system. Each CY8C20x46/CY8C20x66 PSoC
device includes a dedicated CapSense block that provides
sensing and scanning control circuitry for capacitive sensing
applications. Depending on the PSoC package, up to 36 general
purpose IO (GPIO) are also included. The GPIO provides access
to the MCU and analog mux.
IDAC
Vr
Reference
Buffer
Cinternal
Comparator
Mux
Mux
Refs
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as config-
urable USB and I2C slave/SPI master-slave communication
interface, three 16-bit programmable timers, and various system
resets supported by the M8C.
CapSenseCounters
CSCLK
CapSense
ClockSelect
IMO
Oscillator
The Analog Multiplexer System
The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
■ tCooumchppleaxdsc.apacitive sensing interfaces, such as sliders and
■ Chip-wide mux that allows analog input from any IO pin.
■ Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the lat-
est signal-to-noise signal level requirements Application Notes,
which can be found under http://www.cypress.com >> Docu-
mentation >> Application Notes. In general, and unless other-
wise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 001-12696 Rev. *C
Page 3 of 34
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Additional System Resources
Getting Started
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. The merits of each system resource are listed here:
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, reference the PSoC Mixed-
Signal Array Technical Reference Manual, which can be found
on http://www.cypress.com/psoc.
■ The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower for a
slower system clock).
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on the
web at http://www.cypress.com.
■ aTlhreeaId2yClohwardpwowareer acdondrseusmsprteiocnogbnyiteiolinmfienaattuinrge trheedunceeesdthfoer
CPU intervention until a packet addressed to the target device
is received.
Development Kits
■ cLaotwioVnoolftafgaellinDgevteoclttaiogne(lLeVvDel)s,inwtehrirleupthtsecaadnvsaingcneadl tPhOe Rappli-
(Power-On-Reset) circuit eliminates the need for a system
supervisor.
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/shop/. Under Product Categories click
PSoC® Mixed Signal Arrays to view a current list of available
items.
■ iAtinveinsteernnsainl rge.ference provides an absolute reference for capac-
■ dTrhoep5ou.5tVremgualxaitmoru(mLDinOp)upt,ro1v.8id/2e.s5r/e3gVu-slaetlieocntafobrleIOosu.tApurte,gloiswte-r-
controlled bypass mode allows the user to disable the LDO.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
■ tShteanCdYa8rdCC20ypx4re6s/Cs YP8SCoC20IxD6E6tfoaomlsilayroefapvaaritlsa.bHleofworedveerb,uthgeging
additional trace length and a minimal ground plane in the Flex-
Pod can create noise problems that make it difficult to debug
a Power PSoC design. A custom bonded On-Chip Debug
(OCD) device is available in an 48-pin QFN package. The OCD
device is recommended for debugging designs that have high
current and/or high analog accuracy requirements. The QFN
package is compact and is connected to the ICE through a high
density connector.
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com, click on Support
located at the top of the web page, and select CYPros
Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a four hour guaranteed
response at http://www.cypress.com/support.
Application Notes
A long list of application notes assists you in every aspect of your
design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Documentation list located at the top of the web page.
Application notes are sorted by date by default.
Document Number: 001-12696 Rev. *C
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Development Tools
PSoC Designer™ is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC Mixed-Signal Controllers that match
your system requirements.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over on-
chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-12696 Rev. *C
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the IO pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog-to-
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Select Components
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces (I2C-
bus, for example), and the logic to control how they interact with
one another (called valuators).
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed-signal
varieties.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Document Number: 001-12696 Rev. *C
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Document Conventions
Acronyms Used
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Units of Measure lists all the abbreviations used to
measure the PSoC devices.
The following table lists the acronyms that are used in this
document.
Table 1. Acronyms
Numeric Naming
Acronym
AC
Description
alternating current
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
API
CPU
DC
application programming interface
central processing unit
direct current
FSR
GPIO
GUI
full scale range
general purpose IO
graphical user interface
in-circuit emulator
ICE
ILO
IMO
IO
internal low speed oscillator
internal main oscillator
input/output
LSb
least-significant bit
LVD
low voltage detect
MSb
POR
PPOR
PSoC®
SLIMO
SRAM
most-significant bit
power on reset
precision power on reset
Programmable System-on-Chip™
slow IMO
static random access memory
Document Number: 001-12696 Rev. *C
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Pin Information
This section describes, lists, and illustrates the CY8C20x46/CY8C20x66 PSoC device pins and pinout configurations.
The CY8C20x46/CY8C20x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES
are not capable of Digital IO.
16-Pin Part Pinout
Table 2. 16-Pin QFN Part Pinout(2)
Type
Digital Analog
Figure 2. CY8C20246, CY8C20266 16-Pin PSoC Device
Pin
No.
Name
Description
1
2
3
4
5
6
7
8
IO
IO
IOHR
IOHR
IOHR
IOHR
I
I
I
I
I
I
P2[5]
P2[3]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
Crystal output (XOut).
Crystal input (XIn).
I2C SCL, SPI SS.
I2C SDA, SPI MISO.
SPI CLK.
ISSP CLK(1), I2C SCL, SPI MOSI.
Ground connection.
ISSP DATA(1), I2C SDA, SPI CLK.
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
1
2
3
4
P0[4], AI
12
11
10
QFN
XRES
(Top View)
P1[4], EXTCLK, AI
P1[2], AI
9
Power
IOHR
IOHR
IOHR
I
I
I
9
10
11
Optional external clock (EXTCLK)
Input
XRES Active high external reset with
internal pull down.
12
13
14
15
IOH
I
P0[4]
Vdd
P0[7]
P0[3]
Power
Supply voltage.
Integrating input.
IOH
IOH
I
I
16
IOH
I
P0[1]
Integrating input.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset).
2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.
Document Number: 001-12696 Rev. *C
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24-Pin Part Pinout
Table 3. 24-Pin QFN Part Pinout(2, 3)
Type
Digital Analog
Figure 3. CY8C20346, CY8C20366 24-Pin PSoC Device
Pin
No.
Name
Description
1
2
3
4
5
6
7
IO
IO
IO
IOHR
IOHR
IOHR
IOHR
I
I
I
I
I
I
I
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
Crystal output (XOut).
Crystal input (XIn).
18
17
16
15
AI, XOut, P2[5]
AI, XIn, P2[3]
1
2
3
4
5
6
P0[4], AI
P0[2], AI
P0[0], AI
P2[0], AI
XRES
I2C SCL, SPI SS.
I2C SDA, SPI MISO.
SPI CLK.
AI, P2[1]
QFN
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
(Top View)
14
13
ISSP CLK(1), I2C SCL, SPI
P1[6], AI
MOSI.
8
NC
No connection.
9
10
Power
IOHR
Vss
P1[0]
Ground connection.
ISSP DATA(1), I2C SDA, SPI
CLK.
I
11
12
IOHR
IOHR
I
I
P1[2]
P1[4]
Optional external clock input
(EXTCLK).
13
14
IOHR
I
P1[6]
Input
XRES Active high external reset with
internal pull down.
15
16
17
18
19
20
21
22
23
24
CP
IO
I
I
I
I
I
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
IOH
IOH
IOH
IOH
Power
Power
Vdd
Supply voltage.
IOH
IOH
IOH
IOH
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Integrating input.
Integrating input.
Center pad must be connected
to ground.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Note
3. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 001-12696 Rev. *C
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32-Pin Part Pinout
Table 4. 32-Pin QFN Part Pinout (2, 3)
Type
Digital Analog
Figure4. CY8C20446,CY8C2046632-PinPSoCDevice
Pin
No.
Name
Description
1
2
3
4
5
6
7
8
IOH
IO
IO
IO
IO
IO
IO
IOHR
IOHR
IOHR
IOHR
I
I
I
I
I
I
I
I
I
I
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
Integrating input.
Crystal output (XOut)
Crystal input (XIn)
AI, P0[1]
AI, P2[7]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
QFN
(Top View)
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
I2C SCL, SPI SS.
I2C SDA, SPI MISO.
SPI CLK.
ISSP CLK(1), I2C SCL, SPI MOSI.
Ground connection.
ISSP DATA(1), I2C SDA., SPI CLK
9
10
11
12
13
14
15
Power
Input
IOHR
IOHR
IOHR
I
I
I
P1[0]
P1[2]
P1[4]
Optional external clock input
(EXTCLK).
16
17
IOHR
I
P1[6]
XRES Active high external reset with
internal pull down.
18
IO
I
P3[0]
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
IO
IO
IO
IO
IO
IOH
IOH
IOH
IOH
I
I
I
I
I
I
I
I
I
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Power
Vdd
Supply voltage.
IOH
IOH
IOH
I
I
I
P0[7]
P0[5]
P0[3]
Vss
Integrating input.
Ground connection.
Power
Power
Vss
Center pad must be connected to
ground.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *C
Page 10 of 34
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CY8C20x46, CY8C20x66
48-Pin SSOP Part Pinout
(2)
Table 5. 48-Pin SSOP Part Pinout
Figure 5. CY8C20546, CY8C20566-48-Pin SSOP PSoC Device
Name
Description
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
1
2
3
4
5
6
VDD
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
IOH
IOH
IOH
IOH
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
P2[5]
P2[3]
7
P2[1]
NC
NC
8
XTAL Out
9
XTAL In
10
P4[3]
P4[1]
NC
11
12
13
14
9
10
No connection
No connection
SSOP
NC
P3[7]
11 IO
12 IO
13
IO
IO
P4[3]
P4[1]
NC
P3[7]
P3[5]
P3[3]
P3[1]
NC
P3[5] 15
P3[3] 16
P3[1] 17
NC
NC
No connection
NC
18
19
20
NC
14 IO
15 IO
16 IO
17 IO
18
IO
IO
IO
IO
NC
NC
P1[7]
NC
P1[5] 21
P1[3]
P1[1] 23
P1[6]
22
P1[4]
P1[2]
No connection
No connection
VSS
24
P1[0]
19
NC
20 IOHR IO
21 IOHR IO
22 IOHR IO
23 IOHR IO
24
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
TC CLK(1), I2C SCL, SPI MOSI
Ground Pin
25 IOHR IO
TC DATA(1), I2C SDA, SPI
CLK
26 IOHR IO
27 IOHR IO
28 IOHR IO
29
30
31
32
P1[2]
P1[4]
P1[6]
NC
NC
NC
EXT CLK
No connection
No connection
No connection
No connection
NC
Name
Description
33
34
35
NC
NC
No connection
No connection
41
42
IO
IO
IO
IO
IO
IO
P2[2]
P2[4]
P2[6]
XRES Active high external reset with 43
internal pull down
36 IO
37 IO
38 IO
39 IO
40 IO
IO
IO
IO
IO
IO
P3[0]
P3[2]
P3[4]
P3[6]
P2[0]
44
45
46
47
48
IOH IO
IOH IO
IOH IO
IOH IO
Power
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
Document Number: 001-12696 Rev. *C
Page 11 of 34
[+] Feedback
CY8C20x46, CY8C20x66
48-Pin QFN Part Pinout
(2, 3)
Table 6. 48-Pin QFN Part Pinout
Figure 6. CY8C20666 48-Pin QFN PSoC Device
Pin
Name
No.
Description
1
2
3
4
5
6
7
8
NC
No connection.
NC
AI, P2[7]
AI, XOut, P2[5]
P2[6],AI
P2[4],AI
P2[2],AI
P2[0],AI
P4[2],AI
P4[0],AI
36
35
34
33
32
31
1
2
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
Crystal output (XOut).
Crystal input (XIn).
3
4
5
6
AI, XIn , P2[3]
AI, P2[1]
AI, P4[3]
AI, P4[1]
AI, P3[7]
QFN
30
29
28
27
(Top View)
P3[6],AI
P3[4], AI
7
8
9
10
AI, P3[5]
P3[2],AI
], AI
P3[0
AI, P3[3]
9
AI, P3[1]
XRES
P1[6], AI
26
25
11
12
10
11
12
13
14
15
16
17
AI, I2C SCL, SPI SS, P1[7]
IO
IOHR
IOHR
I2C SCL, SPI SS.
I2C SDA, SPI MISO.
No connection.
No connection.
SPI CLK.
NC
P1[3]
P1[1]
IOHR
IOHR
I
I
ISSP CLK(1), I2C SCL, SPI
MOSI.
18
19
20
21
22
Power
IO
IO
Power
IOHR
Vss
D+
D-
Vdd
P1[0]
Ground connection.
Supply voltage.
I
ISSP DATA(1), I2C SDA, SPI
CLK.
23
24
IOHR
IOHR
I
I
P1[2]
P1[4]
Optional external clock input
(EXTCLK).
25
26
IOHR
I
P1[6]
Input
XRES Active high external reset with
internal pull down.
27
28
29
IO
IO
IO
I
I
I
P3[0]
P3[2]
P3[4]
Pin
No.
Name
Description
30
31
32
33
34
35
36
37
38
39
IO
IO
IO
IO
IO
IO
IO
IOH
IOH
IOH
I
I
I
I
I
I
I
I
I
I
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
40
41
42
43
44
45
46
47
48
CP
IOH
Power
I
P0[6]
Vdd
NC
Supply voltage.
No connection.
No connection.
NC
IOH
IOH
IOH
Power
IOH
I
I
I
P0[7]
P0[5]
P0[3]
Vss
P0[1]
Vss
Integrating input.
Ground connection.
I
Power
Center pad must be connected to ground.
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *C
Page 12 of 34
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CY8C20x46, CY8C20x66
48-Pin QFN OCD Part Pinout
The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit
(4)
debugging.
(2, 3)
Table 7. 48-Pin OCD QFN Part Pinout
Figure 7. CY8C20066 48-Pin OCD PSoC Device
Pin
Name
Description
No.
1
2
3
4
5
6
7
8
OCDOE
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
CCLK
HCLK
P1[3]
P1[1]
OCD mode direction pin.
OCDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P4[2], AI
P4[0], AI
P3[6], AI
P3[4], AI
P3[2], AI
P3[0], AI
36
35
34
33
32
31
1
2
E
A
, P2[7]
Crystal output (XOut).
Crystal input (XIn).
I
AI, XOut, P2[5]
3
4
5
6
AI, XIn , P2[3]
AI, P2[1]
AI, P4[3]
AI, P4[1]
AI, P3[7]
QFN
30
29
28
27
(Top View)
7
8
9
10
AI, P3[5]
AI, P3[3]
9
AI, P3[1]
XRES
P1[6], AI
26
25
11
12
10
11
12
13
14
15
16
17
AI, I2C SCL, SPI SS, P1[7]
IO
IOHR
IOHR
I2C SCL, SPI SS.
I2C SDA, SPI MISO.
OCD CPU clock output.
OCD high speed clock output.
SPI CLK.
IOHR
IOHR
I
I
ISSP CLK(1), I2C SCL, SPI
MOSI.
18
19
20
21
22
Power
IO
IO
Power
IOHR
Vss
D+
D-
Vdd
P1[0]
Ground connection.
Supply voltage.
I
I
ISSP DATA(1), I2C SDA, SPI
CLK.
23
IOHR
P1[2]
Pin
No.
Name
Description
24
IOHR
IOHR
I
I
P1[4]
Optional external clock input
(EXTCLK).
37
IOH
I
P0[0]
25
26
P1[6]
XRES
38
IOH
IOH
I
I
P0[2]
P0[4]
Input
Active high external reset with 39
internal pull down.
27
28
29
30
31
32
33
34
35
36
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
I
I
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
40
41
42
43
44
45
46
47
48
CP
IOH
Power
I
P0[6]
Vdd
Supply voltage.
OCDO OCD even data IO.
OCDE OCD odd data output.
P0[7]
P0[5]
P0[3]
Vss
IOH
IOH
IOH
Power
IOH
Power
I
I
I
Integrating input.
Ground connection.
I
P0[1]
Vss
Center pad must be connected to ground.
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Note
4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
Document Number: 001-12696 Rev. *C
Page 13 of 34
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CY8C20x46, CY8C20x66
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x46/CY8C20x66 PSoC devices. For the most up-to-date
electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Figure 8. Voltage versus CPU Frequency
Figure 9. IMO Frequency Trim Options
5.5V
5.5V
SLIMO SLIMO SLIMO
Mode
= 01
Mode
= 00
Mode
= 10
1.71V
1.71V
750 kHz
3 MHz
750 kHz
3 MHz
6 MHz 12 MHz 24 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 8. Units of Measure
Symbol
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilo samples per second
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microwatts
Symbol
Unit of Measure
o
C
mA
ms
mV
nA
ns
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
dB
fF
Hz
KB
Kbit
kHz
ksps
kΩ
MHz
MΩ
µA
nV
Ω
pA
pF
pp
ppm
ps
sps
s
V
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
µF
µH
µs
µW
Document Number: 001-12696 Rev. *C
Page 14 of 34
[+] Feedback
CY8C20x46, CY8C20x66
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V.
Table 9. Comparator User Module Electrical Specifications
Symbol
Description
Comparator Response Time
Min
Typ
70
2.5
20
Max
100
30
Units
ns
mV
Conditions
50 mV overdrive
T
COMP
Offset
Current
PSRR
80
µA Average DC current, 50 mV
overdrive
Supply voltage >2V
Supply voltage <2V
80
40
dB Power Supply Rejection Ratio
dB Power Supply Rejection Ratio
V
Input
0
1.5
Range
ADC Electrical SpecificationsAbsolute Maximum
Table 10. ADC User Module Electrical Specifications
Symbol
Description
Min
Vss
8
Typ
Max
Units
Conditions
Input
V
C
Input Voltage Range
Input Capacitance
Resolution
8-Bit Sample Rate
1.3
5
10
V
pF
This gives 72% of maximum code
IN
IN
Bits Settings 8, 9, or 10
-
23.4375
5.859
ksps Data Clock set to 6 MHz. Sample
Rate = 0.001/(2^Resolution/Data
clock)
ksps Data Clock set to 6 MHz. Sample
Rate = 0.001/(2^Resolution/Data
clock)
-
10-Bit Sample Rate
DC Accuracy
-
-
-
DNL
INL
Offset Error
Operating Current
Data Clock
-1
-2
0
+2
+2
90
350
12
LSB For any configuration
LSB For any configuration
mV
µA
MHz Source is chip’s internal main oscil-
lator. See device data sheet for
accuracy.
15
275
I
F
ADC
2.25
CLK
Monotonicity
Not guaranteed. See DNL
PSRR Power Supply Rejection Ration
-
-
-
-
PSRR (Vdd>3.0V)
24
30
12
0
dB
dB
dB
dB
5
PSRR (2.2 < Vdd < 3.0)
PSRR (2.0 < Vdd < 2.2)
PSRR (Vdd < 2.0)
Gain Error
Input Resistance
1
1/
%FSR For any resolution
R
1/
1/
Ω
Equivalent switched cap input resis-
IN
(500fF*Data- (400fF*Data- (300fF*Data-
tance for 8-, 9-, or 10-bit resolution.
Clock)
Clock)
Clock)
Document Number: 001-12696 Rev. *C
Page 15 of 34
[+] Feedback
CY8C20x46, CY8C20x66
Ratings
Table 11. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Conditions
Min
–55
Typ
+25
Max
+125
Units
C
o
T
Higher storage temperatures reduces data
retention time. Recommended Storage
Temperature is +25°C ± 25°C. Extended
STG
o
duration storage temperatures above 85 C
degrades reliability.
Vdd
Supply Voltage Relative to Vss
DC Input Voltage
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
–0.5
Vss – 0.5
Vss –0.5
–25
2000
–
–
–
–
–
–
–
+6.0
Vdd + 0.5
Vdd + 0.5
+50
V
V
V
mA
V
mA
V
V
I
IO
IOZ
MIO
ESD
LU
Human Body Model ESD
In accordance with JESD78 standard
–
200
Operating Temperature
Table 12. Operating Temperature
Symbol
Description
Ambient Temperature
Conditions
Min
–40
Typ
–
Max
+85
Units
C
o
T
A
T
Operational Die Temperature
The temperature rise from ambient to
junction is package specific. See the table
Thermal Impedances per Package on page
28. The user must limit the power
consumption to comply with this
requirement.
J
o
–40
–
+100
C
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Chip-Level Specifications
Symbol
Vdd
Description
Supply Voltage
Conditions
Min
1.71
Typ
–
Max
5.5
Units
V
See the table DC POR and LVD
Specifications on page 20
o
I
I
I
Supply Current, IMO = 24 MHz
Supply Current, IMO = 12 MHz
Supply Current, IMO = 6 MHz
Deep Sleep Current
Conditions are Vdd = 3.0V, T = 25 C, CPU
–
–
–
2.88
1.71
1.16
4.0
2.6
1.8
mA
mA
mA
DD24
DD12
DD6
A
= 24 MHz. CapSense running at 12 MHz, no
IO sourcing current
o
Conditions are Vdd = 3.0V, T = 25 C, CPU
A
= 12 MHz. CapSense running at 12 MHz, no
IO sourcing current
o
Conditions are Vdd = 3.0V, T = 25 C, CPU
A
= 6 MHz. CapSense running at 6 MHz, no IO
sourcing current
Vdd = 3.0V, T = 25 C, IO regulator turned
o
I
I
–
–
0.1
–
µA
µA
SB0
SB1
A
off
o
Standby Current with POR, LVD
and Sleep Timer
Vdd = 3.0V, T = 25 C, IO regulator turned
1.07
1.5
A
off
Document Number: 001-12696 Rev. *C
Page 16 of 34
[+] Feedback
CY8C20x46, CY8C20x66
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and
–40°C ≤ T ≤ 85°C, 2.4V to 3.0V and –40°C ≤ T ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V and 3.3V at 25°C and are for design guidance only.
Table 14. 3.0V to 5.5V DC GPIO Specifications
Symbol
Description
Pull up Resistor
Conditions
Min
4
Typ
5.6
–
Max
8
–
Units
kΩ
V
R
PU
V
V
V
High Output Voltage
IOH < 10 µA, maximum of 10 mA source Vdd - 0.2
OH1
Port 2 or 3 Pins
current in all IOs
High Output Voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source Vdd - 0.9
–
–
–
–
V
V
OH2
OH3
current in all IOs
High Output Voltage
IOH < 10 µA, maximum of 10 mA source Vdd - 0.2
Port 0 or 1 Pins with LDO Regulator current in all IOs
Disabled for Port 1
V
V
V
V
V
V
V
V
High Output Voltage
IOH = 5 mA, maximum of 20 mA source Vdd - 0.9
–
3.00
–
–
3.3
–
V
V
V
V
V
V
V
V
OH4
OH5
OH6
OH7
OH8
OH9
OH10
OL
Port 0 or 1 Pins with LDO Regulator current in all IOs
Disabled for Port 1
High Output Voltage
IOH < 10 µA, Vdd > 3.1V, maximum of 4
2.85
2.20
2.35
1.90
1.60
1.20
–
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOs all sourcing 5 mA
High Output Voltage
IOH = 5 mA, Vdd > 3.1V, maximum of 20
mA source current in all IOs
Port 1 Pins with LDO Regulator
Enabled for 3V Out
High Output Voltage
IOH < 10 µA, Vdd > 2.7V, maximum of 20
2.50
–
2.75
–
Port 1 Pins with LDO Enabled for 2.5V mA source current in all IOs
Out
High Output Voltage
IOH = 2 mA, Vdd > 2.7V, maximum of 20
Port 1 Pins with LDO Enabled for 2.5V mA source current in all IOs
Out
High Output Voltage
IOH < 10 µA, Vdd > 2.7V, maximum of 20
1.80
–
2.1
–
Port 1 Pins with LDO Enabled for 1.8V mA source current in all IOs
Out
High Output Voltage
IOH = 1 mA, Vdd > 2.7V, maximum of 20
Port 1 Pins with LDO Enabled for 1.8V mA source current in all IOs
Out
Low Output Voltage
IOL = 25 mA, Vdd > 3.3V, maximum of 60
–
0.75
mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
V
V
V
Input Low Voltage
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Pin Capacitance
–
2.00
–
–
0.5
–
–
80
0.001
1.7
0.80
V
V
mV
µA
pF
IL
IH
H
–
1
5
I
IL
C
Package and pin dependent
PIN
o
Temp = 25 C
Document Number: 001-12696 Rev. *C
Page 17 of 34
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Table 15. 2.4V to 3.0V DC GPIO Specifications
Symbol Description
Pull up Resistor
Conditions
Min
4
Vdd - 0.2
Typ
5.6
–
Max
8
–
Units
kΩ
V
R
PU
V
V
V
High Output Voltage
IOH < 10 µA, maximum of 10 mA
OH1
Port 2 or 3 Pins
source current in all IOs
High Output Voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
Vdd - 0.4
Vdd - 0.2
–
–
–
–
V
V
OH2
OH3
source current in all IOs
High Output Voltage
IOH < 10 µA, maximum of 10 mA
Port 0 or 1 Pins with LDO Regulator
source current in all IOs
Disabled for Port 1
V
V
V
V
High Output Voltage
IOH = 2 mA, maximum of 10 mA
source current in all IOs
Vdd - 0.5
1.50
1.20
–
–
1.80
–
–
2.1
–
V
V
V
V
OH4
OH5A
OH6A
OL
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
High Output Voltage
IOH < 10 µA, Vdd > 2.4V, maximum of
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
High Output Voltage
IOH = 1 mA, Vdd > 2.4V, maximum of
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
Low Output Voltage
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
0.75
V
V
V
Input Low Voltage
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins
–
1.4
–
–
0.5
–
–
80
0.001
1.7
0.72
V
V
mV
µA
pF
IL
IH
H
–
1
5
I
IL
C
Package and pin dependent
PIN
o
Temp = 25 C
Table 16. 1.71V to 2.4V DC GPIO Specifications
Symbol Description
Pull up Resistor
Conditions
Min
4
Vdd - 0.2
Typ
5.6
–
Max
8
–
Units
kΩ
V
R
PU
V
V
V
High Output Voltage
IOH = 10 µA, maximum of 10 mA
OH1
Port 2 or 3 Pins
source current in all IOs
High Output Voltage
Port 2 or 3 Pins
IOH = 0.5 mA, maximum of 10 mA
Vdd - 0.5
Vdd - 0.2
–
–
–
–
V
V
OH2
OH3
source current in all IOs
High Output Voltage
IOH = 100 µA, maximum of 10 mA
Port 0 or 1 Pins with LDO Regulator
source current in all IOs
Disabled for Port 1
V
V
High Output Voltage
IOH=2mA, maximumof10mAsource Vdd - 0.5
current in all IOs
–
–
–
V
V
OH4
OL
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
Low Output Voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
0.4
V
Input Low Voltage
–
–
0.3 x Vdd
V
IL
Document Number: 001-12696 Rev. *C
Page 18 of 34
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Table 16. 1.71V to 2.4V DC GPIO Specifications (continued)
Symbol Description
Input High Voltage
Conditions
Min
0.65 x Vdd
Typ
–
80
0.001
1.7
Max
Units
V
mV
µA
V
V
IH
H
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins
–
–
0.5
–
1
5
I
C
IL
Package and pin dependent
pF
PIN
o
Temp = 25 C
Table 17.DC Characteristics – USB Interface
Symbol
Rusbi
Rusba
Vohusb
Volusb
Vdi
Description
USB D+ Pull Up Resistance
USB D+ Pull Up Resistance
Static Output High
Static Output Low
Differential Input Sensitivity
Conditions
With idle bus
While receiving traffic
Min
0.900
1.425
2.8
Typ
Max
1.575
3.090
3.6
Units
kΩ
kΩ
V
V
V
-
-
-
-
-
-
0.3
0.2
0.8
Vcm
Differential Input Common Mode
2.5
V
Range
Vse
Cin
Iio
Rps2
Rext
Single Ended Receiver Threshold
Transceiver Capacitance
Hi-Z State Data Line Leakage
PS/2 Pull Up Resistance
0.8
-
-
-
2.0
50
+10
7
V
pF
µA
kΩ
Ω
On D+ or D- line
-10
3
21.78
5
22.0
External USB Series Resistor
In series with each USB pin
22.22
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. DC Analog Mux Bus Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
R
Switch Resistance to Common Analog
–
–
800
Ω
SW
Bus
R
Resistance of Initialization Switch to
Vss
–
–
800
Ω
GND
The maximum pin voltage for measuring R
and R
is 1.8V
SW
GND
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
V
Low Power Comparator (LPC)
Maximum voltage limited to Vdd
0.0
–
1.8
V
LPC
common mode
I
V
LPC supply current
LPC voltage offset
–
–
10
2.5
40
30
µA
mV
LPC
OSLPC
Document Number: 001-12696 Rev. *C
Page 19 of 34
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DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 20. DC POR and LVD Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Vdd Value for PPOR Trip
Vdd must be greater than or equal to
V
PORLEV[1:0] = 00b, HPOR = 0 1.71V during startup, reset from the
PORLEV[1:0] = 00b, HPOR = 1 XRES pin, or reset from watchdog.
PORLEV[1:0] = 01b, HPOR = 1
1.61
–
1.66
2.36
2.60
2.82
1.71
2.41
2.66
2.95
V
V
V
V
PPOR0
PPOR1
PPOR2
PPOR3
V
V
V
PORLEV[1:0] = 10b, HPOR = 1
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
[5]
[6]
[7]
V
V
V
V
V
V
V
V
2.40
2.64
2.85
2.45
2.71
2.92
3.02
3.13
1.90
1.80
4.73
2.51
2.78
2.99
3.09
3.20
2.32
1.84
4.83
V
V
V
V
V
V
V
V
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
2.95
3.06
1.84
[8]
1.75
4.62
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 21. DC Programming Specifications
Symbol
Vdd
Description
Conditions
Min
1.71
Typ
–
Max
–
Units
V
Supply Voltage for Flash Write
IWRITE
Operations
I
Supply Current During
Programming or Verify
–
–
5
–
–
25
mA
V
DDP
V
V
Input Low Voltage During
See the appropriate DC General Purpose
IO Specifications on page 17
See appropriate DC General Purpose IO
Specifications on page 17 table on pages
15 or 16
V
IL
ILP
Programming or Verify
Input High Voltage During
Programming or Verify
V
–
V
IHP
IH
I
I
Input Current when Applying Driving internal pull down resistor
–
–
–
0.2
1.5
mA
mA
ILP
Vilp to P1[0] or P1[1] During
Programming or Verify
Input Current when Applying Driving internal pull down resistor
–
IHP
Vihp to P1[0] or P1[1] During
Programming or Verify
V
V
Output Low Voltage During
–
–
–
Vss + 0.75
Vdd
V
V
OLP
Programming or Verify
Output High Voltage During
Programming or Verify
See appropriate DC General Purpose IO
Specifications on page 17 table on page
V
OH
OHP
16. For Vdd > 3V use V
in Table 12 on
OH4
page 16.
Flash
Flash
Flash Write Endurance
Flash Data Retention
Erase/write cycles per block
50,000
10
–
20
–
–
Cycles
Years
ENPB
DR
Following maximum Flash write cycles;
ambient temperature of 55°C
Notes
5. Always greater than 50 mV above V
6. Always greater than 50 mV above V
7. Always greater than 50 mV above V
8. Always greater than 50 mV above V
voltage for falling supply.
PPOR1
PPOR2
PPOR3
PPOR0
voltage for falling supply.
voltage for falling supply.
voltage for falling supply.
Document Number: 001-12696 Rev. *C
Page 20 of 34
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AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. AC Chip-Level Specifications
Symbol
Description
Conditions
Min
24
24
19
22.8
Typ
–
–
32
24
Max
–
–
50
25.2
Units
MHz
MHz
kHz
F
F
F
F
Maximum Operating Frequency
Maximum Processing Frequency
Internal Low Speed Oscillator Frequency
MAX
CPU
32K1
IMO24
Internal Main Oscillator Frequency at 24
MHz
MHz Setting
F
F
Internal Main Oscillator Frequency at 12
MHz Setting
11.4
5.7
12
12.6
6.3
MHz
MHz
IMO12
IMO6
Internal Main Oscillator Frequency at 6
6.0
MHz Setting
DC
Duty Cycle of IMO
Supply Ramp Time
External Reset Pulse Width at Power Up After supply voltage is valid
40
0
1
50
–
60
–
%
µs
ms
µs
IMO
RAMP
XRST
XRST2
T
T
T
External Reset Pulse Width after Power Applies after part has booted
10
Up
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 23. AC GPIO Specifications
Symbol
Description
Conditions
Min Typ
Max
Units
F
GPIO Operating Frequency
Normal Strong Mode Port 0, 1
0
–
6 MHz for
MHz
GPIO
1.71V<Vdd<2.4V
0
–
–
–
12 MHz for
2.4V<Vdd<5.5V
TRise23
Rise Time, Strong Mode, Cload = 50 pF
Ports 2 or 3
Vdd = 3.0 to 3.6V, 10% – 90%
Vdd = 1.71 to 3.0V, 10% – 90%
15
15
80
80
ns
ns
TRise23L
Rise Time, Strong Mode Low Supply,
Cload = 50 pF
Ports 2 or 3
TRise01
Rise Time, Strong Mode, Cload = 50 pF
Vdd = 3.0 to 3.6V, 10% – 90%
LDO enabled or disabled
10
10
–
–
50
80
ns
ns
Ports 0 or 1
TRise01L
Rise Time, Strong Mode Low Supply,
Cload = 50 pF
Vdd = 1.71 to 3.0V, 10% – 90%
LDO enabled or disabled
Ports 0 or 1
TFall
Fall Time, Strong Mode, Cload = 50 pF
Vdd = 3.0 to 3.6V, 10% – 90%
10
10
–
–
50
70
ns
ns
All Ports
TFallL
Fall Time, Strong Mode Low Supply, Cload Vdd = 1.71 to 3.0V, 10% – 90%
= 50 pF
All Ports
Document Number: 001-12696 Rev. *C
Page 21 of 34
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Figure 10. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TRise23L
TRise01L
TFall
TFallL
Table 24.AC Characteristics – USB Data Timings
Symbol Description
Tdrate Full speed data rate
Conditions
Average bit rate
Min
12–0.25%
Typ
12
Max
Units
MHz
12 +
0.25%
Tdjr1
Tdjr2
Tudj1
Tudj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Receiver data jitter tolerance
Receiver data jitter tolerance
Driver differential jitter
To next transition
To pair transition
To next transition
To pair transition
To SE0 transition
-18.5
-9
-3.5
-4.0
-2
–
–
–
–
–
–
–
–
18.5
9
3.5
4.0
5
ns
ns
ns
ns
ns
ns
ns
ns
Driver differential jitter
Source jitter for differential transition
Source SE0 interval of EOP
Receiver SE0 interval of EOP
160
82
175
Width of SE0 interval during differential
14
transition
Table 25.AC Characteristics – USB Driver
Symbol Description
Tr Transition rise time
Conditions
Min
4
4
Typ
–
–
Max
20
20
Units
ns
ns
50 pF
50 pF
Tf
Transition fall time
TR
Vcrs
Rise/fall time matching
Output signal crossover voltage
90.00
1.3
–
–
111.1
2.0
%
V
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 26. AC Low Power Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
T
Comparator Response Time, 50 mV
50 mV overdrive does not
100
ns
LPC
Overdrive
include offset voltage.
Document Number: 001-12696 Rev. *C
Page 22 of 34
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AC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC Analog Mux Bus Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
F
Switch Rate
Maximum pin voltage when measuring
–
–
6.3
MHz
SW
switch rate is 1.8Vp-p
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC External Clock Specifications
Symbol
Description
Conditions
Min
0.750
20.6
20.6
150
Typ
–
–
–
–
Max
25.2
5300
–
Units
MHz
ns
ns
µs
F
Frequency
High Period
Low Period
OSCEXT
–
–
–
Power Up IMO to Switch
–
AC Programming Specifications
Figure 11. AC Waveform
SCLK (P1[1])
TRSCLK
TFSCLK
SDATA (P1[0])
TSSCLK
THSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC Programming Specifications
Symbol
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK 3.6 < Vdd
Data Out Delay from Falling Edge of SCLK 3.0 ≤ Vdd ≤ 3.6
Data Out Delay from Falling Edge of SCLK 1.71 ≤ Vdd ≤ 3.0
Conditions
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
–
–
–
Max
20
20
–
–
8
18
25
60
85
130
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ns
T
T
T
T
F
T
T
T
T
T
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
ERASEB
WRITE
DSCLK
DSCLK3
DSCLK2
–
–
–
Document Number: 001-12696 Rev. *C
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AC SPI Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 30. AC SPI Specifications
Symbol
Description
Conditions
Min
–
Typ
–
Max
12
Units
MHz
F
Outputclockfrequencyishalfof
Maximum Input Clock Frequency Selection,
SPIM
input clock rate.
Master 2.4V<Vdd<5.5V
Outputclockfrequencyishalfof
input clock rate
6
MHz
Maximum Input Clock Frequency Selection,
Master(21)1.71V<Vdd<2.4V
F
T
Maximum Input Clock Frequency Selection,
–
–
–
12
6
MHz
MHz
ns
SPIS
SS
Slave 2.4<Vdd<5.5V
Maximum Input Clock Frequency Selection,
Slave 1.71V<Vdd<2.4V
Width of SS_ Negated Between Transmissions
50
–
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 31. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Conditions
Units
Min
0
Max
100
–
Min
0
Max
400
–
F
T
kHz
µs
SCLI2C
Hold Time (repeated) START Condition. After
4.0
0.6
HDSTAI2C
this period, the first clock pulse is generated.
T
T
T
T
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100
0.6
1.3
–
–
–
–
–
–
–
µs
µs
µs
µs
ns
µs
µs
LOWI2C
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
[9]
Bus Free Time Between a STOP and START
Condition
T
Pulse Width of spikes are suppressed by the
input filter.
–
–
0
50
ns
SPI2C
Figure 12. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Note
9. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This automatically be the case
SU;DAT
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SU;DAT
Document Number: 001-12696 Rev. *C
Page 24 of 34
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CY8C20x46, CY8C20x66
Packaging Information
This section illustrates the packaging specifications for the CY8C20x46/CY8C20x66 PSoC device, along with the thermal impedances
for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 13. 16-Pin Chip On Lead 3x3 mm (Sawn)
001-09116 *D
Figure 14. 24-Pin (4x4 x 0.6 mm) QFN
001-13937 *B
Document Number: 001-12696 Rev. *C
Page 25 of 34
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CY8C20x46, CY8C20x66
Figure 15. 32-Pin (5x5 x 0.6 mm) QFN
001-42168 *B
Figure 16. 48-Pin (300 MIL) SSOP
.020
24
1
0.395
0.420
0.292
0.299
DIMENSIONS IN INCHES MIN.
MAX.
25
48
0.620
0.630
0.005
0.010
SEATING PLANE
.010
0.088
0.092
0.095
0.110
GAUGE PLANE
0.004
0.024
0.040
0.025
BSC
0°-8°
0.008
0.016
0.008
0.0135
51-85061 *C
Document Number: 001-12696 Rev. *C
Page 26 of 34
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CY8C20x46, CY8C20x66
Figure 17. 48-Pin (7x7 mm) QFN
001-13191 *C
Important Note
■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■ Pinned vias for thermal conduction are not required for the low power PSoC device.
Document Number: 001-12696 Rev. *C
Page 27 of 34
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CY8C20x46, CY8C20x66
Thermal Impedances
Table 32. Thermal Impedances per Package
[10]
Package
Typical θJA
o
32.69 C/W
16 QFN
o
[11]
20.90 C/W
24 QFN
o
[11]
19.51 C/W
32 QFN
o
69 C/W
48 SSOP
o
[11]
17.68 C/W
48 QFN
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 33. Solder Reflow Peak Temperature
[12]
Package
16 QFN
24 QFN
32 QFN
48 SSOP
48 QFN
Maximum Peak Temperature
Minimum Peak Temperature
o
o
240 C
260 C
o
o
240 C
260 C
o
o
240 C
260 C
o
o
220 C
260 C
o
o
240 C
260 C
Notes
10. T = T + Power x θ .
JA
J
A
11. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
o
o
12. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-12696 Rev. *C
Page 28 of 34
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CY8C20x46, CY8C20x66
Development Kits
Development Tool Selection
This section presents the development tools available for all
current PSoC device families including the CY8C20x46/
CY8C20x66 family.
All development kits can be purchased from the Cypress Online
Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
■ PSoC Designer Software CD
http://www.cypress.com under Software.
■ ICE-Cube In-Circuit Emulator
PSoC Express™
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
free of charge at http://www.cypress.com/psocexpress.
■ Mini-Eval Programming Board
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
PSoC Programmer
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of charge at http://www.cypress.com/psocpro-
grammer.
CY3210-ExpressDK PSoC Express Development Kit
The CY3210-ExpressDK is for advanced prototyping and devel-
opment with PSoC Express (may be used with ICE-Cube In-
2
Circuit Emulator). It provides access to I C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
CY3202-C iMAGEcraft C Compiler
■ PSoC Express Software CD
■ Express Development Board
■ 4 Fan Modules
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com/shop/ under
Product Categories, click PSoC® Mixed Signal Arrays to view a
current list of available items.
■ 2 Proto Modules
■ MiniProg In-System Serial Programmer
■ MiniEval PCB Evaluation Board
■ Jumper Wire Kit
■ USB 2.0 Cable
■ Serial Cable (DB9)
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples
■ 2 CY8C27443-24PXI 28-PDIP Chip Samples
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
Document Number: 001-12696 Rev. *C
Page 29 of 34
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CY8C20x46, CY8C20x66
Evaluation Tools
Device Programmers
All evaluation tools can be purchased from the Cypress Online
All device programmers can be purchased from the Cypress
Store.
Online Store.
CY3210-MiniProg1
CY3216 Modular Programmer
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■ MiniProg Programming Unit
■ Modular Programmer Base
■ 3 Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
■ USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a devel-
opment board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■ PSoCEvalUSB Board
■ LCD Module
■ MIniProg Programming Unit
■ Mini USB Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
Document Number: 001-12696 Rev. *C
Page 30 of 34
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CY8C20x46, CY8C20x66
Accessories (Emulation and Programming)
Table 34. Emulation and Programming Accessories
[13]
[14]
[15]
Part Number
CY8C20246-24LKXI
CY8C20266-24LKXI
CY8C20346-24LQXI
CY8C20366-24LQXI
CY8C20446-24LQXI
CY8C20466-24LQXI
CY8C20546-24PVXI
CY8C20566-24PVXI
CY8C20666-24LTXI
Pin Package
16 QFN
Flex-Pod Kit
Foot Kit
Adapter
CY3250-20266QFN
CY3250-20266QFN
CY3250-20366QFN
CY3250-20366QFN
CY3250-20466QFN
CY3250-20466QFN
CY3250-20X66
CY3250-16QFN-FK
CY3250-16QFN-FK
CY3250-24QFN-FK
CY3250-24QFN-FK
CY3250-32QFN-FK
CY3250-32QFN-FK
CY3250-48SSOP-FK
CY3250-48SSOP-FK
CY3250-48QFN-FK
See note 15
See note 15
See note 15
See note 15
See note 15
See note 15
See note 15
See note 15
See note 15
16 QFN
24 QFN
24 QFN
32 QFN
32 QFN
48 SSOP
48 SSOP
48 QFN
CY3250-20X66
CY3250-20666QFN
Third-Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
third-party vendors to accompany PSoC devices during
development and production. Specific details for each of these
tools can be found at http://www.cypress.com under
Documentation >> Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, refer Application Note “Debugging - Build a PSoC
Emulator into Your Board - AN2323” at http://www.cypress.com/
AN2323.
Notes
13. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
14. Foot kit includes surface mount feet that can be soldered to the target PCB.
15. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-12696 Rev. *C
Page 31 of 34
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CY8C20x46, CY8C20x66
Ordering Information
The following table lists the CY8C20x46 and CY8C20x66 PSoC devices key package features and ordering codes.
Table 35. PSoC Device Key Features and Ordering Information
Flash
SRAM CapSense Digital IO Analog XRES
Package
Ordering Code
USB
(Bytes) (Bytes)
Blocks
Pins
Inputs
Pin
[16]
16 Pin (3x3 x 0.6 mm) QFN
CY8C20246-24LKXI
CY8C20246-24LKXIT
16K
16K
2048
2048
1
13
Yes
No
No
13
[16]
16 Pin (3x3 x 0.6 mm) QFN
1
13
Yes
13
(Tape and Reel)
[16]
24 Pin (4x4 x 0.6 mm) QFN
CY8C20346-24LQXI
CY8C20346-24LQXIT
16K
16K
2048
2048
1
1
20
20
Yes
Yes
No
No
20
[16]
24 Pin (4x4 x 0.6 mm) QFN
20
(Tape and Reel)
[16]
32 Pin (5x5 x 0.6 mm) QFN
CY8C20446-24LQXI
CY8C20446-24LQXIT
16K
16K
2048
2048
1
1
28
28
Yes
Yes
No
No
28
[16]
32 Pin (5x5 x 0.6 mm) QFN
28
(Tape and Reel)
[16]
48-Pin SSOP
CY8C20546-24PVXI
CY8C20546-24PVXIT
16K
16K
2048
2048
1
1
36
36
Yes
Yes
Yes
Yes
36
[16]
48-Pin SSOP
36
(Tape and Reel)
[16]
16 Pin (3x3 x 0.6 mm) QFN
CY8C20266-24LKXI
CY8C20266-24LKXIT
32K
32K
2048
2048
1
1
13
13
Yes
Yes
No
No
13
[16]
16 Pin (3x3 x 0.6 mm) QFN
13
(Tape and Reel)
[16]
24 Pin (4x4 x 0.6 mm) QFN
CY8C20366-24LQXI
CY8C20366-24LQXIT
32K
32K
2048
2048
1
1
20
20
Yes
Yes
No
No
20
[16]
24 Pin (4x4 x 0.6 mm) QFN
20
(Tape and Reel)
[16]
32 Pin (5x5 x 0.6 mm) QFN
CY8C20466-24LQXI
CY8C20466-24LQXIT
32K
32K
2048
2048
1
1
28
28
Yes
Yes
No
No
28
[16]
32 Pin (5x5 x 0.6 mm) QFN
28
(Tape and Reel)
[16]
48-Pin SSOP
CY8C20566-24PVXI
CY8C20566-24PVXIT
32K
32K
2048
2048
1
1
36
36
Yes
Yes
Yes
Yes
36
[16]
48-Pin SSOP
36
(Tape and Reel)
[16]
48 Pin (7x7 mm) QFN
CY8C20666-24LTXI
CY8C20666-24LTXIT
32K
32K
2048
2048
1
1
36
36
Yes
Yes
Yes
Yes
36
[16]
48 Pin (7x7 mm) QFN
36
(Tape and Reel)
(4)
[16]
48 Pin (7x7 mm) QFN (OCD)
CY8C20066-24LTXI
32K
2048
1
36
Yes
Yes
36
Notes
16. Dual-function Digital IO Pins also connect to the common analog mux.
Document Number: 001-12696 Rev. *C
Page 32 of 34
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CY8C20x46, CY8C20x66
Document History Page
Document Title: CY8C20x46 CY8C20x66 CapSenseTM Applications
Document Number: 001-12696
Revision
**
ECN
766857
Origin of Change Submission Date
Description of Change
New silicon and document (Revision **).
HMT
See ECN
*A
1242866 HMT
See ECN
Add features. Update all applicable sections. Update specs.
Fix 24-pin QFN pinout moving pins inside. Update package
revisions. Update and add to Emulation and Programming
Accessories table.
*B
2174006 AESA
See ECN
Added 48-Pin SSOP Part Pinout
Modified symbol R
Specification
to R
in Table DC Analog Mux Bus
VDD
GND
Added footnote in Table DC Analog Mux Bus Specification
Added 16K FLASH Parts. Updated Notes, Package Diagrams
and Ordering Information table. Updated Thermal Impedance
and Solder Reflow tables
*C
2587518 TOF/JASM/MNU/ 10/13/08
HMT
Converted from Preliminary to Final
Fixed broken links. Updated data sheet template.
Added operating voltage ranges with USB
ADC resolution changed from 10-bit to 8-bit
Included ADC specifications table
Included Comparator specification table
Included Voh7, Voh8, Voh9, Voh10 specs
Flash data retention – condition added to Note
Input leakage spec changed to 1 µA max
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
The VIH for 3.0<Vdd<2.4 changed to 1.6 from 2.0
Added USB specification
Added SPI CLK to P1[0]
Updated package diagrams
Updated thermal impedances for QFN packages
Updated F
parameter in Table 23
GPIO
Updated voltage ranges for F
and F
in Table 30
SPIM
SPIS
Update Development Tools, add Designing with PSoC
Designer. Edit, fix links, notes and table format. Update R
IN
formula, fix TRise parameter names in GPIO figure, fix Switch
Rate note. Update maximum data in Table 20. DC POR and
LVD Specifications.
Document Number: 001-12696 Rev. *C
Page 33 of 34
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CY8C20x46, CY8C20x66
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
Wireless
Memories
Image Sensors
PSoC Solutions
General
Low Power/Low Voltage
Precision Analog
LCD Drive
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
CAN 2.0b
USB
psoc.cypress.com/usb
CapSense™, PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. All other
trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys
a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and
company names mentioned in this document may be the trademarks of their respective holders.
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12696 Rev. *C
Revised October 13, 2008
Page 34 of 34
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