CY8C20247-24SXI [CYPRESS]
Microprocessor Circuit, CMOS, PDSO16, 0.150 MM, LEAD FREE, MS-012, SOIC-16;
| 型号： | CY8C20247-24SXI |
| 厂家： | 
CYPRESS |
| 描述： | Microprocessor Circuit, CMOS, PDSO16, 0.150 MM, LEAD FREE, MS-012, SOIC-16 微控制器 光电二极管 外围集成电路 |
| 文件： | 总45页 (文件大小：757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C20xx7/S
1.8 V CapSense® Controller with SmartSense™
Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
1.8
V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
■ 4 Clock Sources
Features
❐ Internal main oscillator (IMO): 6/12/24 MHz
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
■ QuietZone™ Controller
❐ Patented Capacitive Sigma Delta PLUS (CSD PLUS™)
sensing algorithm for robust performance
❐ High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
and sleep timers
❐ External 32 KHz Crystal Oscillator
❐ External Clock Input
■ Programmable pin configurations
❐ Up to 34 general-purpose I/Os (GPIOs)
❐ Dual mode GPIO (Analog and Digital)
❐ High sink current of 25 mA per GPIO
• Max sink current 120 mA for all I/Os combined
❐ Source Current
• 5 mA on ports 0 and 1
• 1 mA on ports 2, 3 and 4
❐ Configurable internal pull-up, high-Z and open drain modes
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
• Overlay thickness of 15 mm for glass and 5 mm plastic
• Proximity Solutions
❐ Superiornoiseimmunityperformanceagainstconductedand
radiated noise and ultra low radiated emissions
• Standardized user modules for overcoming noise
■ Low power CapSense® block with SmartSense Auto-tuning
❐ Low average power consumption –
• 28 µA/sensor in run time (wake-up and scan once every
125 ms)
❐ SmartSense_EMC_PLUS Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
■ Versatile Analog functions
❐ Internal analog bus supports connection of multiple sensors
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process
to form ganged proximity sensor
❐ Internal Low-Dropout voltage regulator for high power supply
rejection ratio (PSRR)
■ Driven shield available on five GPIO pins
❐ Delivers best-in class water tolerant designs
❐ Robust proximity sensing in the presence of metal objects
❐ Supports longer trace lengths
■ Additional system resources
❐ I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Selectable Clock stretch or Forced Nack Mode
• I2C wake from sleep with Hardware address match
❐ 12 MHz (Configurable) SPI master and slave
❐ Three 16-bit timers
❐ Max load of 100 pF (3 MHz)
■ Powerful Harvard-architecture processor
❐ M8C CPU with a max speed of 24 MHz
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ 10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
❐ Two general-purpose high speed, low power analog
comparators
■ Operating Range: 1.71 V to 5.5 V
❐ Standby Mode 1.1 μA (Typ)
❐ Deep Sleep 0.1 μA (Typ)
■ Operating Temperature range: –40 oC to +85 oC
■ Flexible on-chip memory
■ Complete development tools
❐ 8 KB flash, 1 KB SRAM
❐ 16 KB flash, 2 KB SRAM
❐ Free development tool (PSoC Designer™)
❐ 32 KB flash, 2 KB SRAM
■ Sensor and Package options
❐ 50,000 flash erase/write cycles
❐ Read while Write with EEPROM emulation
❐ In-system programming simplifies manufacturing process
❐ 10 Sensing Inputs – 16-pin QFN, 16-pin SOIC
❐ 16 Sensing Inputs – 24-pin QFN
❐ 24 Sensing Inputs – 30-pin WLCSP
❐ 25 Sensing Inputs – 32-pin QFN
❐ 31 Sensing Inputs – 48-pin QFN
Errata: For information on silicon errata, see “Errata” on page 37. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-69257 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 19, 2017
CY8C20xx7/S
Logic Block Diagram
1.8/2.5/3 V
LDO
PWRSYS
[1]
(Regulator)
Port 4
Port 3
Port2
Port 1
Port 0
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2K
SRAM
8K/16K/32K Flash
Nonvolatile Memory
Supervisory ROM(SROM)
Interrupt
Controller
Sleep and
Watchdog
CPU Core(M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Analog
Reference
CapSense
Module
Comparator #1
Comparator #2
Analog
Mux
SYSTEM BUS
Internal
Voltage
References
POR
and
LVD
SPI
Master/
Slave
Three16-Bit
Programmable
Timers
I2C
Slave
System
Resets
Digital
Clocks
SYSTEM RESOURCES
Note
1. Internal voltage regulator for internal circuitry
Document Number: 001-69257 Rev. *P
Page 2 of 45
CY8C20xx7/S
Contents
PSoC® Functional Overview ............................................4
PSoC Core ..................................................................4
CapSense System .......................................................4
Additional System Resources .....................................5
Getting Started ..................................................................5
Application Notes/Design Guides ................................5
Development Kits ........................................................5
Training .......................................................................5
CYPros Consultants ....................................................5
Solutions Library ..........................................................5
Technical Support .......................................................5
Designing with PSoC Designer .......................................6
Select Components .....................................................6
Configure Components ...............................................6
Organize and Connect ................................................6
Generate, Verify, and Debug .......................................6
Pinouts ..............................................................................7
16-pin SOIC (10 Sensing Inputs) ................................7
16-pin QFN (10 Sensing Inputs)[9] ..............................8
24-pin QFN (16 Sensing Inputs)[15] ............................9
30-ball WLCSP (24 Sensing Inputs) ..........................10
32-pin QFN (25 Sensing Inputs)[26] ..........................11
48-pin QFN (31 Sensing Inputs)[32] ..........................12
Electrical Specifications ................................................13
Absolute Maximum Ratings .......................................13
Operating Temperature .............................................13
DC Chip-Level Specifications ....................................14
DC GPIO Specifications ............................................15
DC Analog Mux Bus Specifications ...........................17
DC Low Power Comparator Specifications ...............17
Comparator User Module Electrical Specifications ...18
ADC Electrical Specifications ....................................18
DC POR and LVD Specifications ..............................19
DC Programming Specifications ...............................19
DC I2C Specifications ...............................................20
Shield Driver DC Specifications ................................20
DC IDAC Specifications ............................................20
AC Chip-Level Specifications ....................................21
AC General Purpose I/O Specifications ....................22
AC Comparator Specifications ..................................22
AC External Clock Specifications ..............................22
AC Programming Specifications ................................23
AC I2C Specifications ................................................24
Packaging Information ...................................................27
Thermal Impedances .................................................30
Capacitance on Crystal Pins .....................................30
Solder Reflow Peak Temperature .............................30
Development Tool Selection .........................................31
Software ....................................................................31
Development Kits ......................................................31
Evaluation Tools ........................................................31
Device Programmers .................................................32
Third Party Tools .......................................................32
Ordering Information ......................................................33
Ordering Code Definitions .........................................34
Acronyms ........................................................................35
Reference Documents ....................................................35
Document Conventions .............................................35
Units of Measure .......................................................35
Numeric Naming ........................................................36
Glossary ..........................................................................36
Errata ...............................................................................37
CY8C20xx7/S Qualification Status ............................37
CY8C20xx7/S Errata Summary .................................37
Document History Page .................................................41
Sales, Solutions, and Legal Information ......................45
Worldwide Sales and Design Support .......................45
Document Number: 001-69257 Rev. *P
Page 3 of 45
CY8C20xx7/S
®
Figure 1. CapSense System Block Diagram
PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
CS1
CS2
IDAC
CSN
Vr
The architecture for this device family, as shown in the “Logic
Block Diagram” on page 2, consists of three main areas:
Reference
Buffer
■ The core
Cexternal (P0[1]
or P0[3])
Comparator
■ CapSense analog system
■ System resources
Mux
Mux
Refs
A common, versatile bus allows connection between I/O and the
analog system.
Each CY8C20x37/47/67/S PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 34 GPIOs are also included. The GPIOs
provide access to the MCU and analog mux.
Cap Sense Counters
CSCLK
PSoC Core
CapSense
Clock Select
IMO
Oscillator
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-million instructions per
second (MIPS), 8-bit Harvard-architecture microprocessor.
Analog Multiplexer System
The analog mux bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
CapSense System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to 31
inputs[2]. Capacitive sensing is configurable on each GPIO pin.
Scanning of enabled CapSense pins is completed quickly and
easily across multiple ports.
Switch-control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces, such as sliders and
touchpads.
■ Chip-wide mux that allows analog input from any I/O pin.
■ Crosspoint connection between any I/O pin combinations.
SmartSense™ Auto-tuning
SmartSense auto-tuning is an innovative solution from Cypress
that removes manual tuning of CapSense applications. This
solution is easy to use and provides robust noise immunity. It is
the only auto-tuning solution that establishes, monitors, and
maintains all required tuning parameters of each sensor during
run time. SmartSense auto-tuning allows engineers to go from
prototyping to mass production without retuning for
manufacturing variations in PCB and/or overlay material
properties.
Note
2. 34 GPIOs = 31 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
Document Number: 001-69257 Rev. *P
Page 4 of 45
CY8C20xx7/S
Additional System Resources
Getting Started
System resources provide additional capability, such as
configurable I2C slave, SPI master/slave communication
interface, three 16-bit programmable timers, various system
resets supported by the M8C low voltage detection and power-
on reset. The merits of each system resource are listed here:
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
■ The I2C slave/SPI master-slave module provides 50/100/
400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the CY8C20x37/
47/67/S PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
■ The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
Application Notes/Design Guides
■ The I2C enhanced slave interface appears as a 32-byte RAM
buffer to the external I2C master. Using a simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For more
details, refer to the I2CSBUF User Module datasheet.
Application notes and design guides are an excellent
introduction to the wide variety of possible PSoC designs. They
are located at www.cypress.com/gocapsense. Select
Application Notes under the Related Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which includeArrow, Avnet, Digi-
Key, Farnell, Future Electronics, and Newark. See “Development
Kits” on page 31.
■ Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced power-
on reset (POR) circuit eliminates the need for a system
supervisor.
■ An internal reference provides an absolute reference for
capacitive sensing.
Training
Free PSoC and CapSense technical training (on demand,
webinars, and workshops) is available online at
www.cypress.com/training. The training covers a wide variety of
topics and skill levels to assist you in your designs.
■ A register-controlled bypass mode allows the user to disable
the LDO regulator.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, create a technical support case
or call technical support at 1-800-541-4736.
Document Number: 001-69257 Rev. *P
Page 5 of 45
CY8C20xx7/S
Organize and Connect
Designing with PSoC Designer
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate and Verify
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called “user modules”. User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Document Number: 001-69257 Rev. *P
Page 6 of 45
CY8C20xx7/S
Pinouts
The CY8C20x37/47/67/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES
are not capable of digital I/O.
16-pin SOIC (10 Sensing Inputs)
Table 1. Pin Definitions – CY8C20237-24SXI, CY8C20247/S-24SXI [3]
Type
Figure 2. CY8C20237-24SXI, CY8C20247/S-24SXI
Device
Pin
No.
Name
Description
Digital Analog
1
2
3
4
5
6
7
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
P0[3] Integrating Input
P0[1] Integrating Input
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3]
AI, P0[3]
P0[7], AI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AI, P0[1]
AI, P2[5]
VDD
P0[4], AI
AI, P2[3]
AI, P1[7]
XRES
P1[4], EXTCLK
SOIC
AI, P1[5]
AI, P1[3]
P1[2], AI
P1[0], ISSP DATA, I2C SDA, SPI CLK, AI
AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1]
VSS
P1[1] ISSP CLK[4], I2C SCL, SPI
MOSI
9
Power
VSS Ground connection[7]
10
I/O
I
P1[0] ISSP DATA[4], I2C SDA, SPI
CLK[5]
11
12
I/O
I/O
I
I
P1[2] Driven Shield Output (optional)
P1[4] Optional external clock
(EXTCLK)
13
INPUT
Power
XRES Active high external reset with
internal pull-down[6]
14
15
16
I/O
I/O
I
I
P0[4]
VDD Supply voltage
P0[7]
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
3. 13 GPIOs = 10 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
4. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
5. Alternate SPI clock.
6. The internal pull down is 5KOhm.
7. All VSS pins should be brought out to one common GND plane.
Document Number: 001-69257 Rev. *P
Page 7 of 45
CY8C20xx7/S
[8]
16-pin QFN (10 Sensing Inputs)
Table 2. Pin Definitions – CY8C20237, CY8C20247/S [9]
Type
Pin
Figure 3. CY8C20237, CY8C20247/S Device
Name
Description
No.
Digital Analog
1
2
3
4
5
I/O
I
I
I
I
I
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI CLK
I/O
AI, XOut,P2[5]
AI, XIn,P2[3]
1
2
P0[4] , AI
XRES
IOHR
IOHR
IOHR
12
11
QFN
3
4
(Top View)10 P1[4], EXTCLK, AI
AI,I2 C SCL, SPI SS, P1[7]
AI,I2 C SDA, SPI MISO, P1[5]
9
P1[2] , AI
ISSP CLK[10], I2C SCL, SPI
6
7
IOHR
I
P1[1]
MOSI
Power
VSS Ground connection[13]
ISSP DATA[10], I2C SDA, SPI
8
IOHR
IOHR
IOHR
I
I
I
P1[0]
CLK[11]
9
P1[2] Driven Shield Output (optional)
Optional external clock
(EXTCLK)
10
P1[4]
Active high external reset with
XRES
11
Input
internal pull-down[12]
12
13
14
15
16
IOH
Power
I
P0[4]
VDD Supply voltage
P0[7]
IOH
IOH
IOH
I
I
I
P0[3] Integrating input
P0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
8. No center pad.
9. 13 GPIOs = 10 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
10. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
11. Alternate SPI clock.
12. The internal pull down is 5KOhm.
13. All VSS pins should be brought out to one common GND plane.
Document Number: 001-69257 Rev. *P
Page 8 of 45
CY8C20xx7/S
[14]
24-pin QFN (16 Sensing Inputs)
Table 3. Pin Definitions – CY8C20337, CY8C20347/S [15]
Type
Pin
Figure 4. CY8C20337, CY8C20347/S Device
Name
Description
No.
Digital Analog
1
2
3
4
5
6
7
I/O
I/O
I
I
I
I
I
I
I
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P2[1]
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI CLK
18
17
16
15
AI, XOut, P2[5]
AI, XIn, P2[3]
1
2
3
4
5
6
P0[2], AI
P0[0], AI
P2[4], AI
P2[2], AI
XRES
I/O
IOHR
IOHR
IOHR
IOHR
AI, P2[1]
QFN
(Top View)
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
14
13
P1[6], AI
P1[1] ISSP CLK[16], I2C SCL, SPI
MOSI
8
NC
No connection
9
Power
VSS
Ground connection[19]
10
IOHR
IOHR
IOHR
IOHR
I
I
I
I
P1[0] ISSPDATA[16], I2CSDA, SPI
CLK[17]
11
12
P1[2] Driven Shield Output
(optional)
P1[4] Optional external clock input
(EXTCLK)
13
14
P1[6]
Input
XRES Active high external reset
with internal pull-down[18]
15
16
17
18
I/O
I/O
I
I
I
I
I
P2[2] Driven Shield Output
(optional)
P2[4] Driven Shield Output
(optional)
IOH
IOH
IOH
P0[0] Driven Shield Output
(optional)
P0[2] Driven Shield Output
(optional)
19
20
21
22
23
24
CP
P0[4]
Power
VDD
Supply voltage
IOH
IOH
I
I
P0[7]
P0[3] Integrating input
Power
IOH
Power
VSS
Ground connection[19]
I
P0[1] Integrating input
VSS
Center pad must be
connected to ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
14. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
15. 19 GPIOs = 16 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
16. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
17. Alternate SPI clock.
18. The internal pull down is 5KOhm.
19. All VSS pins should be brought out to one common GND plane.
Document Number: 001-69257 Rev. *P
Page 9 of 45
CY8C20xx7/S
30-ball WLCSP (24 Sensing Inputs)
Table 4. Pin Definitions – CY8C20767, CY8C20747 30-ball Part Pinout (WLCSP) [20]
Type
Pin No.
Name
Description
Figure 5. CY8C20767, CY8C20747 30-ball
WLCSP
Digital
Analog
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
IOH
IOH
I
I
P0[2]
P0[6]
VDD
Driven Shield Output (optional)
Bottom View
5
4
3
2
1
Power
Supply voltage
A
B
C
D
E
F
IOH
I/O
I/O
IOH
IOH
IOH
I/O
I/O
I/O
I/O
IOH
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P0[1]
P2[7]
P4[2]
P0[0]
P0[4]
P0[3]
P2[5]
P2[2]
P2[4]
P0[7]
P3[2]
P2[3]
P2[0]
P3[0]
P3[1]
P3[3]
P2[1]
Integrating Input
Driven Shield Output (optional)
Integrating Input
Crystal Output (Xout)
Driven Shield Output (optional)
Driven Shield Output (optional)
Top View
Crystal Input (Xin)
1
2
3
4
5
A
B
C
Active high external reset with
internal pull-down[21]
E1
E2
E3
E4
Input
XRES
P1[6]
P1[4]
P1[7]
IOHR
IOHR
IOHR
I
I
I
D
E
Optional external clock input
(EXT CLK)
I2C SCL, SPI SS
F
E5
IOHR
I
P1[5]
I2C SDA, SPI MISO
F1
F2
F3
F4
F5
IOHR
IOHR
I
I
P1[2]
P1[0]
VSS
Driven Shield Output (optional)
ISSP DATA[22], I2C SDA, SPI
CLK[23]
Power
IOHR
IOHR
Supply ground[24]
ISSP CLK[22], I2C SCL, SPI
MOSI
I
I
P1[1]
P1[3]
SPI CLK
LEGEND: A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Notes
20. 27 GPIOs = 24 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
21. The internal pull down is 5KOhm.
22. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
23. Alternate SPI clock.
24. All VSS pins should be brought out to one common GND plane.
Document Number: 001-69257 Rev. *P
Page 10 of 45
CY8C20xx7/S
[25]
32-pin QFN (25 Sensing Inputs)
Table 5. Pin Definitions – CY8C20437, CY8C20447/S, CY8C20467/S [26]
Type
Figure 6. CY8C20437, CY8C20447/S, CY8C20467/S Device
Pin
No.
Name
Description
Digital Analog
1
IOH
I/O
I
I
I
I
I
I
I
I
I
I
I
P0[1] Integrating input
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P2[1]
2
3
I/O
AI
,P0[1]
AI, XOut,P2[5]
AI
1
2
3
4
5
6
7
8
24 P2[4] , AI
23 P2[2] , AI
22 P2[0] , AI
21 P4[2] , AI
20 P4[0] , AI
19 P3[2] , AI
18 P3[0] , AI
17 XRES
4
I/O
5
I/O
P4[3]
,XIn, P2[3]
AI
AI, P4[3]
AI, P3[3]
AI, P3[1]
, P2[1]
6
I/O
P3[3]
QFN
(Top View)
7
I/O
P3[1]
8
IOHR
IOHR
IOHR
IOHR
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI CLK.
AI, I2C SCL, SPI SS,P1[7]
9
10
11
P1[1] ISSP CLK[27], I2C SCL, SPI
MOSI.
12
13
Power
VSS
Ground connection[30]
IOHR
I
P1[0] ISSP DATA[27], I2C SDA,
SPI CLK[28]
14
15
IOHR
IOHR
I
I
P1[2] Driven Shield Output (optional)
P1[4] Optional external clock input
(EXTCLK)
16
17
IOHR
I
P1[6]
Input
XRES Active high external reset with
internal pull-down[29]
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
P3[0]
P3[2]
I/O
P4[0]
I/O
P4[2]
I/O
P2[0]
I/O
P2[2] Driven Shield Output (optional)
I/O
P2[4] Driven Shield Output (optional)
IOH
IOH
IOH
IOH
P0[0] Driven Shield Output (optional)
P0[2] Driven Shield Output (optional)
P0[4]
P0[6]
Power
VDD
IOH
IOH
I
I
P0[7]
P0[3] Integrating input
Power
Power
VSS
VSS
Ground connection[30]
Centerpadmustbeconnectedto
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
25. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
26. 28 GPIOs = 25 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
27. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
28. Alternate SPI clock.
29. The internal pull down is 5KOhm.
30. All VSS pins should be brought out to one common GND plane.
Document Number: 001-69257 Rev. *P
Page 11 of 45
CY8C20xx7/S
[31]
48-pin QFN (31 Sensing Inputs)
Table 6. Pin Definitions – CY8C20637, CY8C20647/S, CY8C20667/S [32]
Figure 7. CY8C20637, CY8C20647/S, CY8C20667/S Device
1
2
3
4
5
6
7
8
NC
No connection
NC
AI ,P2[7]
NC
36
35
34
33
32
31
1
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
P2[4],
AI
Crystal output (XOut)
Crystal input (XIn)
AI , XOut,P2[5]
3
4
5
6
P2[2],
P2[0],
P4[2],
P4[0],
AI
AI
AI
AI
AI , XIn ,P2[3]
AI ,P2[1]
AI ,P4[3]
AI ,P4[1]
AI ,P3[7]
AI ,P3[5]
AI ,P3[3]
QFN
(Top View)
30
29
28
27
P3[6],
P3[4],
P3[2],
7
8
9
10
AI
AI
9
AI
AI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
],
P3[0
I/O
IOHR
IOHR
AI P
3[1]
XRES
26
25
11
12
2
I C SCL, SPI SS
AI ,I2 C SCL, SPI SS,P1[7]
P1[6],AI
2
I C SDA, SPI MISO
No connection
No connection
SPI CLK
NC
P1[3]
P1[1]
IOHR
IOHR
I
I
[33]
2
ISSP CLK , I C SCL, SPI MOSI
[36]
Power
V
Ground connection
SS
NC
NC
No connection
No connection
Supply voltage
Power
IOHR
IOHR
IOHR
V
DD
[33]
2
[34]
I
I
I
P1[0]
P1[2]
P1[4]
ISSP DATA , I C SDA, SPI CLK
Driven Shield Output (optional)
Optional external clock input
(EXTCLK)
25
26
IOHR
I
P1[6]
XRES
Input
Active high external reset with
internal pull-down
[35]
27
28
29
I/O
I/O
I/O
I
I
I
P3[0]
P3[2]
P3[4]
30
31
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
NC
P0[0]
P0[2]
P0[4]
40
41
42
43
44
45
46
47
48
CP
IOH
I
P0[6]
Power
V
Supply voltage
No connection
No connection
DD
NC
NC
P0[7]
NC
P0[3]
Driven Shield Output (optional)
Driven Shield Output (optional)
No connection
Driven Shield Output (optional)
Driven Shield Output (optional)
IOH
IOH
Power
IOH
I
I
No connection
Integrating input
Ground connection
Integrating input
[36
IOH
IOH
IOH
I
I
I
V
SS
P0[1]
I
Power
V
Center pad must be connected to ground
SS
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
31. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
32. 34 GPIOs = 31 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
33. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
34. Alternate SPI clock.
35. The internal pull down is 5KOhm.
36. All VSS pins should be brought out to one common GND plane.
Document Number: 001-69257 Rev. *P
Page 12 of 45
CY8C20xx7/S
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x37/47/67/S PSoC devices. For the latest electrical
specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 8. Voltage versus CPU Frequency
5.5 V
1.71 V
750kHz
3 MHz
24MHz
CPU Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Typ
Max
Units
Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
TSTG
Storage temperature
–55
+25
+125
°C
VDD
VIO
Supply voltage relative to VSS
DC input voltage
–
–0.5
VSS – 0.5
VSS – 0.5
–25
–
–
–
–
–
–
+6.0
VDD + 0.5
VDD + 0.5
+50
V
V
–
VIOZ
IMIO
ESD
LU
DC voltage applied to tristate
Maximum current into any port pin
Electro static discharge voltage
Latch up current
–
–
V
mA
V
Human body model ESD
In accordance with JESD78 standard
2000
–
–
200
mA
Operating Temperature
Table 8. Operating Temperature
Symbol
TA
Description
Ambient temperature
Conditions
Min
–40
0
Typ
Max
+85
70
Units
°C
–
–
–
TC
Commercial temperature range
°C
The temperature rise from ambient to junction
is package specific. See the Thermal Imped-
ances on page 30. The user must limit the
power consumption to comply with this
requirement.
TJ
Operational die temperature
–40
–
+100
°C
Document Number: 001-69257 Rev. *P
Page 13 of 45
CY8C20xx7/S
DC Chip-Level Specifications
Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 9. DC Chip-Level Specifications
Symbol
[37, 38, 39]
Description
Supply voltage
Conditions
See Table 14 on page 17.
Min
Typ
Max Units
VDD
1.71
–
5.50
V
Conditions are VDD 3.0 V, TA = 25 °C,
IDD24
IDD12
IDD6
Supply current, IMO = 24 MHz CPU = 24 MHz. CapSense running at 12 MHz,
no I/O sourcing current
–
–
–
2.88
1.71
1.16
4.00
mA
Conditions are VDD 3.0 V, TA = 25 °C,
Supply current, IMO = 12 MHz CPU = 12 MHz. CapSense running at
12 MHz, no I/O sourcing current
2.60
1.80
mA
mA
Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
Supply current, IMO = 6 MHz
[40, 41, 42, 43]
ISB0
Deep sleep current
VDD 3.0 V, TA = 25 °C, I/O regulator turned off
VDD 3.0 V, TA = 25 °C, I/O regulator turned off
–
–
0.10
1.07
1.1
A
A
Standby current with POR, LVD
and sleep timer
[40, 41, 42, 43]
ISB1
1.50
Standby current with I2C
enabled
Conditions are VDD = 3.3 V, TA = 25 °C and
CPU = 24 MHz
[40, 41, 42, 43]
ISBI2C
–
1.64
–
A
Notes
37. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
38. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a. Bring the device out of sleep before powering down.
b. Assure that VDD falls below 100 mV before powering back up.
c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced
registers, refer to the Technical Reference Manual. In deep sleep/standby sleep mode, additional low power voltage monitoring circuitry allows VDD brown out
conditions to be detected and resets the device when VDD goes lower than 1.1 V at edge rates slower than 1 V/ms.
39. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can
be between 1.8 V and 5.5 V.
40. Errata: When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is used to wake the device from
sleep, the interrupt service routine (ISR) may be executed twice. For more information, see the “Errata” on page 37.
41. Errata: When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may be missed, and the
corresponding GPIO ISR not run. For more information, see the “Errata” on page 37.
42. Errata: If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be missed. For more information,
see the “Errata” on page 37.
43. Errata: Device wakes up from sleep when an analog interrupt is trigger. For more information, see the “Errata” on page 37.
Document Number: 001-69257 Rev. *P
Page 14 of 45
CY8C20xx7/S
DC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C TA 85 °C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 10. 3.0 V to 5.5 V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
RPU
Pull-up resistor
–
4
5.60
8
k
High output voltage
Port 2 or 3 pins
IOH < 10 A, maximum of 10 mA source
VOH1
VOH2
VDD – 0.20
VDD – 0.90
–
–
–
–
V
V
current in all I/Os
High output voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source
current in all I/Os
High output voltage
Port 0 or 1 pins with LDO regulator Disabled
for port 1
I
OH < 10 A, maximum of 10 mA source
VOH3
VOH4
VOH5
VOH6
V
DD – 0.20
–
–
–
–
V
V
V
V
current in all I/Os
High output voltage
Port 0 or 1 pins with LDO regulator Disabled
for port 1
I
OH = 5 mA, maximum of 20 mA source
VDD – 0.90
2.85
current in all I/Os
High output voltage
Port 1 Pins with LDO Regulator Enabled for
3 V out
I
OH < 10 A, VDD > 3.1 V, maximum of
3.00
–
3.30
–
4 I/Os all sourcing 5 mA
High output voltage
Port 1 pins with LDO regulator enabled for 3
V out
I
OH = 5 mA, VDD > 3.1 V, maximum of
2.20
20 mA source current in all I/Os
High output voltage
Port 1 pins with LDO enabled for 2.5 V out 20 mA source current in all I/Os
IOH < 10 A, VDD > 2.7 V, maximum of
VOH7
VOH8
VOH9
VOH10
2.35
1.90
1.60
1.20
2.50
–
2.75
–
V
V
V
V
High output voltage
Port 1 pins with LDO enabled for 2.5 V out 20 mA source current in all I/Os
IOH = 2 mA, VDD > 2.7 V, maximum of
High output voltage IOH < 10 A, VDD > 2.7 V, maximum of
Port 1 pins with LDO enabled for 1.8 V out 20 mA source current in all I/Os
High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of
Port 1 pins with LDO enabled for 1.8 V out 20 mA source current in all I/Os
OL = 25 mA, VDD > 3.3 V, maximum of
1.80
–
2.10
–
I
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mAsink
current on odd port pins (for example,
P0[3] and P1[5])
VOL
Low output voltage
–
–
0.75
V
VIL
VIH
VH
Input low voltage
–
–
–
–
0.80
V
V
Input high voltage
–
VDD × 0.65
VDD + 0.7
Input hysteresis voltage
Input leakage (Absolute Value)
Pin capacitance
–
–
–
80
–
1
7
mV
A
pF
IIL
–
0.001
1.70
CPIN
Package and pin dependent Temp = 25 °C
0.50
Input Low Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low
VILLVT3.3
VIHLVT3.3
VILLVT5.5
VIHLVT5.5
0.8
1.4
0.8
1.7
V
–
V
–
–
–
–
–
–
V
–
set, Enable for Port1 [44]
threshold voltage of Port1 input
Input High Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low
set, Enable for Port1 threshold voltage of Port1 input
Input Low Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low
set, Enable for Port1 threshold voltage of Port1 input
Input High Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low
set, Enable for Port1 threshold voltage of Port1 input
V
Note
44. Errata: Pull-up resistor on port1 pins cannot be connected to a voltage that is greater than 0.7 V higher than CY8C20xx7/S VDD. For more information see item #7
in “Errata” on page 37.
Document Number: 001-69257 Rev. *P
Page 15 of 45
CY8C20xx7/S
Table 11. 2.4 V to 3.0 V DC GPIO Specifications
Symbol
Description
Pull-up resistor
Conditions
Min
Typ
Max
Units
RPU
–
4
5.60
8
k
High output voltage
Port 2 or 3 pins
IOH < 10 A, maximum of 10 mAsource
VOH1
VOH2
VDD - 0.20
VDD - 0.40
–
–
–
–
V
V
current in all I/Os
High output voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
source current in all I/Os
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
I
OH < 10 A, maximum of 10 mAsource
VOH3
V
DD - 0.20
–
–
–
–
V
V
V
V
current in all I/Os
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
I
OH = 2 mA, maximum of 10 mAsource
VOH4
VDD - 0.50
1.50
current in all I/Os
High output voltage
Port 1 pins with LDO enabled for 1.8 V
out
I
OH < 10 A, VDD > 2.4 V, maximum of
VOH5A
1.80
–
2.10
–
20 mA source current in all I/Os
High output voltage
Port 1 pins with LDO enabled for 1.8 V
out
I
OH = 1 mA, VDD > 2.4 V, maximum of
VOH6A
1.20
20 mA source current in all I/Os
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
VOL
Low output voltage
–
–
0.75
V
VIL
VIH
VH
IIL
Input low voltage
–
–
–
–
–
–
–
0.72
VDD + 0.7
–
V
V
Input high voltage
VDD × 0.65
Input hysteresis voltage
Input leakage (absolute value)
–
–
80
1
mV
nA
1000
Package and pin dependent
Temp = 25 C
CPIN
Capacitive load on pins
0.50
0.7
1.70
V
7
–
–
pF
V
Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low
threshold voltage of Port1 input
VILLVT2.5
VIHLVT2.5
Input High Voltage with low threshold Bit3 of IO_CFG1 set to enable low
1.2
enable set, Enable for Port1
threshold voltage of Port1 input
Table 12. 1.71 V to 2.4 V DC GPIO Specifications
Symbol
Description
Pull-up resistor
Conditions
Min
Typ
Max
Units
RPU
–
4
5.60
8
k
High output voltage
Port 2 or 3 pins
IOH = 10 A, maximum of 10 mA
VOH1
VOH2
VDD – 0.20
VDD – 0.50
–
–
–
–
V
V
source current in all I/Os
High output voltage
Port 2 or 3 pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 100 A, maximum of 10 mA
VOH3
V
DD – 0.20
DD – 0.50
–
–
–
–
V
V
source current in all I/Os
High output voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
I
OH = 2 mA, maximum of 10 mAsource
current in all I/Os
VOH4
V
Document Number: 001-69257 Rev. *P
Page 16 of 45
CY8C20xx7/S
Table 12. 1.71 V to 2.4 V DC GPIO Specifications (continued)
Symbol
Description
Conditions
Min
Typ
Max
Units
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
VOL
Low output voltage
–
–
0.40
V
VIL
VIH
VH
IIL
Input low voltage
–
–
–
–
–
–
–
0.30 × VDD
V
V
Input high voltage
0.65 × VDD
–
–
Input hysteresis voltage
Input leakage (absolute value)
–
–
80
1
mV
nA
1000
Package and pin dependent
temp = 25 C
CPIN
Capacitive load on pins
0.50
1.70
7
pF
Table 13. GPIO Current Sink and Source Specifications
Supply
Voltage
Port 0/1 per I/O
(max)
Port 2/3/4 per Total Current Even Total Current Odd
Mode
Units
I/O (max)
Pins (max)
Pins (max)
Sink
Source
Sink
5
2
5
20
30
mA
mA
mA
mA
mA
mA
1.71–2.4
2.4–3.0
3.0–5.0
0.5
10
0.2
25
1
10[45]
10[45]
20[45]
10
2
30
60
30
60
Source
Sink
25
5
Source
DC Analog Mux Bus Specifications
Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. DC Analog Mux Bus Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Switch resistance to common analog
bus
RSW
–
–
–
800
Resistance of initialization switch to
VSS
RGND
–
–
–
800
The maximum pin voltage for measuring RSW and RGND is 1.8 V
DC Low Power Comparator Specifications
Table 15 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 15. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Low power comparator (LPC) common
mode
VLPC
Maximum voltage limited to VDD
0.2
–
1.8
V
ILPC
LPC supply current
LPC voltage offset
–
–
–
–
10
80
30
A
VOSLPC
2.5
mV
Note
45. Total current (odd + even ports)
Document Number: 001-69257 Rev. *P
Page 17 of 45
CY8C20xx7/S
Comparator User Module Electrical Specifications
Table 16 lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire
device voltage and temperature operating range: –40 °C TA 85 °C, 1.71 V VDD 5.5 V.
Table 16. Comparator User Module Electrical Specifications
Symbol
TCOMP
Description
Conditions
Min
–
Typ
70
Max
100
30
Units
ns
Comparator response time 50 mV overdrive
Offset
–
–
Valid from 0.2 V to 1.5 V
–
2.5
mV
Average DC current, 50 mV
overdrive
Current
–
20
80
µA
Supply voltage > 2 V
Supply voltage < 2 V
–
Power supply rejection ratio
–
–
80
40
–
–
dB
dB
V
PSRR
Power supply rejection ratio
–
Input range
0.2
1.5
ADC Electrical Specifications
Table 17. ADC User Module Electrical Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Input
VIN
Input voltage range
Input capacitance
–
–
0
–
–
–
VREFADC
5
V
CIIN
pF
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution
1/(500fF × 1/(400fF × 1/(300fF ×
data clock) data clock) data clock)
RIN
Input resistance
Reference
VREFADC
ADC reference voltage
–
1.14
2.25
–
–
1.26
6
V
Conversion Rate
Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications on page 21 for
accuracy
FCLK
Data clock
MHz
Data clock set to 6 MHz.
sample rate = 0.001/
(2^Resolution/Data Clock)
S8
8-bit sample rate
10-bit sample rate
–
–
23.43
5.85
–
–
ksps
ksps
Data clock set to 6 MHz.
sample rate = 0.001/
S10
(2^resolution/data clock)
DC Accuracy
RES
Resolution
Can be set to 8, 9, or 10 bit
8
–1
–2
0
–
–
10
+2
bits
LSB
DNL
Differential nonlinearity
Integral nonlinearity
–
–
INL
–
+2
LSB
8-bit resolution
10-bit resolution
For any resolution
3.20
12.80
–
19.20
76.80
+5
LSB
EOFFSET
Offset error
Gain error
0
LSB
EGAIN
Power
IADC
–5
%FSR
Operating current
–
–
–
–
2.10
24
2.60
–
mA
dB
dB
PSRR (VDD > 3.0 V)
PSRR (VDD < 3.0 V)
PSRR
Power supply rejection ratio
30
–
Document Number: 001-69257 Rev. *P
Page 18 of 45
CY8C20xx7/S
DC POR and LVD Specifications
Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. DC POR and LVD Specifications
Symbol
VPOR0
Description
Conditions
Min
1.61
–
Typ
1.66
2.36
2.60
2.82
2.45
2.71
2.92
3.02
3.13
1.90
1.80
4.73
Max
1.71
2.41
2.66
2.95
2.51
2.78
2.99
3.09
3.20
2.32
1.84
4.83
Units
V
1.66 V selected in PSoC Designer
2.36 V selected in PSoC Designer
2.60 V selected in PSoC Designer
2.82 V selected in PSoC Designer
2.45 V selected in PSoC Designer
2.71 V selected in PSoC Designer
2.92 V selected in PSoC Designer
3.02 V selected in PSoC Designer
3.13 V selected in PSoC Designer
1.90 V selected in PSoC Designer
1.80 V selected in PSoC Designer
4.73 V selected in PSoC Designer
V
DD must be greater thanor equal to 1.71 V
during startup, reset from the XRES pin, or
reset from watchdog.
VPOR1
VPOR2
VPOR3
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
V
–
V
–
V
2.40
2.64[46]
2.85[47]
2.95[48]
3.06
1.84
1.75[49]
4.62
V
V
V
V
–
V
V
V
V
DC Programming Specifications
Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC Programming Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Supply voltage for flash write
operations
VDDIWRITE
–
1.71
–
5.25
V
Supply current during
programming or verify
IDDP
VILP
VIHP
–
–
–
5
–
–
25
VIL
–
mA
V
Input low voltage during
programming or verify
See appropriate “DC GPIO Specifica-
tions” on page 15
Input high voltage during
programming or verify
See appropriate “DC GPIO Specifica-
tions” on page 15
VIH
V
Input current when Applying VILP
to P1[0] or P1[1] during
IILP
Driving internal pull-down resistor
–
–
0.2
mA
programming or verify
Input current when applying VIHP
to P1[0] or P1[1] during
programming or verify
IIHP
Driving internal pull-down resistor
–
–
–
–
–
–
1.5
VSS + 0.75
VDD
mA
V
Output low voltage during
programming or verify
VOLP
VOHP
See appropriate “DC GPIO Specifica-
tions” on page 15. For VDD > 3V use VOH4
in Table 10 on page 15.
Output high voltage during
programming or verify
VOH
V
FlashENPB Flash write endurance
Erase/write cycles per block
50,000
20
–
–
–
–
–
Following maximum Flash write cycles;
ambient temperature of 55 °C
FlashDR
Flash data retention
Years
Notes
46. Always greater than 50 mV above VPPOR1 voltage for falling supply.
47. Always greater than 50 mV above VPPOR2 voltage for falling supply.
48. Always greater than 50 mV above VPPOR3 voltage for falling supply.
49. Always greater than 50 mV above VPPOR0 voltage for falling supply.
Document Number: 001-69257 Rev. *P
Page 19 of 45
CY8C20xx7/S
2
DC I C Specifications
Table 20 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C
TA 85 °C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical parameters apply
to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 20. DC I2C Specifications[50]
Symbol
Description
Conditions
3.1 V ≤ VDD ≤ 5.5 V
Min
–
Typ
–
Max
Units
0.25 × VDD
0.3 × VDD
0.3 × VDD
V
V
V
VILI2C
Input low level
2.5 V ≤ VDD ≤ 3.0 V
1.71 V ≤ VDD ≤ 2.4 V
–
–
–
–
VDD
+
VIHI2C
Input high level
1.71 V ≤ VDD ≤ 5.5 V
0.65 × VDD
–
V
0.7 V[51]
Shield Driver DC Specifications
Table 21 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C
TA 85 °C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical parameters apply
to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 21. Shield Driver DC Specifications
Symbol
VRef
VRefHi
Description
Reference buffer output
Reference buffer output
Conditions
1.7 V ≤ VDD ≤ 5.5 V
1.7 V ≤ VDD ≤ 5.5 V
Min
Typ
–
Max
1.106
1.296
Units
0.942
1.104
V
V
–
DC IDAC Specifications
Table 22 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. DC IDAC Specifications (8-bit IDAC)
Symbol
IDAC_DNL
IDAC_DNL
Description
Differential nonlinearity
Integral nonlinearity
Range = 4x
Min
–1
Typ
–
Max
1
Units
LSB
LSB
µA
Notes
–
–
–2
–
2
138
138
–
169
169
DAC setting = 127 dec
DAC setting = 64 dec
IDAC_Current
Range = 8x
–
µA
Table 23. DC IDAC Specifications (7-bit IDAC)
Symbol
IDAC_DNL
IDAC_DNL
Description
Differential nonlinearity
Integral nonlinearity
Range = 4x
Min
–1
Typ
–
Max
1
Units
LSB
LSB
µA
Notes
–
–
–2
–
2
137
138
–
168
169
DAC setting = 127 dec
DAC setting = 64 dec
IDAC_Current
Range = 8x
–
µA
Notes
50. Errata: Pull-up resistors on I2C interface cannot be connected to a supply voltage that is more than 0.7 V higher than the CY8C20xx7/S power supply. For more
information see item #6 in the “Errata” on page 37.
51. Errata: For more information see item #6 in the “Errata” on page 37.
Document Number: 001-69257 Rev. *P
Page 20 of 45
CY8C20xx7/S
AC Chip-Level Specifications
Table 24 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 24. AC Chip-Level Specifications
Symbol
FIMO24
Description
IMO frequency at 24 MHz Setting
IMO frequency at 12 MHz setting
IMO frequency at 6 MHz setting
CPU frequency
Conditions
Min
22.8
11.4
5.7
0.75
15
–
Typ
24
12
6.0
–
Max
25.2
12.6
6.3
25.20
50
Units
MHz
MHz
MHz
MHz
kHz
kHz
%
–
FIMO12
FIMO6
FCPU
–
–
–
F32K1
ILO frequency
–
32
32
50
50
–
F32K_U
DCIMO
DCILO
ILO untrimmed frequency
Duty cycle of IMO
–
–
–
40
40
–
60
ILO duty cycle
–
VDD slew rate during power-up
60
%
SRPOWER_UP Power supply slew rate
250
–
V/ms
ms
tXRST
External reset pulse width at power-up
After supply voltage is valid
1
–
tXRST2
External reset pulse width after power-up[52] Applies after part has booted
10
–
–
–
s
6 MHz IMO cycle-to-cycle jitter (RMS)
–
0.7
6.7
ns
6 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
–
–
4.3
29.3
ns
6 MHz IMO period jitter (RMS)
–
–
–
–
0.7
0.5
3.3
5.2
ns
ns
12 MHz IMO cycle-to-cycle jitter (RMS)
12 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
[53]
tJIT_IMO
–
––
2.3
5.6
ns
12 MHz IMO period jitter (RMS)
–
–
–
–
0.4
1.0
2.6
8.7
ns
ns
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
–
–
–
–
1.4
0.6
6.0
4.0
ns
ns
24 MHz IMO period jitter (RMS)
Note
52. The minimum required XRES pulse length is longer when programming the device (see Table 28 on page 23).
53. See the Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-69257 Rev. *P
Page 21 of 45
CY8C20xx7/S
AC General Purpose I/O Specifications
Table 25 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 25. AC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
6 MHz for
1.71 V <VDD < 2.40 V
12 MHz for
2.40 V < VDD< 5.50 V
Units
0
–
MHz
FGPIO
GPIO operating frequency
Normal strong mode Port 0, 1
0
–
–
–
–
–
–
–
MHz
ns
Rise time, strong mode, Cload = 50 pF
Ports 2 or 3
tRISE23
tRISE23L
tRISE01
tRISE01L
tFALL
VDD = 3.0 to 3.6 V, 10% to 90%
15
15
10
10
10
10
80
80
50
80
50
70
Rise time, strong mode low supply,
Cload = 50 pF, Ports 2 or 3
V
DD = 1.71 to 3.0 V, 10% to 90%
ns
Rise time, strong mode, Cload = 50 pF VDD = 3.0 to 3.6 V, 10% to 90%
ns
Ports 0 or 1
LDO enabled or disabled
Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
VDD = 1.71 to 3.0 V, 10% to 90%
LDO enabled or disabled
ns
Fall time, strong mode, Cload = 50 pF
all ports
V
DD = 3.0 to 3.6 V, 10% to 90%
VDD = 1.71 to 3.0 V, 10% to 90%
Figure 9. GPIO Timing Diagram
ns
Fall time, strong mode low supply,
Cload = 50 pF, all ports
tFALLL
ns
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TRise23L
TRise01L
TFall
TFallL
AC Comparator Specifications
Table 26 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 26. AC Low Power Comparator Specifications
Symbol
tLPC
Description
Conditions
Min
Typ
Max
Units
Comparator response time,
50 mV overdrive
50 mV overdrive does not include
offset voltage.
–
–
100
ns
AC External Clock Specifications
Table 27 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC External Clock Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Frequency (external oscillator
frequency)
–
0.75
–
25.20
MHz
High period
–
–
–
20.60
20.60
150
–
–
–
5300
ns
ns
s
FOSCEXT
Low period
–
–
Power-up IMO to switch
Document Number: 001-69257 Rev. *P
Page 22 of 45
CY8C20xx7/S
AC Programming Specifications
Figure 10. AC Waveform
SCLK (P1[1])
TRSCLK
TFSCLK
SDATA (P1[0])
TSSCLK
THSCLK
TDSCLK
Table 28 lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC Programming Specifications
Symbol
tRSCLK
Description
Rise time of SCLK
Conditions
Min
1
Typ
–
Max
20
20
–
Units
ns
–
–
–
–
–
–
–
tFSCLK
tSSCLK
tHSCLK
FSCLK
Fall time of SCLK
1
–
ns
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
tERASEB
tWRITE
tDSCLK
tDSCLK3
tDSCLK2
Flash erase time (block)
–
–
18
25
60
85
130
Flash block write time
–
–
Data out delay from falling edge of SCLK 3.6 VDD
Data out delay from falling edge of SCLK 3.0 VDD 3.6
Data out delay from falling edge of SCLK 1.71 VDD 3.0
–
–
–
–
ns
–
–
ns
Required to enter programming
mode when coming out of sleep
tXRST3
External reset pulse width after power-up
300
–
–
s
tXRES
XRES pulse length
–
–
–
–
300
0.1
–
–
–
–
–
1
s
ms
ms
ms
[54]
[54]
tVDDWAIT
VDD stable to wait-and-poll hold off
VDD stable to XRES assertion delay
SDAT high pulse time
tVDDXRES
tPOLL
14.27
0.01
–
200
“Key window” time after a VDD ramp
acquire event, based on 256 ILO clocks.
[54]
tACQ
–
–
3.20
98
–
–
19.60
615
ms
“Key window” time after an XRES event,
based on 8 ILO clocks
[54]
tXRESINI
s
Note
54. Valid from 5 to 50 °C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67,
CY8C20X47, CY8C20X37, Programming Spec for more details.
Document Number: 001-69257 Rev. *P
Page 23 of 45
CY8C20xx7/S
2
AC I C Specifications
Table 29 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC Characteristics of the I2C SDA and SCL Pins
Standard
Mode
Fast Mode
Symbol
fSCL
Description
Units
Min
Max
Min
Max
SCL clock frequency
0
100
0
400 kHz
Hold time (repeated) START condition. After this period, the first clock pulse is
generated
tHD;STA
4.0
–
0.6
–
µs
tLOW
LOW period of the SCL clock
4.7
4.0
4.7
20
–
–
1.3
0.6
–
–
µs
µs
µs
µs
ns
µs
µs
ns
tHIGH
HIGH Period of the SCL clock
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Setup time for a repeated START condition
Data hold time
–
0.6
–
[55]
3.45
–
20
100[56]
0.90
–
Data setup time
250
4.0
4.7
–
Setup time for STOP condition
–
0.6
–
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
–
1.3
–
tSP
–
0
50
Figure 11. Definition for Timing for Fast/Standard Mode on the I2C Bus
Notes
55. Errata: To wake up from sleep using I2C hardware address match event, I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL. For
more information see item #5 in the “Errata” on page 37.
56. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-69257 Rev. *P
Page 24 of 45
CY8C20xx7/S
Table 30. SPI Master AC Specifications
Symbol Description
FSCLK
Conditions
VDD 2.4 V
DD < 2.4 V
Min
Typ
Max
Units
–
–
–
–
6
3
MHz
MHz
SCLK clock frequency
SCLK duty cycle
V
DC
–
–
50
–
%
VDD 2.4 V
VDD < 2.4 V
60
100
–
–
–
–
ns
ns
tSETUP
MISO to SCLK setup time
tHOLD
SCLK to MISO hold time
SCLK to MOSI valid time
MOSI high time
–
–
–
40
–
–
–
–
–
40
–
ns
ns
ns
tOUT_VAL
tOUT_H
40
Figure 12. SPI Master Mode 0 and 2
SPI Master, modes 0 and 2
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TSETUP
THOLD
MISO
(input)
LSB
MSB
TOUT_SU
TOUT_H
MOSI
(output)
Figure 13. SPI Master Mode 1 and 3
SPI Master, modes 1 and 3
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TSETUP
THOLD
MISO
(input)
MSB
LSB
TOUT_SU
TOUT_H
MOSI
(output)
LSB
MSB
Document Number: 001-69257 Rev. *P
Page 25 of 45
CY8C20xx7/S
Table 31. SPI Slave AC Specifications
Symbol Description
FSCLK
Conditions
Min
Typ
–
Max
4
Units
MHz
ns
SCLK clock frequency
SCLK low time
–
–
–
–
–
–
–
–
–
–
–
tLOW
42
–
–
tHIGH
SCLK high time
42
–
–
ns
tSETUP
tHOLD
MOSI to SCLK setup time
SCLK to MOSI hold time
SS high to MISO valid
SCLK to MISO valid
SS high time
30
–
–
ns
50
–
–
ns
tSS_MISO
tSCLK_MISO
tSS_HIGH
tSS_CLK
tCLK_SS
–
–
–
153
125
–
ns
–
ns
50
–
ns
Time from SS low to first SCLK
Time from last SCLK to SS high
2/SCLK
2/SCLK
–
–
ns
–
–
ns
Figure 14. SPI Slave Mode 0 and 2
SPI Slave, modes 0 and 2
TSS_HIGH
TCLK_SS
TSS_CLK
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TOUT_H
TSS_MISO
MISO
(output)
TSETUP
THOLD
MOSI
(input)
LSB
MSB
Figure 15. SPI Slave Mode 1 and 3
SPI Slave, modes 1 and 3
TSS_CLK
TCLK_SS
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TOUT_H
TSCLK_MISO
TSS_MISO
MISO
(output)
MSB
LSB
TSETUP
THOLD
MOSI
(input)
MSB
LSB
Document Number: 001-69257 Rev. *P
Page 26 of 45
CY8C20xx7/S
Packaging Information
This section illustrates the packaging specifications for the CY8C20x37/47/67 PSoC device, along with the thermal impedances for
each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 16. 16-pin (150 Mil) SOIC
51-85068 *E
Figure 17. 16-pin Chip-On-Lead (3 × 3 × 0.6 mm) (Sawn) Package Outline, 001-09116
001-09116 *J
Document Number: 001-69257 Rev. *P
Page 27 of 45
CY8C20xx7/S
Figure 18. 24-Pin (4 × 4 × 0.6 mm) QFN
001-13937 *F
Figure 19. 32-Pin (5 × 5 × 0.6 mm) QFN
001-42168 *E
Document Number: 001-69257 Rev. *P
Page 28 of 45
CY8C20xx7/S
Figure 20. 48-Pin (6 × 6 × 0.6 mm) QFN
001-57280 *E
Important Notes
■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■ Pinned vias for thermal conduction are not required for the low power PSoC device.
Document Number: 001-69257 Rev. *P
Page 29 of 45
CY8C20xx7/S
Thermal Impedances
Table 32. Thermal Impedances per Package
[57]
Package
Typical JA
95 C/W
16-pin SOIC
33 C/W
21 C/W
20 C/W
18 C/W
54 C/W
16-pin QFN
24-pin QFN[58]
32-pin QFN[58]
48-pin QFN[58]
30-ball WLCSP
Capacitance on Crystal Pins
Table 33. Typical Package Capacitance on Crystal Pins
Package
32-Pin QFN
48-Pin QFN
Package Capacitance
3.2 pF
3.3 pF
Solder Reflow Peak Temperature
Table 34 shows the solder reflow temperature limits that must not be exceeded.
Table 34. Solder Reflow Peak Temperature
Package
16-pin SOIC
16-pin QFN
24-pin QFN
32-pin QFN
48-pin QFN
30-ball WLCSP
Maximum Time above TC – 5 C
Maximum Peak Temperature (TC)
260 C
260 C
260 C
260 C
260 C
260 C
30 seconds
30 seconds
30 seconds
30 seconds
30 seconds
30 seconds
Notes
57. TJ = TA + Power ×
.
JA
58. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
Document Number: 001-69257 Rev. *P
Page 30 of 45
CY8C20xx7/S
PSoC Programmer
Development Tool Selection
Software
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer. PSoC
Programmer software is compatible with both PSoC ICE Cube
in-circuit Emulator and PSoC MiniProg. PSoC programmer is
available free of cost at
PSoC Designer™
At the core of the PSoC development software suite is
PSoC Designer, used to generate PSoC firmware applications.
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
http://www.cypress.com/psocprogrammer.
Development Kits
All development kits are sold at the Cypress Online Store.
This system provides design database management by project,
in-system programming support, and built-in support for third-
party assemblers and C compilers. PSoC Designer also
supports C language compilers developed specifically for the
devices in the PSoC family. PSoC Designer is available free of
charge at
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
http://www.cypress.com/psocdesigner and includes a free C
compiler.
The CY3210-MiniProg1 kit allows you to program PSoC devices
through the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
through a provided USB 2.0 cable. The kit includes:
PSoC Designer Software Subsystems
You choose a base device to work with and then select different
onboard analog and digital components called user modules that
use the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters. You configure the user modules
for your chosen application and connect them to each other and
to the proper pins. Then you generate your project. This
prepopulates your project with APIs and libraries that you can
use to program your application.
■ MiniProg programming unit
■ MiniEval socket programming and evaluation board
■ 28-pin CY8C29466-24PXI PDIP PSoC device sample
■ 28-pin CY8C27443-24PXI PDIP PSoC device sample
■ PSoC Designer software CD
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration allows for changing configurations at run time.
Code Generation Tools PSoC Designer supports multiple third-
party C compilers and assemblers. The code generation tools
work seamlessly within the PSoC Designer interface and have
been tested with a full range of debugging tools. The choice is
yours.
■ Getting Started guide
■ USB 2.0 cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
■ Evaluation board with LCD module
■ MiniProg programming unit
■ Two 28-pin CY8C29466-24PXI PDIP PSoC device samples
■ PSoC Designer software CD
■ Getting Started guide
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■ USB 2.0 cable
Document Number: 001-69257 Rev. *P
Page 31 of 45
CY8C20xx7/S
CY3207ISSP In-System Serial Programmer (ISSP)
Device Programmers
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
All device programmers are purchased from the Cypress Online
Store.
CY3216 Modular Programmer
Note CY3207ISSP needs special software and is not compatible
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
with PSoC Programmer. The kit includes:
■ CY3207 programmer unit
■ PSoC ISSP software CD
■ Modular programmer base
■ Three programming module cards
■ MiniProg programming unit
■ PSoC Designer software CD
■ Getting Started guide
■ 110 ~ 240 V power supply, Euro-Plug adapter
■ USB 2.0 cable
■ USB 2.0 cable
Third Party Tools
Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and
production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Document Number: 001-69257 Rev. *P
Page 32 of 45
CY8C20xx7/S
Ordering Information
Table 35 lists the CY8C20x37/47/67/S PSoC devices’ key package features and ordering codes.
Table 35. PSoC Device Key Features and Ordering Information
Flash SRAM CapSense Digital I/O
XRES
Pin
Analog
Ordering Code
Package
ADC
Inputs [59]
(Bytes) (Bytes) Sensors
Pins
13
13
13
13
13
13
19
19
19
19
19
19
28
28
28
28
28
28
28
28
28
28
34
34
34
34
34
34
34
34
34
34
CY8C20237-24SXI
16-pin SOIC
8 K
16 K
8 K
1 K
2 K
1 K
1 K
2 K
2 K
1 K
1 K
2 K
2 K
2 K
2 K
1 K
1 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
1 K
1 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
2 K
10
10
10
10
10
10
16
16
16
16
16
16
25
25
25
25
25
25
25
25
25
25
31
31
31
31
31
31
31
31
31
31
13
13
13
13
13
13
19
19
19
19
19
19
28
28
28
28
28
28
28
28
28
28
34
34
34
34
34
34
34
34
34
34
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
Yes Yes
CY8C20247S-24SXI
CY8C20237-24LKXI
CY8C20237-24LKXIT
CY8C20247S-24LKXI
CY8C20247S-24LKXIT
CY8C20337-24LQXI
CY8C20337-24LQXIT
CY8C20347-24LQXI
CY8C20347-24LQXIT
CY8C20347S-24LQXI
CY8C20347S-24LQXIT
CY8C20437-24LQXI
CY8C20437-24LQXIT
CY8C20447-24LQXI
CY8C20447-24LQXIT
CY8C20447S-24LQXI
CY8C20447S-24LQXIT
CY8C20467-24LQXI
CY8C20467-24LQXIT
CY8C20467S-24LQXI
CY8C20467S-24LQXIT
CY8C20637-24LQXI
CY8C20637-24LQXIT
CY8C20647-24LQXI
CY8C20647-24LQXIT
CY8C20647S-24LQXI
CY8C20647S-24LQXIT
CY8C20667-24LQXI
CY8C20667-24LQXIT
CY8C20667S-24LQXI
CY8C20667S-24LQXIT
16-pin SOIC
16-pin QFN
16-pin QFN (Tape and Reel)
16-pin QFN
8 K
16 K
16 K
8 K
16-pin QFN (Tape and Reel)
24-pin QFN
24-pin QFN (Tape and Reel)
24-pin QFN
8 K
16 K
16 K
16 K
16 K
8 K
24-pin QFN (Tape and Reel)
24-pin QFN
24-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
32-pin QFN
8 K
16 K
16 K
16 K
16 K
32 K
32 K
32 K
32 K
8 K
32-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
32-pin QFN
32-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
48-pin QFN
8 K
16 K
16 K
16 K
16 K
32 K
32 K
32 K
32 K
48-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
48-pin QFN
48-pin QFN (Tape and Reel)
Note
59. Dual-function Digital I/O Pins also connect to the common analog mux.
Document Number: 001-69257 Rev. *P
Page 33 of 45
CY8C20xx7/S
Table 35. PSoC Device Key Features and Ordering Information (continued)
Flash SRAM CapSense Digital I/O
XRES
Pin
Analog
Ordering Code
Package
ADC
Inputs [59]
(Bytes) (Bytes) Sensors
Pins
CY8C20767-24FDXC
CY8C20767-24FDXCT
30-pin WLCSP
30-pin WLCSP (Tape and Reel)
32 K
32 K
2 K
2 K
24
24
27
27
27
Yes Yes
Yes Yes
27
Ordering Code Definitions
-
CY 8 C 20 XX7 X 24 XX
(T)
X
X
Tape and reel
Temperature range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Types: XX = S, LK, LQ, or FD
S = 16-pin SOIC
LK = 16-pin QFN (no center pad)
LQ = 24-pin QFN, 32-pin QFN, 48-pin QFN
FD = 30-ball WLCSP
Speed grade = 24 MHz
S = SmartSense™ Auto-tuning Enabled
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-69257 Rev. *P
Page 34 of 45
CY8C20xx7/S
Acronyms
The following table lists the acronyms that are used in this
document.
Reference Documents
■ Technical reference manual for CY20xx7 devices
■ In-system Serial Programming (ISSP) protocol for 20xx7
■ Host Sourced Serial Programming for 20xx7 devices
Table 36. Acronyms Used in this Document
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
complementary metal oxide semiconductor
central processing unit
digital-to-analog converter
direct current
Document Conventions
CMOS
CPU
DAC
DC
Units of Measure
Table 37 lists all the abbreviations used to measure the PSoC
devices.
Table 37. Units of Measure
ESD
FSR
GPIO
I2C
electrostatic discharge
full scale range
Symbol
°C
Unit of Measure
degree Celsius
decibel
general purpose input/output
inter-integrated circuit
in-circuit emulator
dB
kHz
ksps
k
MHz
A
s
kilohertz
ICE
kilo samples per second
kilohm
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
I/O
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
millivolt
ISSP
LCD
LDO
LED
LPC
LSB
LVD
in-system serial programming
liquid crystal display
low dropout (regulator)
light-emitting diode
mA
mm
ms
mV
nA
ns
low power comparator
least-significant bit
low voltage detect
nanoampere
nanosecond
ohm
MCU
MIPS
MISO
MOSI
MSB
OCD
PCB
POR
PSRR
micro-controller unit
million instructions per second
master in slave out
%
percent
master out slave in
pF
picofarad
volt
most-significant bit
V
on-chip debug
W
watt
printed circuit board
power on reset
power supply rejection ratio
PWRSYS power system
PSoC
QFN
programmable system-on-chip
quad flat no-lead
SCLK
SDA
serial I2C clock
serial I2C data
SDATA
SOIC
SPI
serial ISSP data
small outline integrated circuit
serial peripheral interface
static random access memory
slave select
SRAM
SS
USB
universal serial bus
wafer level chip scale package
WLCSP
Document Number: 001-69257 Rev. *P
Page 35 of 45
CY8C20xx7/S
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Glossary
Crosspoint connection
Differential non linearity
Connection between any GPIO combination via analog multiplexer bus.
Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the worst case deviation from the
ideal 1 LSB step.
Hold time
Hold time is the time following a clock event during which the data input to a latch or flip-
flop must remain stable in order to guarantee that the latched data is correct.
I2C
It is a serial multi-master bus used to connect low speed peripherals to MCU.
Integral nonlinearity
It is a term describing the maximum deviation between the ideal output of a DAC/ADC and
the actual output level.
Latch-up current
Current at which the latch-up test is conducted according to JESD78 standard (at 125
degree Celsius)
Power supply rejection ratio (PSRR)
The PSRR is defined as the ratio of the change in supply voltage to the corresponding
change in output voltage of the device.
Scan
The conversion of all sensor capacitances to digital values.
Setup time
Period required to prepare a device, machine, process, or system for it to be ready to
function.
Signal-to-noise ratio
SPI
The ratio between a capacitive finger signal and system noise.
Serial peripheral interface is a synchronous serial data link standard.
Document Number: 001-69257 Rev. *P
Page 36 of 45
CY8C20xx7/S
Errata
This section describes the errata for the CY8C20xx7/S family. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
CY8C20xx7/S Qualification Status
Product Status: Production released.
CY8C20xx7/S Errata Summary
The following Errata items apply to the CY8C20xx7/S datasheet 001-69257.
1. DoubleTimer0 ISR
■Problem Definition
When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt
is used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode.
■Scope of Impact
The ISR may be executed twice.
■Workaround
In the ISR, firmware should clear the one-shot bit with a statement such as “and reg[B0h], FDh”
■Fix Status
Will not be fixed
■Changes
None
2. Missed GPIO Interrupt
■Problem Definition
When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt
may be missed, and the corresponding GPIO ISR not run.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt.
■Scope of Impact
The GPIO interrupt service routine will not be run.
■Workaround
The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake
the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt.
Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0.
Alternatively, the ISR’s for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system
has attempted to generate a GPIO interrupt.
■Fix Status
Will not be fixed
■Changes
None
Document Number: 001-69257 Rev. *P
Page 37 of 45
CY8C20xx7/S
3. Missed Interrupt During Transition to Sleep
■Problem Definition
If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will
be missed.
■Parameters Affected
No datasheet parameters are affected.
■TriggerCondition(S)
Triggered by enabling sleep mode just prior to an interrupt.
■Scope of Impact
The relevant interrupt service routine will not be run.
■Workaround
None.
■Fix Status
Will not be fixed
■Changes
None
4. Wakeup from sleep with analog interrupt
■Problem Definition
Device wakes up from sleep when an analog interrupt is trigger
■Parameters Affected
No datasheet parameters are affected.
■TriggerCondition(S)
Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 °C or above
■Scope of Impact
Device unexpectedly wakes up from sleep
■Workaround
Disable the analog interrupt before entering sleep and turn it back on upon wake-up.
■Fix Status
Will not be fixed
■Changes
None
Document Number: 001-69257 Rev. *P
Page 38 of 45
CY8C20xx7/S
5. Wake-up from Sleep with Hardware I2C Address match on Pins P1[0], P1[1]
■Problem Definition
I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL, to wake-up from sleep using I2C hardware
address match event.
■Parameters Affected
tHD;DAT increased to 20 ns from 0 ns
■TriggerCondition(S)
This is an issue only when all these three conditions are met:
1) P1.0 and P1.1 are used as I2C pins,
2) Wakeup from sleep with hardware address match feature is enabled, and
3) I2C master does not provide 20 ns hold time on SDA with respect to falling edge of SCL.
■Scope of Impact
These trigger conditions cause the device to never wake-up from sleep based on I2C address match event.
■Workaround
For a design that meets all of the trigger conditions, the following suggested circuit has to be implemented as a work-around.
The R and C values proposed are 100 ohm and 200 pF respectively.
■Fix Status
Will not be fixed
■Changes
None
Document Number: 001-69257 Rev. *P
Page 39 of 45
CY8C20xx7/S
6. I2C Port Pin Pull-up Supply Voltage
■Problem Definition
Pull-up resistor on I2C interface cannot be connected to a supply voltage that is greater than 0.7 V of CY8C20xx7/S VDD
.
■Parameters Affected
None.
■TriggerCondition(S)
This problem occurs only when the I2C master is powered at a higher voltage than CY8C20xx7/S.
■Scope of Impact
This trigger condition will corrupt the I2C communication between the I2C host and the CY8C20xx7/S CapSense controller.
■Workaround
I2C master cannot be powered at a supply voltage that is greater than 0.7 V compared to CY8C20xx7/S supply voltage.
■Fix Status
Will not be fixed
■Changes
None
7. Port1 Pin Voltage
■Problem Definition
Pull-up resistor on port1 pins cannot be connected to a voltage that is greater than 0.7 V higher than CY8C20xx7/S VDD
.
■Parameters Affected
None.
■TriggerCondition(S)
This problem occurs only when port1 pins are at voltage 0.7 V higher than VDD of CY8C20xx7/S.
■Scope of Impact
This trigger condition will not allow CY8C20xx7/S to drive the output signal on port1 pins, input path is unaffected by this
condition.
■Workaround
Port1 should not be connected to a higher voltage than VDD of CY8C20xx7/S.
■Fix Status
Will not be fixed
■Changes
None
Document Number: 001-69257 Rev. *P
Page 40 of 45
CY8C20xx7/S
Document History Page
Document Title: CY8C20xx7/S, 1.8 V CapSense® Controller with SmartSense™Auto-tuning 31 Buttons, 6 Sliders, Proximity
Sensors
Document Number: 001-69257
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
3276782
3327230
DST
DST
06/27/2011 New silicon and document
*A
07/28/2011 Changed 48-pin dimensions to 6 × 6 × 0.6 mm QFN
Updated pins name in Table 3 on page 9 and removed USB column and
updated dimensions for 48-pin parts in Table 35 on page 33
Updated Figure 20 on page 29
Removed ICE and Debugger sections.
Removed CY3215 Development Kit and CY3280-20x66 UCC sections.
Updated Ordering Information.
*B
*C
3403111
3473317
YVA
DST
10/12/2011 Moved status from Advance to Preliminary.
Updated Ordering Information
Removed the row named “48-Pin (6 × 6 mm) QFN (OCD)”.
Changed all 48-pin ordering code column from CY8C20XXX-24LTxx to
CY8C20XXX-24LQxx.
Updated 16-pin SOIC and 16-pin QFN package drawings.
12/23/2011 Updated Features.
Updated Pinouts (Removed PSoC in captions of Figure 2, Figure 3, Figure 4,
Figure 6, and Figure 7).
Updated DC Chip-Level Specifications under Electrical Specifications
(Updated typical value of IDD24 parameter from 3.32 mA to 2.88 mA, updated
typical value of IDD12parameter from 1.86 mAto 1.71 mA, updated typical value
of IDD6 parameter from 1.13 mA to 1.16 mA, updated maximum value of ISB0
parameter from 0.50 µA to 1.1 µA, added ISBI2C parameter and its details).
Updated DC GPIO Specifications under Electrical Specifications (Added the
parameters namely VILLVT3.3, VIHLVT3.3, VILLVT5.5, VIHLVT5.5 and their details in
Table 10, added the parameters namely VILLVT2.5, VIHLVT2.5 and their details in
Table 11).
Added the following sections namely DC I2C Specifications, Shield Driver DC
Specifications, and DC IDAC Specifications under Electrical Specifications.
Updated AC Chip-Level Specifications (Added the parameter namely tJIT_IMO
and its details).
Updated Ordering Information (updated Table 35).
*D
3510277
YVA/DST
02/16/2012 Added CY8C20x37/37S/47/47S/67/67S part numbers and changed title to “1.8
V CapSense® Controller with SmartSense™ Auto-tuning
31 Buttons, 6 Sliders”
Updated Features.
Modified comparator blocks in Logic Block Diagram.
Replaced SmartSense with SmartSense auto-tuning.
Added CY8C20xx7S part numbers in Pin Definitions.
Added footnote for Table 20.
Updated Table 21 and Table 22 and added Table 23.
Updated F32K1 min value.
Updated data hold time min values.
Updated CY8C206x7 part information in Table “Emulation and Programming
Accessories”.
Updated Ordering Information.
*E
3539259
DST
03/01/2012 Changed Datasheet status from Preliminary to Final.
Updated all Pinouts to include Driven Shield Output (optional) information.
Updated Min value for VLPC Table 15.
Updated Offset and Input range in Table 16.
Document Number: 001-69257 Rev. *P
Page 41 of 45
CY8C20xx7/S
Document History Page (continued)
Document Title: CY8C20xx7/S, 1.8 V CapSense® Controller with SmartSense™Auto-tuning 31 Buttons, 6 Sliders, Proximity
Sensors
Document Number: 001-69257
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*F
3645807
DST/BVI
07/03/2012 Updated FSCLK parameter in the Table 31, “SPI Slave AC Specifications,” on
page 26
Changed tOUT_HIGH to tOUT_H in Table 30, “SPI Master AC Specifications,” on
page 25
Updated Features section, “Programmable pin configurations” bullet:
■ Included the following sub-bullet point -
5 mA source current on port 0 and 1 and 1 mA on port 2,3 and 4
■ Changed the bullet point “High sink current of 25 mAfor each GPIO” to “High
sink current of 25 mA for each GPIO. Total 120 mA maximum sink current
per chip”
■ Added “QuietZone™ Controller” bullet and updated “Low power CapSense®
block with SmartSense™ auto-tuning” bullet.
Updated package diagrams 001-13937 to *D and 001-57280 to *C revisions.
*G
3800055
DST
11/23/2012 Changed document title.
Part named changed from CY8C20xx7 to CY8C20xx7/S
Table 20: Update to VIHI2C to match Item #6 in K2 Si Errata document (001-
75370)
Updated package diagrams:
51-85068 to *E
001-09116 to *G
001-13937 to *E
001-42168 to *E
001-57280 to *E
*H
*I
3881332
3993458
SRLI
DST
02/04/2013 Updated Features:
Added Note “Please contact your nearest sales office for additional details.”
and referred the same note in “24 Sensing Inputs – 30-pin WLCSP”.
05/07/2013 Updated Electrical Specifications (Updated DC GPIO Specifications (Updated
heading of third column as “Port 0/1 per I/O (max)” for Table 13)).
Updated Packaging Information:
spec 001-09116 – Changed revision from *G to *H (Figure 17).
Added Errata.
*J
4081796
DST
07/31/2013 Added Errata footnotes (Note 40, 41, 42, 43, 44).
Updated already existing footnotes (Note 50, 51, 55) as Errata footnotes.
Updated Electrical Specifications:
Updated DC Chip-Level Specifications:
Added Note 40, 41, 42, 43 and referred the same notes in ISB0, ISB1, ISBI2C
parameters.
Updated DC GPIO Specifications:
Added Note 44 andreferredthe samenoteindescriptionofVILLVT3.3 parameter
in Table 10.
Updated DC I2C Specifications:
Updated Note 50, 51 referred in Table 20.
Updated AC I2C Specifications:
Updated Note 55 referred in Table 29.
Updated to new template.
Document Number: 001-69257 Rev. *P
Page 42 of 45
CY8C20xx7/S
Document History Page (continued)
Document Title: CY8C20xx7/S, 1.8 V CapSense® Controller with SmartSense™Auto-tuning 31 Buttons, 6 Sliders, Proximity
Sensors
Document Number: 001-69257
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*K
4248645
DST
01/16/2014 Updated Pinouts:
Updated 32-pin QFN (25 Sensing Inputs)[25]:
Updated Figure 6.
Updated Packaging Information:
spec 001-09116 – Changed revision from *H to *I.
*L
4404150
SLAN
06/10/2014 Updated Pinouts:
Updated 16-pin SOIC (10 Sensing Inputs):
Updated Table 1:
Added Note 6 and referred the same note in description of XRES pin.
Updated 16-pin QFN (10 Sensing Inputs)[8]:
Updated Table 2:
Added Note 12 and referred the same note in description of XRES pin.
Updated 24-pin QFN (16 Sensing Inputs)[14]:
Updated Table 3:
Added Note 18 and referred the same note in description of XRES pin.
Updated 30-ball WLCSP (24 Sensing Inputs):
Updated Table 4:
Added Note 21 and referred the same note in description of XRES pin.
Updated 32-pin QFN (25 Sensing Inputs)[25]:
Updated Table 5:
Added Note 29 and referred the same note in description of XRES pin.
Updated 48-pin QFN (31 Sensing Inputs)[31]:
Updated Table 6:
Added Note 35 and referred the same note in description of XRES pin.
Updated Electrical Specifications:
Updated DC GPIO Specifications:
Updated Table 10:
Updated minimum and maximum values of VIH parameter.
Updated Table 11:
Updated minimum and maximum values of VIH parameter.
Updated AC Chip-Level Specifications:
Updated Table 24:
Removed minimum and maximum values of “ILO untrimmed frequency”.
Updated Packaging Information:
spec 001-09116 – Changed revision from *I to *J.
Completing Sunset Review.
*M
*N
4825924
5068999
SLAN
ARVI
07/07/2015 Added the footnote “All VSS pins should be brought out to one common GND
plane” in pinout tables (Table 1 through Table 6).
Updated Packaging Information:
spec 001-13937 – Changed revision from *E to *F.
Updated to new template.
12/31/2015 Updated hyperlink of “Technical Reference Manual” in all instances across the
document.
Updated PSoC® Functional Overview:
Updated Additional System Resources:
Updated description.
Updated Development Tool Selection:
Removed “Accessories (Emulation and Programming)”.
Removed “Build a PSoC Emulator into Your Board”.
Document Number: 001-69257 Rev. *P
Page 43 of 45
CY8C20xx7/S
Document History Page (continued)
Document Title: CY8C20xx7/S, 1.8 V CapSense® Controller with SmartSense™Auto-tuning 31 Buttons, 6 Sliders, Proximity
Sensors
Document Number: 001-69257
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*O
5122184
JFMD
02/02/2016 Updated Features:
Removed Note “Please contact your nearest sales office for additional details.”
and its reference.
Updated Ordering Information:
Updated Table 35:
Updated part numbers.
*P
5742810 AESATMP9 05/19/2017 Updated logo and copyright.
Document Number: 001-69257 Rev. *P
Page 44 of 45
CY8C20xx7/S
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-69257 Rev. *P
Revised May 19, 2017
Page 45 of 45
相关型号：
CY8C20247/S-24LKXI
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
CYPRESS
CY8C20247/S-24LKXIT
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
CYPRESS
CY8C20247/S-24SXI
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
CYPRESS
CY8C20247S-24LKXI
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
CYPRESS
CY8C20247S-24LKXIT
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
CYPRESS
CY8C20247S-24SXI
1.8 V CapSense® Controller with SmartSense⢠Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
CYPRESS
©2020 ICPDF网 联系我们和版权申明