CY8C20246AS-24LKXI_技术文档

CY8C20XX6A/S

1.8 V Programmable CapSense^®Controller

with SmartSense™ Auto-tuning

1–33 Buttons, 0–6 Sliders

1.8

V Programmable CapSense^®Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6 Sliders

❐ High sink current of 25 mA per GPIO

• Max sink current 120 mA for all GPIOs

❐ Source Current

Features

■ Low power CapSense^®block with SmartSense Auto-tuning

❐ Patented CSA_EMC, CSD sensing algorithms

❐ SmartSense_EMC Auto-Tuning

• Sets and maintains optimal sensor performance during run

time

• Eliminates system tuning during development and

production

• Compensates for variations in manufacturing process Low

average power consumption – xx µA/sensor in run time

(wake-up and scan once every yyy ms)

• 5 mA on ports 0 and 1

• 1 mA on ports 2,3 and 4

❐ Configurable internal pull-up, high-Z and open drain modes

❐ Selectable, regulated digital I/O on port 1

❐ Configurable input threshold on port 1

■ Versatile Analog functions

❐ Internal analog bus supports connection of multiple sensors

to form ganged proximity sensor

❐ InternalLow-Dropoutvoltageregulatorfor highpowersupply

rejection ratio (PSRR)

■ Powerful Harvard-architecture processor

❐ M8C CPU with a max speed of 24 MHz

■ Full-Speed USB

■ Operating Range: 1.71 V to 5.5 V

❐ Standby Mode 1.1 μA (Typ)

❐ Deep Sleep 0.1 μA (Typ)

❐ 12 Mbps USB 2.0 compliant

■ Additional system resources

❐ I2C Slave:

■ Operating Temperature range: –40 °C to +85 °C

• Selectable to 50 kHz, 100 kHz, or 400 kHz

❐ Configurable up to 12 MHz SPI master and slave

❐ Three 16-bit timers

❐ Watchdog and sleep timers

❐ Integrated supervisory circuit

❐ 10-bit incremental analog-to-digital converter (ADC) with

internal voltage reference

❐ Two general-purpose high speed, low power analog

comparators

■ Flexible on-chip memory

❐ 8 KB flash, 1 KB SRAM

❐ 16 KB flash, 2 KB SRAM

❐ 32 KB flash, 2 KB SRAM

❐ Read while Write with EEPROM emulation

❐ 50,000 flash erase/write cycles

❐ In-system programming simplifies manufacturing process

■ Four Clock Sources

❐ Internal main oscillator (IMO): 6/12/24 MHz

❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog

and sleep timers

❐ External 32 KHz Crystal Oscillator

❐ External Clock Input

■ Complete development tools

❐ Free development tool (PSoC Designer™)

■ Sensor and Package options

❐ 10 Sensors – QFN 16, 24

❐ 16 Sensors – QFN 24

❐ 22 / 25 Sensors – QFN 32

❐ 24 Sensors - WLCSP 30

❐ 31 Sensors – SSOP 48

❐ 33 Sensors – QFN 48

■ Programmable pin configurations

❐ Up to 36 general-purpose I/Os (GPIOs) configurable as

buttons or sliders

❐ Dual mode GPIO (Analog inputs and Digital I/O supported)

Errata: For information on silicon errata, see “Errata” on page 45. Details include trigger conditions, devices affected, and proposed workaround

Cypress Semiconductor Corporation

Document Number: 001-54459 Rev. *T

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 28, 2013

CY8C20XX6A/S

Logic Block Diagram

[1]

1.8/2.5/3V

LDO

PWRSYS

Port 4 Port 3

Port 2

Port 1

Port 0

(Regulator)

PSoC CORE

SYSTEM BUS

Global Analog Interconnect

8K/16K/32K Flash

1K/2K

SRAM

Supervisory ROM (SROM)

Nonvolatile Memory

Interrupt

Controller

Sleep and

Watchdog

CPU Core (M8C)

6/12/24 MHz Internal Main Oscillator

(IMO)

Internal Low Speed Oscillator (ILO)

Multiple Clock Sources

CAPSENSE

SYSTEM

Analog

Reference

CapSense

Module

Two

Analog

Mux

Comparators

SYSTEM BUS

Internal

Voltage

References

POR

and

LVD

SPI

Master/

Slave

Three 16-Bit

Programmable

Timers

I2C

Slave

System

Resets

Digital

Clocks

USB

SYSTEM RESOURCES

Note

1. Internal voltage regulator for internal circuitry

Document Number: 001-54459 Rev. *T

Page 2 of 51

CY8C20XX6A/S

Contents

PSoC^®Functional Overview ............................................4

PSoC Core ..................................................................4

CapSense System .......................................................4

Additional System Resources .....................................5

Getting Started ..................................................................6

CapSense Design Guides ...........................................6

Silicon Errata ...............................................................6

Development Kits ........................................................6

Training .......................................................................6

CYPros Consultants ....................................................6

Solutions Library ..........................................................6

Technical Support .......................................................6

Development Tools ..........................................................7

PSoC Designer Software Subsystems ........................7

Designing with PSoC Designer .......................................8

Select User Modules ...................................................8

Configure User Modules ..............................................8

Organize and Connect ................................................8

Generate, Verify, and Debug .......................................8

Pinouts ..............................................................................9

16-pin QFN (10 Sensing Inputs) ..................................9

24-pin QFN (17 Sensing Inputs) ................................10

24-pin QFN (15 Sensing Inputs (With USB)) .............11

30-ball WLCSP (24 Sensing Inputs) ..........................12

32-pin QFN (25 Sensing Inputs) ................................13

32-pin QFN (22 Sensing Inputs (With USB)) .............14

48-pin SSOP (31 Sensing Inputs) .............................15

48-pin QFN (33 Sensing Inputs) ................................16

48-pin QFN (33 Sensing Inputs (With USB)) .............17

48-pin QFN (OCD) (33 Sensing Inputs) ....................18

Electrical Specifications ................................................19

Absolute Maximum Ratings .......................................19

Operating Temperature .............................................19

DC Chip-Level Specifications ....................................20

DC GPIO Specifications ............................................21

DC Analog Mux Bus Specifications ...........................23

DC Low Power Comparator Specifications ...............23

Comparator User Module Electrical Specifications ...24

ADC Electrical Specifications ....................................24

DC POR and LVD Specifications ..............................25

DC Programming Specifications ...............................25

DC I2C Specifications ...............................................26

DC Reference Buffer Specifications ..........................26

DC IDAC Specifications ............................................26

AC Chip-Level Specifications ....................................27

AC GPIO Specifications ............................................28

AC Comparator Specifications ..................................29

AC External Clock Specifications ..............................29

AC Programming Specifications ................................30

AC I2C Specifications ................................................31

Packaging Information ...................................................34

Thermal Impedances .................................................37

Capacitance on Crystal Pins .....................................37

Solder Reflow Specifications .....................................37

Development Tool Selection .........................................38

Software ....................................................................38

Development Kits ......................................................38

Evaluation Tools ........................................................38

Device Programmers .................................................38

Accessories (Emulation and Programming) ..............39

Third Party Tools .......................................................39

Build a PSoC Emulator into Your Board ....................39

Ordering Information ......................................................40

Ordering Code Definitions .........................................42

Acronyms ........................................................................43

Reference Documents ....................................................43

Document Conventions .................................................43

Units of Measure .......................................................43

Numeric Naming ........................................................44

Glossary ..........................................................................44

Errata ...............................................................................45

Qualification Status ...................................................45

Errata Summary ........................................................45

Document History Page .................................................48

Sales, Solutions, and Legal Information ......................51

Worldwide Sales and Design Support .......................51

Products ....................................................................51

PSoC® Solutions ......................................................51

Cypress Developer Community .................................51

Technical Support .....................................................51

Document Number: 001-54459 Rev. *T

Page 3 of 51

CY8C20XX6A/S

®

required tuning parameters. SmartSense allows engineers to go

from prototyping to mass production without re-tuning for

manufacturing variations in PCB and/or overlay material

properties.

PSoC Functional Overview

The PSoC family consists of on-chip controller devices, which

are designed to replace multiple traditional microcontroller unit

(MCU)-based components with one, low cost single-chip

SmartSense_EMC

programmable component.

A

PSoC device includes

configurable analog and digital blocks, and programmable

interconnect. This architecture allows the user to create

customized peripheral configurations, to match the requirements

of each individual application. Additionally, a fast CPU, Flash

program memory, SRAM data memory, and configurable I/O are

included in a range of convenient pinouts.

In addition to the SmartSense auto tuning algorithm to remove

manual tuning of CapSense applications, SmartSense_EMC

user module incorporates a unique algorithm to improve

robustness of capacitive sensing algorithm/circuit against high

frequency conducted and radiated noise. Every electronic device

must comply with specific limits for radiated and conducted

external noise and these limits are specified by regulatory bodies

(for example, FCC, CE, U/L and so on). A very good PCB layout

design, power supply design and system design is a mandatory

for a product to pass the conducted and radiated noise tests. An

ideal PCB layout, power supply design or system design is not

often possible because of cost and form factor limitations of the

product. SmartSense_EMC with superior noise immunity is well

suited and handy for such applications to pass radiated and

conducted noise test.

The architecture for this device family, as shown in the Logic

Block Diagram on page 2, consists of three main areas:

■ The Core

■ CapSense Analog System

■ System Resources (including a full-speed USB port).

A common, versatile bus allows connection between I/O and the

analog system.

Figure 1. CapSense System Block Diagram

Each CY8C20XX6A/S PSoC device includes a dedicated

CapSense block that provides sensing and scanning control

circuitry for capacitive sensing applications. Depending on the

PSoC package, up to 36 GPIO are also included. The GPIO

provides access to the MCU and analog mux.

CS1

IDAC

CS2

PSoC Core

The PSoC Core is a powerful engine that supports a rich

instruction set. It encompasses SRAM for data storage, an

interrupt controller, sleep and watchdog timers, and IMO and

ILO. The CPU core, called the M8C, is a powerful processor with

speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit

Harvard-architecture microprocessor.

CSN

Vr

Reference

Buffer

Cinternal

CapSense System

The analog system contains the capacitive sensing hardware.

Several hardware algorithms are supported. This hardware

performs capacitive sensing and scanning without requiring

external components. The analog system is composed of the

CapSense PSoC block and an internal 1 V or 1.2 V analog

reference, which together support capacitive sensing of up to

33 inputs . Capacitive sensing is configurable on each GPIO

pin. Scanning of enabled CapSense pins are completed quickly

and easily across multiple ports.

Cexternal (P0[1]

or P0[3])

Comparator

Mux

Refs

[2]

Cap Sense Counters

CSCLK

SmartSense

SmartSense is an innovative solution from Cypress that removes

manual tuning of CapSense applications. This solution is easy to

use and provides a robust noise immunity. It is the only

auto-tuning solution that establishes, monitors, and maintains all

CapSense

Clock Select

IMO

Oscillator

Note

2

2. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I C + 1 pin for modulator capacitor.

Document Number: 001-54459 Rev. *T

Page 4 of 51

CY8C20XX6A/S

Analog Multiplexer System

communication interface, three 16-bit programmable timers, and

various system resets supported by the M8C.

The Analog Mux Bus can connect to every GPIO pin. Pins are

connected to the bus individually or in any combination. The bus

also connects to the analog system for analysis with the

CapSense block comparator.

These system resources provide additional capability useful to

complete systems. Additional resources include low voltage

detection and power on reset. The merits of each system

resource are listed here:

Switch control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

2

■ The I C slave/SPI master-slave module provides

50/100/400 kHz communication over two wires. SPI

communication over three or four wires runs at speeds of

46.9 kHz to 3 MHz (lower for a slower system clock).

■ Complex capacitive sensing interfaces, such as sliders and

touchpads.

■ Low-voltage detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced

power-on-reset (POR) circuit eliminates the need for a system

supervisor.

■ Chip-wide mux that allows analog input from any I/O pin.

■ Crosspoint connection between any I/O pin combinations.

■ An internal reference provides an absolute reference for

capacitive sensing.

Additional System Resources

System resources provide additional capability, such as

2

■ A register-controlled bypass mode allows the user to disable

the LDO regulator.

configurable USB and I C slave, SPI master/slave

Document Number: 001-54459 Rev. *T

Page 5 of 51

CY8C20XX6A/S

errata document with datasheet for a complete functional

description of device.

Getting Started

The quickest way to understand PSoC silicon is to read this

datasheet and then use the PSoC Designer Integrated

Development Environment (IDE). This datasheet is an overview

of the PSoC integrated circuit and presents specific pin, register,

and electrical specifications.

Development Kits

PSoC Development Kits are available online from and through a

growing number of regional and global distributors, which

include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and

Newark.

For in depth information, along with detailed programming

details, see the Technical Reference Manual for the

CY8C20XX6A/S PSoC devices.

Training

Free PSoC technical training (on demand, webinars, and

workshops), which is available online via www.cypress.com,

covers a wide variety of topics and skill levels to assist you in

your designs.

For up-to-date ordering, packaging, and electrical specification

information, see the latest PSoC device datasheets on the web

at www.cypress.com/psoc.

CapSense Design Guides

CYPros Consultants

Design Guides are an excellent introduction to the wide variety

of possible CapSense designs. They are located at

www.cypress.com/go/CapSenseDesignGuides.

Certified PSoC consultants offer everything from technical

assistance to completed PSoC designs. To contact or become a

PSoC consultant go to the CYPros Consultants web site.

Refer Getting Started with CapSense design guide for

information on CapSense design and CY8C20XX6A/H/AS

Solutions Library

®

CapSense

Design Guide for specific information on

Visit our growing library of solution focused designs. Here you

can find various application designs that include firmware and

hardware design files that enable you to complete your designs

quickly.

CY8C20XX6A/AS CapSense controllers.

Silicon Errata

Errata documents known issues with silicon including errata

trigger conditions, scope of impact, available workarounds and

silicon revision applicability. Refer to Silicon Errata for the PSoC

CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H

available at http://www.cypress.com/?rID=56239 for errata

information on CY8C20xx6A/AS/H family of device. Compare

Technical Support

®

Technical support – including a searchable Knowledge Base

articles and technical forums – is also available online. If you

cannot find an answer to your question, call our Technical

Support hotline at 1-800-541-4736.

families

Document Number: 001-54459 Rev. *T

Page 6 of 51

CY8C20XX6A/S

Code Generation Tools

Development Tools

The code generation tools work seamlessly within the

PSoC Designer interface and have been tested with a full range

of debugging tools. You can develop your design in C, assembly,

or a combination of the two.

PSoC Designer™ is the revolutionary integrated design

environment (IDE) that you can use to customize PSoC to meet

your specific application requirements. PSoC Designer software

accelerates system design and time to market. Develop your

applications using a library of precharacterized analog and digital

peripherals (called user modules) in a drag-and-drop design

environment. Then, customize your design by leveraging the

dynamically generated application programming interface (API)

libraries of code. Finally, debug and test your designs with the

integrated debug environment, including in-circuit emulation and

standard software debug features. PSoC Designer includes:

Assemblers. The assemblers allow you to merge assembly

code seamlessly with C code. Link libraries automatically use

absolute addressing or are compiled in relative mode, and linked

with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices. The

optimizing C compilers provide all of the features of C, tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

■ Application editor graphical user interface (GUI) for device and

user module configuration and dynamic reconfiguration

■ Extensive user module catalog

■ Integrated source-code editor (C and assembly)

■ Free C compiler with no size restrictions or time limits

■ Built-in debugger

Debugger

PSoC Designer has a debug environment that provides

hardware in-circuit emulation, allowing you to test the program in

a physical system while providing an internal view of the PSoC

device. Debugger commands allow you to read and program and

read and write data memory, and read and write I/O registers.

You can read and write CPU registers, set and clear breakpoints,

and provide program run, halt, and step control. The debugger

also lets you to create a trace buffer of registers and memory

locations of interest.

■ In-circuit emulation

■ Built-in support for communication interfaces:

2

❐ Hardware and software I C slaves and masters

❐ Full-speed USB 2.0

❐ Up

to

four

full-duplex

universal

asynchronous

receiver/transmitters (UARTs), SPI master and slave, and

wireless

Online Help System

The online help system displays online, context-sensitive help.

Designed for procedural and quick reference, each functional

subsystem has its own context-sensitive help. This system also

provides tutorials and links to FAQs and an Online Support

Forum to aid the designer.

PSoC Designer supports the entire library of PSoC 1 devices and

runs on Windows XP, Windows Vista, and Windows 7.

PSoC Designer Software Subsystems

Design Entry

In-Circuit Emulator

In the chip-level view, choose a base device to work with. Then

select different onboard analog and digital components that use

the PSoC blocks, which are called user modules. Examples of

user modules are analog-to-digital converters (ADCs),

digital-to-analog converters (DACs), amplifiers, and filters.

Configure the user modules for your chosen application and

connect them to each other and to the proper pins. Then

generate your project. This prepopulates your project with APIs

and libraries that you can use to program your application.

A

low-cost, high-functionality in-circuit emulator (ICE) is

available for development support. This hardware can program

single devices.

The emulator consists of a base unit that connects to the PC

using a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full-speed

(24 MHz) operation.

The tool also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

reconfiguration makes it possible to change configurations at run

time. In essence, this lets you to use more than 100 percent of

PSoC’s resources for an application.

Document Number: 001-54459 Rev. *T

Page 7 of 51

CY8C20XX6A/S

internal operation of the user module and provide performance

specifications. Each datasheet describes the use of each user

module parameter, and other information that you may need to

successfully implement your design.

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed-function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and lowering inventory costs. These

configurable resources, called PSoC blocks, have the ability to

implement a wide variety of user-selectable functions. The PSoC

development process is:

Organize and Connect

Build signal chains at the chip level by interconnecting user

modules to each other and the I/O pins. Perform the selection,

configuration, and routing so that you have complete control over

all on-chip resources.

1. Select user modules.

Generate, Verify, and Debug

2. Configure user modules.

3. Organize and connect.

4. Generate, verify, and debug.

When you are ready to test the hardware configuration or move

on to developing code for the project, perform the “Generate

Configuration Files” step. This causes PSoC Designer to

generate source code that automatically configures the device to

your specification and provides the software for the system. The

generated code provides APIs with high-level functions to control

and respond to hardware events at run time, and interrupt

service routines that you can adapt as needed.

Select User Modules

PSoC Designer provides a library of prebuilt, pretested hardware

peripheral components called “user modules”. User modules

make selecting and implementing peripheral devices, both

analog and digital, simple.

A complete code development environment lets you to develop

and customize your applications in C, assembly language, or

both.

Configure User Modules

Each user module that you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a PWM

User Module configures one or more digital PSoC blocks, one

for each eight bits of resolution. Using these parameters, you can

establish the pulse width and duty cycle. Configure the

parameters and properties to correspond to your chosen

application. Enter values directly or by selecting values from

drop-down menus. All of the user modules are documented in

datasheets that may be viewed directly in PSoC Designer or on

the Cypress website. These user module datasheets explain the

The last step in the development process takes place inside

PSoC Designer’s Debugger (accessed by clicking the Connect

icon). PSoC Designer downloads the HEX image to the ICE

where it runs at full-speed. PSoC Designer debugging

capabilities rival those of systems costing many times more. In

addition to traditional single-step, run-to-breakpoint, and

watch-variable features, the debug interface provides a large

trace buffer. It lets you to define complex breakpoint events that

include monitoring address and data bus values, memory

locations, and external signals.

Document Number: 001-54459 Rev. *T

Page 8 of 51

CY8C20XX6A/S

Pinouts

The CY8C20XX6A/S PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every

port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, V , V , and XRES are

SS

DD

not capable of Digital I/O.

[3, 4]

16-pin QFN (10 Sensing Inputs)

Table 1. Pin Definitions – CY8C20236A, CY8C20246A, CY8C20246AS PSoC Device

Type

Figure 2. CY8C20236A, CY8C20246A, CY8C20246AS

No.

Name

Description

Digital Analog

1

2

3

4

5

6

I/O

I

P2[5] Crystal output (XOut)

P2[3] Crystal input (XIn)

I/O

AI, XOut, P2[5]

AI, XIn,P2[3]

1

2

P0[4] , AI

IOHR

P1[7] I C SCL, SPI SS

12

11

10

QFN

( Top View)

XRES

P1[4], EXTCLK,AI

P1[2] , AI

2

P1[5] I C SDA, SPI MISO

AI,I2 C SCL, SPI SS,P1[7]

AI,I2 C SDA, SPI MISO,P1[5]

3

4

9

P1[3] SPI CLK

[5]

2

P1[1] ISSP CLK , I C SCL, SPI

MOSI

7

8

Power

V

Ground connection

SS

[5]

2

IOHR

I

P1[0] ISSP DATA , I C SDA, SPI

[6]

CLK

9

IOHR

I

P1[2]

10

P1[4] Optional external clock

(EXTCLK)

11

Input

XRES Active high external reset with

internal pull-down

12

13

14

15

16

IOH

I

P0[4]

Power

V

Supply voltage

DD

IOH

I

P0[7]

P0[3] Integrating input

P0[1] Integrating input

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Notes

3. 13 GPIOs = 10 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.

4. No Center Pad.

5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

6. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 9 of 51

CY8C20XX6A/S

24-pin QFN (17 Sensing Inputs) ^[7]

[8]

Table 2. Pin Definitions – CY8C20336A, CY8C20346A, CY8C20346AS

Type

Figure 3. CY8C20336A, CY8C20346A, CY8C20346AS

Name

Description

No.

Digital Analog

1

2

3

4

5

6

7

I/O

I

P2[5] Crystal output (XOut)

P2[3] Crystal input (XIn)

P2[1]

I/O

2

18

17

AI, XOut, P2[5]

AI, XIn, P2[3]

1

2

3

4

5

6

P0[4], AI

P0[2], AI

P0[0], AI

P2[0], AI

XRES

IOHR

P1[7] I C SCL, SPI SS

2

P1[5] I C SDA, SPI MISO

16

15

AI, P2[1]

QFN

(Top View )

AI, I2C SCL, SPI SS, P1[7]

AI, I2C SDA, SPI M ISO, P1[5]

AI, SPI CLK, P1[3]

P1[3] SPI CLK

14

13

P1[6], AI

[9]

2

P1[1] ISSP CLK , I C SCL, SPI

MOSI

8

9

NC

No connection

Power

V

Ground connection

SS

[9]

2

10

IOHR

I

P1[0] ISSP DATA , I C SDA, SPI

[10]

CLK

11

12

IOHR

I

P1[2]

P1[4] Optional external clock input

(EXTCLK)

13

14

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull-down

15

16

17

18

19

20

21

22

23

24

CP

I/O

I

P2[0]

P0[0]

P0[2]

P0[4]

P0[6]

IOH

Power

V

Supply voltage

DD

IOH

I

P0[7]

P0[5]

P0[3] Integrating input

P0[1] Integrating input

Power

V

Center pad must be

connected to ground

SS

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Notes

7. 20 GPIOs = 17 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.

8. The center pad (CP) on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground,

SS

it must be electrically floated and not connected to any other signal.

9. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

10. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 10 of 51

CY8C20XX6A/S

24-pin QFN (15 Sensing Inputs (With USB)) ^[11]

[12]

Table 3. Pin Definitions – CY8C20396A

Type

Figure 4. CY8C20396A

Name

Description

No.

Digital Analog

1

2

3

4

5

6

7

I/O

I

P2[5]

P2[3]

P2[1]

I/O

2

[ ], AI

P2 5

18

17

16

15

14

13

1

2

3

4

5

6

P0[2], AI

IOHR

P1[7] I C SCL, SPI SS

[

P2 3], AI

P0[0], AI

2

P1[5] I C SDA, SPI MISO

[

XRES

P2 1], AI

QFN

(Top View)

P1[3] SPI CLK

AI, I2 C SCL, SPI SS,P1[7]

AI, I2C SDA, SPI MISO,P1[5]

AI, SPI CLK,P1[3]

P1[6], AI

P1[4] , AI, EXTCLK

P1[2 ], AI

[13]

2

P1[1] ISSP CLK , I C SCL, SPI

MOSI

8

Power

V

Ground

USB D+

USB D-

Supply

SS

9

I/O

I

D+

D-

10

11

12

Power

V

DD

[13]

2

IOHR

I

P1[0] ISSP DATA , I C SDA, SPI

[14]

CLK

13

14

IOHR

I

P1[2]

P1[4] Optional external clock input

(EXTCLK)

15

16

IOHR

I

P1[6]

RESET INPUT

XRES Active high external reset with

internal pull-down

17

18

19

20

21

22

23

24

CP

IOH

I

P0[0]

P0[2]

P0[4]

P0[6]

P0[7]

P0[5]

P0[3] Integrating input

P0[1] Integrating input

Power

V

Center pad must be connected

to Ground

SS

LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output

Notes

11. 20 GPIOs = 15 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.

12. The center pad (CP) on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground,

SS

it must be electrically floated and not connected to any other signal.

13. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

14. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 11 of 51

CY8C20XX6A/S

30-ball WLCSP (24 Sensing Inputs) ^[15]

Table 4. Pin Definitions – CY8C20766A, CY8C20746A 30-ball WLCSP

Type

Name

Description

No.

Digital Analog

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

C1

C2

C3

C4

C5

D1

D2

D3

D4

D5

E1

IOH

I

P0[2]

P0[6]

Figure 5. CY8C20766A 30-ball WLCSP

Bottom View

Power

V

Supply voltage

5

4

3

2

1

DD

IOH

I/O

I

P0[1] Integrating Input

A

B

C

D

E

F

P2[7]

I/O

P2[6]

IOH

I/O

P0[0]

P0[4]

P0[3] Integrating Input

P2[5] Crystal Output (Xout)

I/O

P2[2]

I/O

P2[4]

IOH

I/O

P0[7]

P0[5]

Top View

P2[3] Crystal Input (Xin)

1

2

3

4

5

I/O

P2[0]

P3[0]

P3[1]

P3[3]

P2[1]

I/O

A

B

I/O

C

Input

XRES Active high external reset with

internal pull-down

D

E

E2

E3

IOHR

I

P1[6]

P1[4] Optional external clock input

(EXT CLK)

2

E4

E5

F1

F2

IOHR

I

P1[7] I C SCL, SPI SS

F

2

P1[5] I C SDA, SPI MISO

P1[2]

[16]

2

P1[0] ISSP DATA , I C SDA, SPI

[17]

CLK

V_SS

F3

F4

Power

Supply ground

[16]

2

IOHR

I

P1[1] ISSP CLK , I C SCL, SPI

MOSI

F5

IOHR

P1[3] SPI CLK

Notes

15. 27 GPIOs = 24 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.

16. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

17. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 12 of 51

CY8C20XX6A/S

32-pin QFN (25 Sensing Inputs) ^[18]

[19]

Table 5. Pin Definitions – CY8C20436A, CY8C20446A, CY8C20446AS, CY8C20466A, CY8C20466AS

Type

Figure 6. CY8C20436A, CY8C20446A, CY8C20446AS,

CY8C20466A, CY8C20466AS

No.

Name

Description

Digital

Analog

1

2

IOH

I/O

I

P0[1] Integrating input

P2[7]

3

I/O

P2[5] Crystal output (XOut)

P2[3] Crystal input (XIn)

P2[1]

4

I/O

AI, P0[1]

AI, P2[7]

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P0[0] , AI

P2[6] , AI

P2[4] , AI

P2[2] , AI

P2[0] , AI

P3[2] , AI

P3[0] , AI

XRES

5

I/O

6

I/O

P3[3]

AI, XOut,P2[5]

AI, XIn,P2[3]

AI, P2[1]

QFN

(Top View)

7

I/O

P3[1]

8

IOHR

P1[7] I²C SCL, SPI SS

P1[5] I²C SDA, SPI MISO

P1[3] SPI CLK.

AI, P3[3]

AI, P3[1]

AI,I2 C SCL, SPI SS,P1[7]

9

10

11

12

13

P1[1] ISSP CLK^[20], I²C SCL, SPI MOSI.

Power

V_SS

Ground connection.

IOHR

I

P1[0] ISSP DATA^[20], I²C SDA,

SPI CLK^[21]

14

15

IOHR

I

P1[2]

P1[4] Optional external clock input

(EXTCLK)

16

17

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull-down

18

I/O

I

P3[0]

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CP

I/O

I

P3[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I/O

IOH

Power

V_DD

P0[7]

P0[5]

Supply voltage

IOH

I

P0[3] Integrating input

Power

V_SS

Ground connection

Center pad must be connected to

ground

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Notes

18. 28 GPIOs = 25 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.

19. The center pad (CP) on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground,

SS

it must be electrically floated and not connected to any other signal.

20. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

21. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 13 of 51

CY8C20XX6A/S

32-pin QFN (22 Sensing Inputs (With USB)) ^[22]

[23]

Table 6. Pin Definitions – CY8C20496A

Type

Figure 7. CY8C20496A

Name

Description

No.

Digital Analog

1

2

IOH

I/O

I

P0[1] Integrating Input

P2[5] XTAL Out

3

I/O

P2[3] XTAL In

AI

P

1

,

0[ ]

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P0[0] , AI

P2[6] , AI

P2[4] , AI

P2[2] , AI

P2[0] , AI

P3[2] , AI

P3[0] , AI

XRES

4

I/O

P2[1]

XTAL OUT P2 5

[ ]

P1[7] I²C SCL, SPI SS

P1[5] I²C SDA, SPI MISO

P1[3] SPI CLK

XTAL IN P2 3

,

[ ]

7]

1[

5

1[ ]

5

IOHR

AI P2 1

QFN

(Top View)

6

P

I2C SCL, SPI SS

I2C SDA, SPI MISO

7

SPI CLK P1

]

[3

,

[24]

ISSP CLK, I2C SCL, SPI MOSI,P1 1

8

P1[1] ISSP CLK^[24], I²C SCL, SPI MOSI

[ ]

9

Power

V_SS

D+

Ground Pin

USB D+

10

11

12

13

I

D-

USB D-

Power

V_DD

Power pin

IOHR

I

P1[0] ISSP DATA^[24], I²C SDA, SPI

CLKI^[25]

14

15

IOHR

I

P1[2]

P1[4] Optional external clock input

(EXTCLK)

16

17

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull-down

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

I/O

I

P3[0]

P3[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

I/O

IOH

Power

V_DD

P0[7]

P0[5]

Power Pin

IOH

I

P0[3] Integrating Input

V_SSGround Pin

LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.

Notes

22. 27 GPIOs = 22 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.

23. The center pad (CP) on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground,

SS

it must be electrically floated and not connected to any other signal.

24. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

25. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 14 of 51

CY8C20XX6A/S

48-pin SSOP (31 Sensing Inputs) ^[26]

Table 7. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A

[27]

No.

Figure 8. CY8C20536A, CY8C20546A, and CY8C20566A

Digital Analog Name

Description

1

IOH

I/O

I

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

NC

AI,P0[7]

AI,P0[5]

AI, P0[3]

AI P0[1]

AI, P2[7]

1

2

3

4

5

6

VDD

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

2

P0[6] , AI

P0[4] , AI

P0[2] , AI

P0[0] , AI

P2[6] , AI

P2[4] , AI

P2[2], AI

P2[0], AI

P3[6], AI

P3[4], AI

P3[2], AI

P3[0] , AI

XRES

3

Integrating Input

4

Integrating Input

XTALOUT,P2[5]

XTALIN,P2[3]

5

7

8

9

AI,P2[1]

NC

6

I/O

XTAL Out

XTAL In

NC

10

7

I/O

AI,P4[3]

AI,P4[1]

NC

AI,P3[7]

AI, P3[5]

AI, P3[3]

AI, P3[1]

NC

11

12

13

14

15

16

8

I/O

SSOP

9

No connection

NC

10

NC

11 I/O

12 I/O

13

I

P4[3]

P4[1]

NC

17

18

19

20

21

NC

P1[6] , AI

NC

I2 C SCL, SPI SS,P1[7]

No connection

I2 C SDA, SPI MISO,P1[5]

SPI CLK,P1[3]

ISSP CLK,I2C SCL, SPI MOSI,P1[1 ] 23

14 I/O

15 I/O

16 I/O

17 I/O

18

I

P3[7]

P3[5]

P3[3]

P3[1]

NC

[27]

22

P1[4] , EXT CLK

P1[2], AI

[27, 28]

VSS

24

P1[0],ISSP DATA,I2C SDA,SPI CLK

No connection

19

NC

No connection

20 IOHR

21 IOHR

22 IOHR

23 IOHR

24

I

P1[7]

P1[5]

P1[3]

P1[1]

V_SS

I²C SCL, SPI SS

I²C SDA, SPI MISO

SPI CLK

ISSP CLK^[27], I²C SCL, SPI MOSI

Ground Pin

25 IOHR

I

P1[0]

ISSP DATA^[27], I²C SDA, SPI

CLK^[28]

26 IOHR

27 IOHR

I

P1[2]

P1[4]

Optional external clock input

(EXT CLK)

28 IOHR

I

P1[6]

NC

29

30

31

32

No connection

NC

No.

NC

Digital Analog

Name

Description

33

34

35

NC

No connection

41

42

43

I/O

I

P2[2]

P2[4]

P2[6]

XRES Active high external reset with

internal pull-down

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

I

P3[0]

P3[2]

P3[4]

P3[6]

P2[0]

44

45

46

47

48

IOH

I

P0[0]

P0[2]

P0[4]

P0[6]

V_DD

IOH

VREF

IOH

Power

Power Pin

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.

Notes

26. 34 GPIOs = 31 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.

27. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

28. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 15 of 51

CY8C20XX6A/S

48-pin QFN (33 Sensing Inputs) ^[29]

[30, 31]

Table 8. Pin Definitions – CY8C20636A

Figure 9. CY8C20636A

Digital Analog Name

Description

No connection

No.

1

NC

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

I/O

I

P2[7]

P2[5]

P2[3]

P2[1]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

NC

Crystal output (XOut)

Crystal input (XIn)

NC

P2[6] ,AI

P2[4] A, I

36

35

34

33

32

31

1

2

3

4

5

AI ,P2[7]

AI , XOut,P2[5]

AI ,XIn ,P2[3]

AI ,P2[1]

P2[2] ,AI

P2[0] A, I

P4[2] ,AI

P4[0] ,AI

AI ,P4[3]

6

QFN

(Top View)

AI ,P4[1]

AI ,P3[7]

AI ,P3[5]

AI ,P3[3]

30

29

28

27

P3[6] ,AI

P3[4] ,AI

P3[2] ,AI

7

8

9

10

I/O

IOHR

I²C SCL, SPI SS

I²C SDA, SPI MISO

No connection

SPI CLK

ISSP CLK^[30], I²C SCL, SPI

MOSI

] ,AI

P3[0

AI P

3[1]

XRES

26

25

11

12

AI ,I2 C SCL, SPI SS,P1[7]

P1[6] ,AI

NC

P1[3]

P1[1]

IOHR

I

18

19

20

21

22

Power

V_SS

Ground connection

DNU

V_DD

Power

IOHR

Supply voltage

ISSP DATA^[30], I²C SDA, SPI

CLK^[32]

I

P1[0]

23

24

IOHR

I

P1[2]

P1[4]

Optional external clock input

(EXTCLK)

25

26

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull-down

27

28

29

I/O

I

P3[0]

P3[2]

P3[4]

No.

Digital Analog

Name

Description

30

31

32

33

34

35

36

37

38

39

I/O

IOH

I

P3[6]

P4[0]

P4[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

40

41

42

43

44

45

46

47

48

CP

IOH

I

P0[6]

V_DD

NC

Power

Supply voltage

No connection

NC

IOH

I

P0[7]

P0[5]

P0[3]

V_SS

P0[1]

V_SS

I

Power

I

Integrating input

Ground connection

IOH

Power

Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Notes

29. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulation capacitor.

30. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

31. The center pad (CP) on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground,

SS

it must be electrically floated and not connected to any other signal

32. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 16 of 51

CY8C20XX6A/S

48-pin QFN (33 Sensing Inputs (With USB)) ^[33]

[34, 35]

Table 9. Pin Definitions – CY8C20646A, CY8C20646AS, CY8C20666A, CY8C20666AS

Figure 10. CY8C20646A, CY8C20646AS, CY8C20666A,

CY8C20666AS

Digital Analog

Name

Description

No.

1

NC

No connection

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

I/O

I

P2[7]

P2[5]

P2[3]

P2[1]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

NC

Crystal output (XOut)

Crystal input (XIn)

NC

P2[6],AI

P2[4],AI

36

35

34

33

32

31

1

2

AI , P2[7]

AI, XOut, P2[5]

AI, XIn , P2[3]

AI ,P2[1]

3

4

5

6

P2[2],AI

P2[0],AI

P4[2],AI

P4[0],AI

AI , P4[3]

QFN

(Top View)

AI , P4[1]

AI , P3[7]

AI, P3[5]

AI, P3[3]

30

29

28

27

P3[6],AI

P3[4], AI

P3[2],AI

7

8

9

10

I/O

IOHR

I²C SCL, SPI SS

I²C SDA, SPI MISO

No connection

SPI CLK

ISSP CLK^[34], I²C SCL, SPI MOSI

Ground connection

USB D+

] , AI

P3[0

XRES

P1[6], AI

AI, P3[1]

26

25

11

12

AI,I2 C SCL, SPI SS,P1[7]

NC

IOHR

Power

I/O

I

P1[3]

P1[1]

V_SS

D+

D-

USB D-

Power

IOHR

V_DD

P1[0]

Supply voltage

ISSP DATA^[34], I²C SDA, SPI

CLK^[36]

I

23

24

IOHR

I

P1[2]

P1[4]

Optional external clock input

(EXTCLK)

25

26

IOHR

I

P1[6]

Input

XRES Active high external reset with

internal pull-down

27

28

29

I/O

I

P3[0]

P3[2]

P3[4]

No.

Digital Analog

Name

Description

30

31

32

33

34

35

36

37

38

39

I/O

IOH

I

P3[6]

P4[0]

P4[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

40

41

42

43

44

45

46

47

48

CP

IOH

I

P0[6]

V_DD

NC

Power

Supply voltage

No connection

NC

IOH

I

P0[7]

P0[5]

P0[3]

V_SS

P0[1]

V_SS

Integrating input

Ground connection

Power

I

Power

IOH

Center pad must be connected to ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Notes

33. 38 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.

34. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance

(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.

35. The center pad (CP) on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground,

SS

it must be electrically floated and not connected to any other signal.

36. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 17 of 51

CY8C20XX6A/S

48-pin QFN (OCD) (33 Sensing Inputs) ^[37]

The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD). Note that this part is only used for in-circuit debugging.

[38, 39]

Table 10. Pin Definitions – CY8C20066A

No.

Figure 11. CY8C20066A

Digital Analog

Name

Description

1^[40]

2

3

4

5

6

7

8

OCDOE

P2[7]

P2[5]

P2[3]

P2[1]

P4[3]

P4[1]

P3[7]

P3[5]

P3[3]

P3[1]

P1[7]

P1[5]

CCLK

HCLK

P1[3]

P1[1]

OCD mode direction pin

I/O

I

Crystal output (XOut)

Crystal input (XIn)

OCDO

P2[6],AI

P2[4],AI

36

35

34

33

32

31

1

2

E

A

I

, P2[7]

AI, XOut, P2[5]

AI, XIn , P2[3]

AI ,P2[1]

3

4

5

6

P2[2],AI

P2[0],AI

P4[2],AI

P4[0],AI

AI ,P4[3]

QFN

(Top View)

AI , P4[1]

AI , P3[7]

30

29

28

27

9

P3[6],AI

P3[4] , AI

P3[2],AI

P3[0] , AI

7

8

10

11

12

13

14^[40]

15^[40]

16

17

AI, P3[5]

9

I/O

IOHR

AI, P3[3]

10

I²C SCL, SPI SS

I²C SDA, SPI MISO

OCD CPU clock output

OCD high speed clock output

SPI CLK.

ISSP CLK^[⁴¹^],I²C SCL, SPI

MOSI

AI, P3[1]

XRES

P1[6], AI

26

25

11

12

AI,I2 C SCL, SPI SS,P1[7]

IOHR

I

18

19

20

21

22

Power

V_SS

D+

D-

V_DD

P1[0]

Ground connection

USB D+

USB D-

I/O

Power

IOHR

Supply voltage

]

I

ISSP DATA^[⁴¹, I²C SDA, SPI

]

CLK^[⁴²

23

24

IOHR

I

P1[2]

P1[4]

No.

37

Digital

Analog

Name

Description

Optional external clock input

(EXTCLK)

IOH

I

P0[0]

25

26

P1[6]

XRES

38

IOH

I

P0[2]

P0[4]

Input

Active high external reset with 39

internal pull-down

27

28

29

30

31

32

33

34

35

36

I/O

I

P3[0]

P3[2]

P3[4]

P3[6]

P4[0]

P4[2]

P2[0]

P2[2]

P2[4]

P2[6]

40

41

IOH

I

P0[6]

V_DD

Power

Supply voltage

42^[40]

OCDO OCD even data I/O

OCDE OCD odd data output

P0[7]

P0[5]

P0[3]

V_SS

43^[40]

44

45

46

47

48

CP

IOH

I

Integrating input

Ground connection

Power

IOH

I

P0[1]

V_SS

Center pad must be connected to

ground

LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.

Notes

37. 38 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 2 pins for USB + 1 pin for modulation capacitor.

38. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.

39. The center pad (CP) on the QFN package must be connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground,

SS

it must be electrically floated and not connected to any other signal.

40. This pin (associated with OCD part only) is required for connecting the device to ICE-Cube In-Circuit Emulator for firmware debugging purpose. To know more about

®

the usage of ICE-Cube, refer to CY3215-DK PSoC IN-CIRCUIT EMULATOR KIT GUIDE.

41. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance

(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.

42. Alternate SPI clock.

Document Number: 001-54459 Rev. *T

Page 18 of 51

CY8C20XX6A/S

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C20XX6A/S PSoC devices. For the latest electrical specifi-

cations, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.

Figure 12. Voltage versus CPU Frequency

5.5V

1.71V

750kHz

3 MHz

24MHz

CPU Frequency

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 11. Absolute Maximum Ratings

Symbol

Description

Conditions

Min

Typ

Max

Units

T

Storage temperature

Higher storage temperatures reduce data

retention time. Recommended Storage

Temperature is +25 °C ± 25 °C. Extended

duration storage temperatures above 85 °C

degrades reliability.

–55

+25

+125

°C

STG

V

Supply voltage relative to V

DC input voltage

–

–0.5

–

+6.0

V

DD

SS

V

– 0.5

V

+ 0.5

IO

SS

DD

[43]

DC voltage applied to tristate

Maximum current into any port pin –

Electrostatic discharge voltage

Latch-up current

– 0.5

+ 0.5

V

IOZ

I

–25

+50

mA

V

MIO

ESD

LU

Human body model ESD

2000

–

In accordance with JESD78 standard

200

mA

Operating Temperature

Table 12. Operating Temperature

Symbol

Description

Conditions

Min

–40

0

Typ

Max

+85

70

Units

°C

T

Ambient temperature

–

A

T

Commercial temperature range

Operational die temperature

°C

C

J

The temperature rise from ambient to

junction is package specific. Refer the

Thermal Impedances on page 37. The user

must limit the power consumption to comply

with this requirement.

–40

–

+100

°C

Note

43. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above V_DD

.

Document Number: 001-54459 Rev. *T

Page 19 of 51

CY8C20XX6A/S

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 13. DC Chip-Level Specifications

Symbol

[44, 45, 46, 47]

Description

Supply voltage

Conditions

Min

Typ

Max Units

V

No USB activity. Refer the table “DC

POR and LVD Specifications” on

page 25

1.71

–

5.50

V

DD

[44, 45, 46, 47]

DDUSB

V

Operating voltage

USB activity, USB regulator enabled

USB activity, USB regulator bypassed

4.35

3.15

–

5.25

3.60

4.00

V

3.3

2.88

I

Supply current, IMO = 24 MHz Conditions are V  3.0 V, T = 25 °C,

mA

DD24

DD12

DD6

DD

A

CPU = 24 MHz. CapSense running at

12 MHz, no I/O sourcing current

I

Supply current, IMO = 12 MHz Conditions are V  3.0 V, T = 25 °C,

–

1.71

1.16

2.60

1.80

mA

DD

A

CPU = 12 MHz. CapSense running at

12 MHz, no I/O sourcing current

Supply current, IMO = 6 MHz Conditions are V  3.0 V, T = 25 °C,

DD

A

CPU = 6 MHz. CapSense running at

6 MHz, no I/O sourcing current

I

Average supply current per

sensor

One sensor scanned at 10 mS rate

One sensor scanned at 100 mS rate

One sensor scanned at 500 mS rate

–

250

25

–

A

DDAVG10

DDAVG100

DDAVG500

Average supply current per

sensor

Average supply current per

sensor

7

–

[48, 49, 50, 51, 52, 53]

Deep sleep current

V

 3.0 V, T = 25 °C, I/O regulator

0.10

1.07

1.64

1.05

1.50

–

SB0

SB1

DD

A

turned off

[48, 49, 50, 51, 52, 53]

Standby current with POR,

LVD and sleep timer

V

DD

turned off

 3.0 V, T = 25 °C, I/O regulator

A

2

Standby current with I C

Conditions are V = 3.3 V, T = 25 °C

DD A

and CPU = 24 MHz

SBI2C

enabled

Notes

44. When V_DDremains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be

slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SR_{POWER_UP}parameter.

45. If powering down in standby sleep mode, to properly detect and recover from a V_DDbrown out condition any of the following actions must be taken:

a.Bring the device out of sleep before powering down.

b.Assure that V_DDfalls below 100 mV before powering back up.

c.Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.

d.Increase the buzz rate to assure that the falling edge of V_DDis captured. The rate is configured through the PSSDC bits in the SLP_CFG register.

For the referenced registers, refer to the CY8C20X36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows

V

_DDbrown out conditions to be detected for edge rates slower than 1V/ms.

46. For USB mode, the V_DDsupply for bus-powered application should be limited to 4.35 V–5.35 V. For self-powered application, V_DDshould be 3.15 V–3.45 V.

47. For proper CapSense block functionality, if the drop in V_DDexceeds 5% of the base V_DD, the rate at which V_DDdrops should not exceed 200 mV/s. Base V_DDcan

be between 1.8 V and 5.5 V.

48. Errata: When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms (default), the device may

not come out of sleep when a sleep-ending input is received. For more information, see the “Errata” on page 45.

49. Errata: The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is in or out of transition of sleep

mode. For more information, see the “Errata” on page 45.

50. Errata: When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is used to wake the device from

sleep, the interrupt service routine (ISR) may be executed twice. For more information, see the “Errata” on page 46.

51. Errata: When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may be missed, and the

corresponding GPIO ISR not run. For more information, see the “Errata” on page 46.

52. Errata: If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be missed. For more information,

see the “Errata” on page 47.

53. Errata: Device wakes up from sleep when an analog interrupt is trigger. For more information, see the “Errata” on page 47.

Document Number: 001-54459 Rev. *T

Page 20 of 51

CY8C20XX6A/S

DC GPIO Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and

–40 °C  T  85 °C, 2.4 V to 3.0 V and –40 °C  T  85 °C, or 1.71 V to 2.4 V and –40 °C  T  85 °C, respectively. Typical

A

parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only.

Table 14. 3.0 V to 5.5 V DC GPIO Specifications

Symbol

R_PU

Description

Pull-up resistor

Conditions

Min

Typ

5.60

–

Max Units

–

4

8

–

k

V_OH1

V_OH2

V_OH3

High output voltage

Port 2 or 3 or 4 pins

I_OH< 10 A, maximum of 10 mA source

current in all I/Os

V_DD– 0.20

V_DD– 0.90

V_DD– 0.20

V

High output voltage

Port 2 or 3 or 4 pins

I_OH= 1 mA, maximum of 20 mA source

current in all I/Os

–

V

High output voltage

Port 0 or 1 pins with LDO regulator

Disabled for port 1

I_OH< 10 A, maximum of 10 mA source

current in all I/Os

V_OH4

V_OH5

V_OH6

High output voltage

I_OH= 5 mA, maximum of 20 mA source

current in all I/Os

V_DD– 0.90

2.85

–

V

Port 0 or 1 pins with LDO regulator

Disabled for port 1

High output voltage

Port 1 Pins with LDO Regulator Enabled all sourcing 5 mA

for 3 V out

I_OH< 10 A, V_DD> 3.1 V, maximum of 4 I/Os

3.00 3.30

High output voltage

Port 1 pins with LDO regulator enabled for source current in all I/Os

3 V out

I_OH= 5 mA, V_DD> 3.1 V, maximum of 20 mA

2.20

–

V_OH7

V_OH8

V_OH9

V_OH10

V_OL

High output voltage

I_OH<10A, V_DD> 2.7 V, maximum of 20 mA

2.35

1.90

1.60

1.20

–

2.50 2.75

V

Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os

High output voltage

Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os

I_OH= 2 mA, V_DD> 2.7 V, maximum of 20 mA

–

High output voltage

Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os

I_OH<10A, V_DD> 2.7 V, maximum of 20 mA

1.80 2.10

High output voltage

Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os

I_OH= 1 mA, V_DD> 2.7 V, maximum of 20 mA

–

Low output voltage

I_OL= 25 mA, V_DD> 3.3 V, maximum of

0.75

60 mA sink current on even port pins (for

example, P0[2] and P1[4]) and 60 mA sink

current on odd port pins (for example, P0[3]

and P1[5])

V_IL

V_IH

V_H

Input low voltage

–

2.00

–

0.80

V

Input high voltage

–

1

7

Input hysteresis voltage

Input leakage (Absolute Value)

Pin capacitance

80

mV

A

pF

I_IL

–

0.001

1.70

C_PIN

Package and pin dependent

Temp = 25 °C

0.50

V_ILLVT3.3Input Low Voltage with low threshold

enable set, Enable for Port1

Bit3 of IO_CFG1 set to enable low threshold

voltage of Port1 input

0.8

1.4

0.8

1.7

V

–

V

–

V

–

V_IHLVT3.3Input High Voltage with low threshold

enable set, Enable for Port1

Bit3 of IO_CFG1 set to enable low threshold

voltage of Port1 input

V_ILLVT5.5Input Low Voltage with low threshold

enable set, Enable for Port1

Bit3 of IO_CFG1 set to enable low threshold

voltage of Port1 input

V_IHLVT5.5Input High Voltage with low threshold

enable set, Enable for Port1

Bit3 of IO_CFG1 set to enable low threshold

voltage of Port1 input

V

Document Number: 001-54459 Rev. *T

Page 21 of 51

CY8C20XX6A/S

Table 15. 2.4 V to 3.0 V DC GPIO Specifications

Symbol Description

Pull-up resistor

Conditions

Min

Typ

5.60

–

Max Units

R

–

I

4

8

–

k

PU

V

High output voltage

Port 2 or 3 or 4 pins

< 10 A, maximum of 10 mA source

current in all I/Os

V

– 0.20

V

OH1

OH

DD

High output voltage

Port 2 or 3 or 4 pins

I

= 0.2 mA, maximum of 10 mA source

– 0.40

– 0.20

–

V

OH2

OH3

OH

current in all I/Os

I < 10 A, maximum of 10 mA source

OH

current in all I/Os

High output voltage

Port 0 or 1 pins with LDO regulator

Disabled for port 1

V

High output voltage

Port 0 or 1 pins with LDO regulator

Disabled for Port 1

I

= 2 mA, maximum of 10 mA source

V

– 0.50

–

V

OH4

OH

DD

current in all I/Os

V

High output voltage

I

< 10 A, V > 2.4 V, maximum of

1.50

1.80 2.10

V

OH5A

OH6A

OL

OH

DD

Port 1 pins with LDO enabled for 1.8 V out 20 mA source current in all I/Os

High output voltage = 1 mA, V > 2.4 V, maximum of 20 mA

Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os

I

1.20

–

OH

DD

Low output voltage

IOL = 10 mA, maximum of 30 mA sink

0.75

current on even port pins (for example,

P0[2] and P1[4]) and 30 mA sink current on

odd port pins (for example, P0[3] and P1[5])

V

Input low voltage

–

1.40

–

0.72

–

V

IL

IH

H

Input high voltage

Input hysteresis voltage

Input leakage (absolute value)

Capacitive load on pins

80

1

mV

I

–

1000 nA

IL

C

Package and pin dependent

Temp = 25 C

0.50

1.70

7

–

pF

V

Input Low Voltage with low threshold

enable set, Enable for Port1

Bit3 of IO_CFG1 set to enable low threshold

voltage of Port1 input

0.7

1.2

V

ILLVT2.5

IHLVT2.5

Input High Voltage with low threshold

enable set, Enable for Port1

Bit3 of IO_CFG1 set to enable low threshold

voltage of Port1 input

V

Table 16. 1.71 V to 2.4 V DC GPIO Specifications

Symbol Description

Pull-up resistor

Conditions

Min

Typ

5.60

–

Max

Units

k

R

–

4

8

–

PU

V

High output voltage

Port 2 or 3 or 4 pins

I

= 10 A, maximum of 10 mA V – 0.20

source current in all I/Os

V

OH1

OH

DD

High output voltage

Port 2 or 3 or 4 pins

I

= 0.5 mA, maximum of 10 mA V – 0.50

–

V

OH2

OH3

OH

DD

source current in all I/Os

I = 100 A, maximum of 10 mA V – 0.20

OH

source current in all I/Os

High output voltage

Port 0 or 1 pins with LDO regulator

DD

Disabled for Port 1

V

High output voltage

Port 0 or 1 Pins with LDO Regulator

Disabled for Port 1

I

= 2 mA, maximum of 10 mA source V – 0.50

–

V

OH4

OL

OH

DD

current in all I/Os

V

Low output voltage

I

= 5 mA, maximum of 20 mA sink

–

0.40

OL

current on even port pins (for example,

P0[2] and P1[4]) and 30 mA sink

current on odd port pins (for example,

P0[3] and P1[5])

Document Number: 001-54459 Rev. *T

Page 22 of 51

CY8C20XX6A/S

Table 16. 1.71 V to 2.4 V DC GPIO Specifications (continued)

Symbol Description

Input low voltage

Conditions

Min

Typ

–

Max

Units

V

–

0.30 × V

IL

IH

H

DD

V

Input high voltage

0.65 × V

–

V

DD

Input hysteresis voltage

Input leakage (absolute value)

Capacitive load on pins

–

80

1

mV

nA

pF

I

1000

7

IL

C

Package and pin dependent

temp = 25 °C

0.50

1.70

Table 17. DC Characteristics – USB Interface

Symbol

Description

USB D+ pull-up resistance

Static output high

Conditions

Min

900

1425

2.8

Typ

Max

Units



R

With idle bus

–

1575

3090

3.6

USBI

USBA

OHUSB

OLUSB

DI

R

While receiving traffic

–



V

–

V

Static output low

–

0.3

V

Differential input sensitivity

Differential input common mode range

Single ended receiver threshold

Transceiver capacitance

High Z state data line leakage

PS/2 pull-up resistance

–

0.2

V

–

0.8

–

2.5

2.0

V

CM

–

0.8

–

V

SE

C

I

–

50

pF

A



IN

On D+ or D- line

–10

3000

21.78

–

+10

7000

22.22

IO

R

–

5000

22.0

PS2

EXT

External USB series resistor

In series with each USB pin



DC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 18. DC Analog Mux Bus Specifications

Symbol

Description

Conditions

Min

–

Typ

–

Max

800

Units



R

Switch resistance to common analog bus –

SW

R

Resistance of initialization switch to V

–



GND

SS

The maximum pin voltage for measuring R_SWand R_GNDis 1.8 V

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 19. DC Comparator Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

V

Low power comparator (LPC) common Maximum voltage limited to V

mode

0.0

–

1.8

V

LPC

DD

I

LPC supply current

LPC voltage offset

–

10

3

40

30

A

LPC

V

mV

OSLPC

Document Number: 001-54459 Rev. *T

Page 23 of 51

CY8C20XX6A/S

Comparator User Module Electrical Specifications

The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the

entire device voltage and temperature operating range: –40 °C  T  85 °C, 1.71 V  V  5.5 V.

A

DD

Table 20. Comparator User Module Electrical Specifications

Symbol

Description

Conditions

50 mV overdrive

Min

–

Typ

70

Max

100

30

Units

ns

t

Comparator response time

COMP

Offset

Valid from 0.2 V to V – 0.2 V

–

2.5

20

mV

µA

DD

Current

Average DC current, 50 mV

overdrive

–

80

Supply voltage > 2 V

Supply voltage < 2 V

Power supply rejection ratio

–

0

80

40

–

dB

V

PSRR

Power supply rejection ratio

–

Input range

1.5

ADC Electrical Specifications

Table 21. ADC User Module Electrical Specifications

Symbol Description

Input

Conditions

Min

Typ

Max

Units

V

Input voltage range

–

0

–

VREFADC

5

V

pF



IN

C

R

Input capacitance

Input resistance

IIN

IN

Equivalent switched cap input

resistance for 8-, 9-, or 10-bit

resolution

1/(500fF × 1/(400fF × 1/(300fF ×

data clock) data clock) data clock)

Reference

V

ADC reference voltage

–

1.14

2.25

–

1.26

6

V

REFADC

Conversion Rate

F

Data clock

Source is chip’s internal main

oscillator. See AC Chip-Level

Specifications for accuracy

MHz

CLK

S8

8-bit sample rate

10-bit sample rate

Data clock set to 6 MHz. sample

rate = 0.001/ (2^Resolution/Data

Clock)

–

23.43

5.85

–

ksps

S10

Data clock set to 6 MHz. sample

rate = 0.001/ (2^resolution/data

clock)

DC Accuracy

RES

Resolution

Can be set to 8-, 9-, or 10-bit

8

–1

–2

0

–

10

+2

bits

LSB

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

–

INL

–

+2

LSB

E

8-bit resolution

10-bit resolution

For any resolution

3.20

12.80

–

19.20

76.80

+5

LSB

OFFSET

GAIN

0

LSB

E

Gain error

–5

%FSR

Power

I

Operating current

–

2.10

24

2.60

–

mA

dB

ADC

PSRR

Power supply rejection ratio

PSRR (V > 3.0 V)

DD

PSRR (V < 3.0 V)

30

–

DD

Document Number: 001-54459 Rev. *T

Page 24 of 51

CY8C20XX6A/S

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 22. DC POR and LVD Specifications

Symbol

Description

Conditions

Min

1.61

–

Typ

1.66

2.36

2.60

2.82

2.45

2.71

2.92

3.02

3.13

1.90

1.80

4.73

Max

1.71

2.41

2.66

2.95

2.51

2.78

2.99

3.09

3.20

2.32

1.84

4.83

Units

V

1.66 V selected in PSoC Designer

2.36 V selected in PSoC Designer

2.60 V selected in PSoC Designer

2.82 V selected in PSoC Designer

2.45 V selected in PSoC Designer

2.71 V selected in PSoC Designer

2.92 V selected in PSoC Designer

3.02 V selected in PSoC Designer

3.13 V selected in PSoC Designer

1.90 V selected in PSoC Designer

1.80 V selected in PSoC Designer

4.73 V selected in PSoC Designer

V

must be greater than or equal

DD

V

POR0

POR1

POR2

POR3

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

to 1.71 V during startup, reset

from the XRES pin, or reset from

watchdog.

–

2.40

V

[54]

2.64

2.85

2.95

[55]

[56]

3.06

1.84

[57]

1.75

4.62

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 23. DC Programming Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

V

Supply voltage for flash write

operations

–

1.71

–

5.25

V

DDIWRITE

I

Supply current during

programming or verify

–

5

–

25

mA

V

DDP

V

Input low voltage during

programming or verify

See the appropriate DC GPIO

Specifications on page 21

V

IL

ILP

V

Input high voltage during

programming or verify

See the appropriate “DC GPIO

Specifications” on page 21

V

–

V

IHP

IH

I

Input current when Applying V

to P1[0] or P1[1] during

programming or verify

Driving internal pull-down resistor

–

0.2

mA

ILP

Input current when applying V

to P1[0] or P1[1] during

programming or verify

Driving internal pull-down resistor

–

1.5

mA

IHP

V

Output low voltage during

programming or verify

–

V

+ 0.75

V

OLP

SS

Output high voltage during

programming or verify

See

Specifications on page 21. For

> 3 V use V in Table 12 on

appropriate

DC

GPIO

V

DD

OHP

OH

V

DD

OH4

page 19.

Flash

Flash write endurance

Flash data retention

Erase/write cycles per block

50,000

20

–

ENPB

Following maximum Flash write

cycles; ambient temperature of 55 °C

Years

DR

Notes

54. Always greater than 50 mV above V_PPOR1voltage for falling supply.

55. Always greater than 50 mV above V_PPOR2voltage for falling supply.

56. Always greater than 50 mV above V_PPOR3voltage for falling supply.

57. Always greater than 50 mV above V_PPOR0voltage for falling supply.

Document Number: 001-54459 Rev. *T

Page 25 of 51

CY8C20XX6A/S

2

DC I C Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and

–40 °C  T  85 °C, 2.4 V to 3.0 V and –40 °C  T  85 °C, or 1.71 V to 2.4 V and –40 °C  T  85 °C, respectively. Typical

A

parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.

Table 24. DC I²C Specifications

Symbol

Description

Input low level

Conditions

3.1 V ≤ V ≤ 5.5 V

Min

Typ

Max

Units

V

–

0.25 × V

V

ILI2C

DD

2.5 V ≤ V ≤ 3.0 V

–

0.3 × V

–

V

DD

1.71 V ≤ V ≤ 2.4 V

DD

V

Input high level

1.71 V ≤ V ≤ 5.5 V

0.65 × V

DD

IHI2C

DD

DC Reference Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and

–40 °C  T  85 °C, 2.4 V to 3.0 V and –40 °C  T  85 °C, or 1.71 V to 2.4 V and –40 °C  T  85 °C, respectively. Typical

A

parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.

Table 25. DC Reference Buffer Specifications

Symbol

Description

Conditions

1.7 V ≤ V ≤ 5.5 V

Min

Typ

Max

Units

V

Reference buffer output

1

–

1.05

V

Ref

DD

Reference buffer output

1.7 V ≤ V ≤ 5.5 V

1.2

–

1.25

V

RefHi

DD

DC IDAC Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 26. DC IDAC Specifications

Symbol

IDAC_DNL

IDAC_INL

Description

Differential nonlinearity

Integral nonlinearity

Range = 0.5x

Min

–4.5

–5

Typ

–

Max

+4.5

+5

Units

LSB

Notes

–

LSB

IDAC_Gain

(Source)

6.64

14.5

42.7

91.1

184.5

–

22.46

47.8

92.3

170

µA DAC setting = 128 dec.

Not recommended for CapSense

Range = 1x

–

µA

applications.

Range = 2x

–

Range = 4x

–

µA DAC setting = 128 dec

Range = 8x

–

426.9

Document Number: 001-54459 Rev. *T

Page 26 of 51

CY8C20XX6A/S

AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 27. AC Chip-Level Specifications

Symbol

Description

IMO frequency at 24 MHz Setting

IMO frequency at 12 MHz setting

IMO frequency at 6 MHz setting

CPU frequency

Conditions

Min

22.8

11.4

5.7

0.75

15

Typ

24

12

6.0

–

Max

25.2

12.6

6.3

25.20

50

Units

MHz

kHz

%

F

–

V

IMO24

IMO12

IMO6

CPU

ILO frequency

32

50

–

32K1

ILO untrimmed frequency

Duty cycle of IMO

13

82

32K_U

DC

SR

40

60

IMO

ILO duty cycle

40

60

%

ILO

Power supply slew rate

slew rate during power-up

DD

–

250

–

V/ms

ms

POWER_UP

t

External reset pulse width at power-up After supply voltage is valid

1

–

XRST

External reset pulse width after

Applies after part has booted

10

–

s

XRST2

[58]

power-up

t

Startup time of ECO

N=32

–

1

–

s

OS

[59]

6 MHz IMO cycle-to-cycle jitter (RMS)

0.7

4.3

6.7

ns

JIT_IMO

6 MHz IMO long term N (N = 32)

cycle-to-cycle jitter (RMS)

29.3

6 MHz IMO period jitter (RMS)

–

0.7

0.5

2.3

3.3

5.2

5.6

ns

12 MHz IMO cycle-to-cycle jitter (RMS)

12 MHz IMO long term N (N = 32)

cycle-to-cycle jitter (RMS)

12 MHz IMO period jitter (RMS)

–

0.4

1.0

1.4

2.6

8.7

6.0

ns

24 MHz IMO cycle-to-cycle jitter (RMS)

24 MHz IMO long term N (N = 32)

cycle-to-cycle jitter (RMS)

24 MHz IMO period jitter (RMS)

–

0.6

4.0

ns

Notes

58. The minimum required XRES pulse length is longer when programming the device (see Table 33 on page 30).

59. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.

Document Number: 001-54459 Rev. *T

Page 27 of 51

CY8C20XX6A/S

AC GPIO Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 28. AC GPIO Specifications

Symbol

Description

Conditions

Min

Typ

Max

6 MHz for

Units

F

GPIO operating frequency

Normal strong mode Port 0, 1

0

–

MHz

GPIO

1.71 V <V < 2.40 V

DD

0

–

12 MHz for

MHz

ns

2.40 V < V < 5.50 V

DD

t

Rise time, strong mode, Cload = 50 pF

Port 2 or 3 or 4 pins

V

= 3.0 to 3.6 V, 10% to 90% 15

80

50

80

50

70

RISE23

RISE23L

RISE01

RISE01L

FALL

DD

Rise time, strong mode low supply,

Cload = 50 pF, Port 2 or 3 or 4 pins

= 1.71 to 3.0 V, 10% to 90% 15

= 3.0 to 3.6 V, 10% to 90% 10

ns

Rise time, strong mode, Cload = 50 pF

Ports 0 or 1

ns

LDO enabled or disabled

Rise time, strong mode low supply,

Cload = 50 pF, Ports 0 or 1

V

= 1.71 to 3.0 V, 10% to 90% 10

ns

DD

LDO enabled or disabled

Fall time, strong mode, Cload = 50 pF

all ports

V

= 3.0 to 3.6 V, 10% to 90% 10

ns

DD

Fall time, strong mode low supply,

Cload = 50 pF, all ports

V

= 1.71 to 3.0 V, 10% to 90% 10

ns

FALLL

Figure 13. GPIO Timing Diagram

90%

GPIO Pin

Output

Voltage

10%

t_RISE23

t_RISE01

t_RISE23L

t_RISE01L

t_FALL

t_FALLL

Document Number: 001-54459 Rev. *T

Page 28 of 51

CY8C20XX6A/S

Table 29. AC Characteristics – USB Data Timings

Symbol

Description

Full speed data rate

Receiver jitter tolerance

FS Driver jitter

Conditions

Average bit rate

Min

12 – 0.25%

–18.5

–9.0

Typ

12

–

Max

Units

t

12 + 0.25% MHz

DRATE

To next transition

To pair transition

To next transition

To pair transition

To SE0 transition

18.5

9

ns

JR1

–

JR2

–3.5

–

3.5

4.0

5

DJ1

FS Driver jitter

–4.0

–

DJ2

Source jitter for differential

transition

–2.0

–

FDEOP

t

Source SE0 interval of EOP

Receiver SE0 interval of EOP

–

160.0

82.0

–

175

–

ns

FEOPT

FEOPR

FST

Width of SE0 interval during

differential transition

14

Table 30. AC Characteristics – USB Driver

Symbol

Description

Transition rise time

Conditions

Min

4

Typ

–

Max

20

Units

ns

t

50 pF

–

FR

Transition fall time

4

–

20

ns

FF

[60]

Rise/fall time matching

Output signal crossover voltage

90

1.30

–

111

2.00

%

FRFM

V

–

V

CRS

AC Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 31. AC Low Power Comparator Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

t

Comparator response time,

50 mV overdrive

50 mV overdrive does not include

offset voltage.

–

100

ns

LPC

AC External Clock Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 32. AC External Clock Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

F

Frequency (external oscillator

frequency)

–

0.75

–

25.20

MHz

OSCEXT

High period

–

20.60

150

–

5300

ns

s

Low period

–

Power-up IMO to switch

Note

60. T_FRFMis not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3 V. This condition does not affect USB communications.

Signal integrity tests show an excellent eye diagram at 3.15 V.

Document Number: 001-54459 Rev. *T

Page 29 of 51

CY8C20XX6A/S

AC Programming Specifications

Figure 14. AC Waveform

SCLK (P1[1])

T_RSCLK

T_FSCLK

SDATA (P1[0])

T_SSCLK

T_HSCLK

T_DSCLK

The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 33. AC Programming Specifications

Symbol

Description

Rise time of SCLK

Conditions

Min

1

Typ

–

Max

20

–

Units

ns

t

–

RSCLK

Fall time of SCLK

1

–

ns

FSCLK

SSCLK

HSCLK

Data setup time to falling edge of SCLK

40

0

–

ns

Data hold time from falling edge of SCLK –

–

ns

F

Frequency of SCLK

–

8

MHz

ms

ns

SCLK

t

Flash erase time (block)

Flash block write time

–

18

25

60

85

130

–

ERASEB

WRITE

DSCLK

DSCLK3

DSCLK2

XRST3

–

Data out delay from falling edge of SCLK 3.6  V

–

DD

Data out delay from falling edge of SCLK 3.0  V  3.6

–

ns

DD

Data out delay from falling edge of SCLK 1.71  V  3.0

–

ns

DD

External reset pulse width after power-up Required to enter programming

mode when coming out of sleep

300

–

s

t

XRES pulse length

–

300

0.1

–

1

s

ms

XRES

[61]

V

stable to wait-and-poll hold off

stable to XRES assertion delay

VDDWAIT

DD

14.27

0.01

3.20

–

VDDXRES

SDATA high pulse time

200

19.60

POLL

[61]

“Key window” time after a V ramp

acquire event, based on 256 ILO clocks.

ACQ

DD

[61]

t

“Key window” time after an XRES event,

based on 8 ILO clocks

–

98

–

615

s

XRESINI

Note

61. Valid from 5 to 50 °C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67, CY8C20X47,

CY8C20X37, Programming Spec for more details.

Document Number: 001-54459 Rev. *T

Page 30 of 51

CY8C20XX6A/S

2

AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 34. AC Characteristics of the I²C SDA and SCL Pins

Standard Mode

Fast Mode

Symbol

Description

Units

Min

0

Max

100

–

Min

Max

400

–

f

t

SCL clock frequency

0

kHz

µs

SCL

Holdtime(repeated)STARTcondition. Afterthisperiod, thefirst

clock pulse is generated

4.0

0.6

HD;STA

t

LOW period of the SCL clock

4.7

4.0

4.7

0

–

1.3

0.6

0

–

µs

ns

µs

ns

LOW

HIGH Period of the SCL clock

HIGH

Setup time for a repeated START condition

Data hold time

–

SU;STA

HD;DAT

SU;DAT

SU;STO

BUF

3.45

–

0.90

–

[62]

Data setup time

250

4.0

4.7

–

100

Setup time for STOP condition

–

0.6

1.3

0

–

Bus free time between a STOP and START condition

Pulse width of spikes are suppressed by the input filter

–

50

SP

Figure 15. Definition for Timing for Fast/Standard Mode on the I²C Bus

Note

62. A Fast-Mode I²C-bus device can be used in a standard mode I²C-bus system, but the requirement t_SU;DAT 250 ns must then be met. This automatically be the

case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line t_rmax+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the Standard-Mode I²C-bus specification) before the SCL line is released.

Document Number: 001-54459 Rev. *T

Page 31 of 51

CY8C20XX6A/S

Table 35. SPI Master AC Specifications

Symbol

Description

Conditions

Min

Typ

Max

Units

F

SCLK clock frequency

V

2.4 V

–

6

3

MHz

SCLK

DD

< 2.4 V

DC

t

SCLK duty cycle

–

50

–

%

MISO to SCLK setup time

V

 2.4 V

< 2.4 V

60

100

–

ns

SETUP

DD

t

SCLK to MISO hold time

SCLK to MOSI valid time

MOSI high time

–

40

–

40

–

ns

HOLD

OUT_VAL

OUT_H

40

Figure 16. SPI Master Mode 0 and 2

SPI Master, modes 0 and 2

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 0)

SCLK

(mode 2)

T_SETUP

T_HOLD

MISO

(input)

LSB

MSB

T_{OUT_SU}

T_{OUT_H}

MOSI

(output)

Figure 17. SPI Master Mode 1 and 3

SPI Master, modes 1 and 3

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 1)

SCLK

(mode 3)

T_SETUP

T_HOLD

MISO

(input)

MSB

LSB

T_{OUT_SU}

T_{OUT_H}

MOSI

(output)

LSB

MSB

Document Number: 001-54459 Rev. *T

Page 32 of 51

CY8C20XX6A/S

Table 36. SPI Slave AC Specifications

Symbol

Description

SCLK clock frequency

SCLK low time

Conditions

Min

Typ

–

Max

4

Units

MHz

ns

F

–

SCLK

t

42

–

LOW

SCLK high time

42

–

ns

HIGH

MOSI to SCLK setup time

SCLK to MOSI hold time

SS high to MISO valid

SCLK to MISO valid

SS high time

30

–

ns

SETUP

50

–

ns

HOLD

–

153

125

–

ns

SS_MISO

SCLK_MISO

SS_HIGH

SS_CLK

CLK_SS

–

ns

50

–

ns

Time from SS low to first SCLK

Time from last SCLK to SS high

2/SCLK

–

ns

–

ns

Figure 18. SPI Slave Mode 0 and 2

SPI Slave, modes 0 and 2

T_{SS_HIGH}

T_{CLK_SS}

T_{SS_CLK}

/SS

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 0)

SCLK

(mode 2)

T_{OUT_H}

T_{SS_MISO}

MISO

(output)

T_SETUP

T_HOLD

MOSI

(input)

LSB

MSB

Figure 19. SPI Slave Mode 1 and 3

SPI Slave, modes 1 and 3

T_{SS_CLK}

T_{CLK_SS}

/SS

1/F_SCLK

T_HIGH

T_LOW

SCLK

(mode 1)

SCLK

(mode 3)

T_{OUT_H}

T_{SCLK_MISO}

T_{SS_MISO}

MISO

(output)

MSB

LSB

T_SETUP

T_HOLD

MOSI

(input)

MSB

LSB

Document Number: 001-54459 Rev. *T

Page 33 of 51

CY8C20XX6A/S

Packaging Information

This section illustrates the packaging specifications for the CY8C20XX6A/S PSoC device, along with the thermal impedances for each

package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Figure 20. 16-pin QFN (No E-Pad) (3 × 3 × 0.6 mm) LG16A (Sawn) Package Outline, 001-09116

001-09116 *H

Figure 21. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937

001-13937 *E

Document Number: 001-54459 Rev. *T

Page 34 of 51

CY8C20XX6A/S

Figure 22. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168

001-42168 *E

Figure 23. 48-pin SSOP (300 Mils) O483 Package Outline, 51-85061

51-85061 *F

Document Number: 001-54459 Rev. *T

Page 35 of 51

CY8C20XX6A/S

Figure 24. 48-pin QFN (7 × 7 × 1.0 mm) LT48A 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191

001-13191 *G

Figure 25. 48-pin QFN (6 × 6 × 0.6 mm) LQ48A 4.6 × 4.6 E-Pad (Sawn) Package Outline, 001-57280

001-57280 *E

Important Notes

■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

■ Pinned vias for thermal conduction are not required for the low power PSoC device.

Document Number: 001-54459 Rev. *T

Page 36 of 51

CY8C20XX6A/S

Thermal Impedances

Table 37. Thermal Impedances per Package

[63]

Package

Typical _JA

33 C/W

21 C/W

20 C/W

69 C/W

Typical _JC

16-pin QFN (No Center Pad)

–

[64]

24-pin QFN

–

[64]

32-pin QFN

–

48-pin SSOP

–

[64]

48-pin QFN (6 × 6 × 0.6 mm)

25.20 C/W

18 C/W

3.04 C/W

[64]

48-pin QFN (7 × 7 × 1.0 mm)

–

30-ball WLCSP

54 C/W

Capacitance on Crystal Pins

Table 38. Typical Package Capacitance on Crystal Pins

Package

32-pin QFN

48-pin QFN

Package Capacitance

3.2 pF

3.3 pF

Solder Reflow Specifications

Table 39 shows the solder reflow temperature limits that must not be exceeded.

Table 39. Solder Reflow Specifications

Package

Maximum Peak Temperature (T_C) Maximum Time above T_C– 5 °C

16-pin QFN

24-pin QFN

32-pin QFN

48-pin SSOP

260 C

30 seconds

48-pin QFN (6 × 6 × 0.6 mm)

48-pin QFN (7 × 7 × 1.0 mm)

30-ball WLCSP

Notes

63. T_J= T_A+ Power × 

.

JA

64. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.

Document Number: 001-54459 Rev. *T

Page 37 of 51

CY8C20XX6A/S

■ 28-pin CY8C29466A-24PXI PDIP PSoC Device Sample

■ 28-pin CY8C27443A-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

Development Tool Selection

Software

PSoC Designer™

■ Getting Started Guide

At the core of the PSoC development software suite is PSoC

Designer. Utilized by thousands of PSoC developers, this robust

software has been facilitating PSoC designs for over half a

decade. PSoC Designer is available free of charge at

http://www.cypress.com.

■ USB 2.0 Cable

CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, and plenty of

breadboarding space to meet all of your evaluation needs. The

kit includes:

PSoC Programmer

Flexible enough to be used on the bench in development, yet

suitable for factory programming, PSoC Programmer works

either as a standalone programming application or it can operate

directly from PSoC Designer. PSoC Programmer software is

compatible with both PSoC ICE-Cube In-Circuit Emulator and

PSoC MiniProg. PSoC Programmer is available free of charge

at http://www.cypress.com.

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

Development Kits

All development kits are sold at the Cypress Online Store.

■ USB 2.0 Cable

CY3215-DK Basic Development Kit

CY3280-20X66 Universal CapSense Controller

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software

interface enables users to run, halt, and single step the

processor and view the content of specific memory locations.

PSoC Designer supports the advance emulation features also.

The kit includes:

The CY3280-20X66 CapSense Controller Kit is designed for

easy prototyping and debug of CY8C20XX6A CapSense Family

designs with pre-defined control circuitry and plug-in hardware.

Programming hardware and an I2C-to-USB bridge are included

for tuning and data acquisition.

■ PSoC Designer Software CD

The kit includes:

■ ICE-Cube In-Circuit Emulator

■ CY3280-20X66 CapSense Controller Board

■ CY3240-I2USB Bridge

■ ICE Flex-Pod for CY8C29X66A Family

■ Cat-5 Adapter

■ CY3210 MiniProg1 Programmer

■ USB 2.0 Retractable Cable

■ CY3280-20X66 Kit CD

■ Mini-Eval Programming Board

■ 110 ~ 240 V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

Device Programmers

All device programmers are purchased from the Cypress Online

Store.

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466A-24PXI 28-PDIP Chip Samples

CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular

programmer and the MiniProg1 programming unit. The modular

programmer includes three programming module cards and

supports multiple Cypress products. The kit includes:

Evaluation Tools

All evaluation tools are sold at the Cypress Online Store.

CY3210-MiniProg1

■ Modular Programmer Base

■ Three Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

The CY3210-MiniProg1 kit enables the user to program PSoC

devices via the MiniProg1 programming unit. The MiniProg is a

small, compact prototyping programmer that connects to the PC

via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ USB 2.0 Cable

Document Number: 001-54459 Rev. *T

Page 38 of 51

CY8C20XX6A/S

CY3207ISSP In-System Serial Programmer (ISSP)

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production programming environment.

Note that CY3207ISSP needs special software and is not

compatible with PSoC Programmer. The kit includes:

■ 110 ~ 240 V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

Accessories (Emulation and Programming)

Table 40. Emulation and Programming Accessories

[65]

[66]

[67]

Part Number

Pin Package

Flex-Pod Kit

Foot Kit

Adapter

CY8C20236A-24LKXI

CY8C20246A-24LKXI

CY8C20246AS-24LKXI

CY8C20336A-24LQXI

CY8C20346A-24LQXI

CY8C20346AS-24LQXI

CY8C20396A-24LQXI

CY8C20436A-24LQXI

CY8C20446A-24LQXI

CY8C20446AS-24LQXI

CY8C20466A-24LQXI

CY8C20466AS-24LQXI

CY8C20496A-24LQXI

CY8C20536A-24PVXI

CY8C20546A-24PVXI

CY8C20566A-24PVXI

16-pin QFN (No E-Pad) CY3250-20246QFN

16-pin QFN (No E-Pad)

CY3250-20246QFN-POD

Not Supported

See note 64

See note 67

24-pin QFN

32-pin QFN

48-pin SSOP

CY3250-20346QFN

CY3250-20346QFN-POD

Not Supported

See note 64

See note 67

Not Supported

CY3250-20466QFN

CY3250-20466QFN-POD

Not Supported

See note 64

See note 67

CY3250-20466QFN

CY3250-20466QFN-POD

Not Supported

See note 67

Not Supported

CY3250-20566

CY3250-20566-POD

See note 67

Third Party Tools

Several tools have been specially designed by third-party vendors to accompany PSoC devices during development and production.

Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.

Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC

device, refer Application Note Debugging - Build a PSoC Emulator into Your Board – AN2323.

Notes

65. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

66. Foot kit includes surface mount feet that can be soldered to the target PCB.

67. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Document Number: 001-54459 Rev. *T

Page 39 of 51

CY8C20XX6A/S

Ordering Information

The following table lists the CY8C20XX6A/S PSoC devices' key package features and ordering codes.

Table 41. PSoC Device Key Features and Ordering Information

Flash SRAM CapSense Digital

XRES

Analog

Inputs

Package

Ordering Code

USB ADC

[68]

(Bytes) (Bytes) Blocks I/O Pins

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad)

CY8C20236A-24LKXI

8 K

1 K

2 K

1

13

Yes No Yes

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad) (Tape and Reel)

CY8C20236A-24LKXIT

CY8C20246A-24LKXI

CY8C20246AS-24LKXI

CY8C20246A-24LKXIT

CY8C20246AS-24LKXIT

8 K

13

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad)

16 K

13

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad)

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad) (Tape and Reel)

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad) (Tape and Reel)

24-pin (4 × 4 × 0.6 mm) QFN

CY8C20336A-24LQXI

CY8C20336A-24LQXIT

8 K

1 K

1

20

Yes No Yes

24-pin (4 × 4 × 0.6 mm) QFN

(Tape and Reel)

24-pin (4 × 4 × 0.6 mm) QFN

CY8C20346A-24LQXI

CY8C20346AS-24LQXI

CY8C20346A-24LQXIT

16 K

2 K

1

20

Yes No Yes

20

24-pin (4 × 4 × 0.6 mm) QFN

(Tape and Reel)

24-pin (4 × 4 × 0.6 mm) QFN

(Tape and Reel)

CY8C20346AS-24LQXIT

16 K

2 K

1

20

Yes No Yes

20

24-pin (4 × 4 × 0.6 mm) QFN

CY8C20396A-24LQXI

CY8C20396A-24LQXIT

16 K

2 K

1

19

Yes Yes Yes

24-pin (4 × 4 × 0.6 mm) QFN

(Tape and Reel)

32-pin (5 × 5 × 0.6 mm) QFN

CY8C20436A-24LQXI

CY8C20436A-24LQXIT

8 K

1 K

1

28

Yes No Yes

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

32-pin (5 × 5 × 0.6 mm) QFN

CY8C20446A-24LQXI

CY8C20446AS-24LQXI

CY8C20446A-24LQXIT

16 K

2 K

1

28

Yes No Yes

28

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

CY8C20446AS-24LQXIT

16 K

2 K

1

28

Yes No Yes

28

32-pin (5 × 5 × 0.6 mm) QFN

CY8C20466A-24LQXI

CY8C20466AS-24LQXI

CY8C20466A-24LQXIT

32 K

2 K

1

28

Yes No Yes

28

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

CY8C20466AS-24LQXIT

32 K

2 K

1

28

Yes No Yes

28

32-pin (5 × 5 × 0.6 mm) QFN

CY8C20496A-24LQXI

CY8C20496A-24LQXIT

16 K

2 K

1

25

Yes Yes Yes

25

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

Document Number: 001-54459 Rev. *T

Page 40 of 51

CY8C20XX6A/S

Table 41. PSoC Device Key Features and Ordering Information (continued)

Flash SRAM CapSense Digital

(Bytes) (Bytes) Blocks I/O Pins

XRES

Analog

Inputs

Package

Ordering Code

USB ADC

[68]

[69]

48-pin SSOP

CY8C20536A-24PVXI

8 K

1 K

2 K

1 K

1

34

36

Yes No Yes

34

[69]

48-pin SSOP (Tape and Reel)

CY8C20536A-24PVXIT

34

[69]

48-pin SSOP

CY8C20546A-24PVXI

16 K

32 K

8 K

34

48-pin SSOP (Tape and Reel)

CY8C20546A-24PVXIT

34

[69]

48-pin SSOP

CY8C20566A-24PVXI

CY8C20566A-24PVXIT

CY8C20636A-24LQXI

CY8C20636A-24LQXIT

34

48-pin SSOP (Tape and Reel)

48-pin (6 × 6 × 0.6 mm) QFN

34

36

48-pin (6 × 6 × 0.6 mm) QFN

(Tape and Reel)

8 K

36

[69]

48-pin (7 × 7 × 1.0 mm) QFN

CY8C20636A-24LTXI

CY8C20636A-24LTXIT

8 K

1 K

1

36

Yes No Yes

36

[69]

48-pin (7 × 7 × 1.0 mm) QFN

[69]

(Tape and Reel)

48-pin (6 × 6 × 0.6 mm) QFN

CY8C20646A-24LQXI

CY8C20646A-24LQXIT

16 K

2 K

1

36

Yes Yes Yes

36

48-pin (6 × 6 × 0.6 mm) QFN

(Tape and Reel)

[69]

48-pin (7 × 7 × 1.0 mm) QFN

CY8C20646A-24LTXI

CY8C20646A-24LTXIT

16 K

2 K

1

36

Yes Yes Yes

36

[69]

48-pin (7 × 7 × 1.0 mm) QFN

[69]

(Tape and Reel)

48-pin (6 × 6 × 0.6 mm) QFN

CY8C20666A-24LQXI

CY8C20666A-24LQXIT

32 K

2 K

1

36

Yes Yes Yes

36

48-pin (6 × 6 × 0.6 mm) QFN

(Tape and Reel)

[69]

48-pin (7 × 7 × 1.0 mm) QFN

CY8C20666A-24LTXI

CY8C20666AS-24LTXI

CY8C20666A-24LTXIT

32 K

2 K

1

36

Yes Yes Yes

36

[69]

(Tape and Reel)

[69]

48-pin (7 × 7 × 1.0 mm) QFN

(Tape and Reel)

CY8C20666AS-24LTXIT

32 K

2 K

1

36

Yes Yes Yes

36

[69]

[68]

48-pin (7 × 7 × 1.0 mm) QFN

CY8C20066A-24LTXI

[68]

(OCD)

30-ball WLCSP

CY8C20746A-24FDXC

16 K

32 K

1 K

2 K

1

27

Yes No Yes

27

30-ball WLCSP (Tape and Reel) CY8C20746A-24FDXCT

30-ball WLCSP CY8C20766A-24FDXC

30-ball WLCSP (Tape and Reel) CY8C20766A-24FDXCT

27

20

24-pin (4 × 4 × 0.6 mm) QFN

CY8C20336AN-24LQXI

CY8C20336AN-24LQXIT

8 K

1 K

1

20

Yes No No

24-pin (4 × 4 × 0.6 mm) QFN

(Tape and Reel)

32-pin (5 × 5 × 0.6 mm) QFN

CY8C20436AN-24LQXI

CY8C20436AN-24LQXIT

8 K

1 K

1

28

Yes No No

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

[69]

48-pin (7 × 7 × 1.0 mm) QFN

(Tape and Reel)

CY8C20636AN-24LTXI

CY8C20636AN-24LTXIT

8 K

1 K

1

36

Yes No No

[69]

Document Number: 001-54459 Rev. *T

Page 41 of 51

CY8C20XX6A/S

Table 41. PSoC Device Key Features and Ordering Information (continued)

Flash SRAM CapSense Digital

(Bytes) (Bytes) Blocks I/O Pins

XRES

Analog

Inputs

Package

Ordering Code

USB ADC

[68]

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad)

CY8C20246AS-24LKXI

16 K

2 K

1

13

Yes No Yes

16-pin (3 × 3 × 0.6 mm) QFN

(no E-Pad, Tape and Reel)

CY8C20246AS-24LKXIT

13

24-pin (4 × 4 × 0.6 mm) QFN

CY8C20346AS-24LQXI

CY8C20346AS-24LQXIT

16 K

2 K

1

20

Yes No Yes

24-pin (4 × 4 × 0.6 mm) QFN

(Tape and Reel)

32-pin (5 × 5 × 0.6 mm) QFN

CY8C20446AS-24LQXI

CY8C20446AS-24LQXIT

16 K

2 K

1

28

Yes No Yes

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

32-pin (5 × 5 × 0.6 mm) QFN

CY8C20466AS-24LQXI

CY8C20466AS-24LQXIT

32 K

2 K

1

28

Yes No Yes

32-pin (5 × 5 × 0.6 mm) QFN

(Tape and Reel)

48-pin (6 × 6 × 0.6 mm) QFN

CY8C20666AS-24LQXI

CY8C20666AS-24LQXIT

32 K

2 K

1

36

Yes Yes Yes

48-pin (6 × 6 × 0.6 mm) QFN

(Tape and Reel)

[69]

48-pin (7 × 7 × 1.0 mm) QFN

CY8C20666AS-24LTXI

CY8C20666AS-24LTXIT

32 K

2 K

1

36

Yes Yes Yes

[69]

(Tape and Reel)

48-pin (6 × 6 × 0.6 mm) QFN

CY8C20646AS-24LQXI

CY8C20646AS-24LQXIT

16 K

2 K

1

36

Yes Yes Yes

48-pin (6 × 6 × 0.6 mm) QFN

(Tape and Reel)

[69]

48-pin (7 × 7 × 1.0 mm) QFN

CY8C20646AS-24LTXI

CY8C20646AS-24LTXIT

16 K

2 K

1

36

Yes Yes Yes

[69]

48-pin (7 × 7 × 1.0 mm) QFN

[69]

(Tape and Reel)

Ordering Code Definitions

CY 20 XX6AX

8

C

-

24 XX

X

T

Tape and Reel

Temperature range: X = C or I

C = Commercial; I = Industrial

Pb-free

Package Type: XX = LK or LQ or PV or LT or FD

LK = 16-pin QFN (no E-Pad)

LQ = 24-pin QFN, 32-pin QFN, 48-pin (6 × 6 × 0.6 mm) QFN

PV = 48-pin SSOP

LT = 48-pin (7 × 7 × 1.0 mm) QFN

FD = 30-ball WLCSP

Speed Grade: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = PSoC

Company ID: CY = Cypress

Notes

68. Dual-function Digital I/O Pins also connect to the common analog mux.

69. Not Recommended for New Designs.

Document Number: 001-54459 Rev. *T

Page 42 of 51

CY8C20XX6A/S

Acronyms

Reference Documents

Table 42. Acronyms Used in this Document

■ Technical reference manual for CY8C20xx6 devices

Acronym

AC

Description

alternating current

■ In-system Serial Programming (ISSP) protocol for 20xx6

(AN2026C)

ADC

API

CMOS

CPU

DAC

DC

analog-to-digital converter

application programming interface

complementary metal oxide semiconductor

central processing unit

digital-to-analog converter

direct current

■ Host Sourced Serial Programming for 20xx6 devices

(AN59389)

Document Conventions

Units of Measure

EOP

FSR

end of packet

full scale range

Table 43. Units of Measure

Symbol

°C

dB

fF

Unit of Measure

GPIO

GUI

general purpose input/output

graphical user interface

inter-integrated circuit

in-circuit emulator

digital analog converter current

internal low speed oscillator

internal main oscillator

input/output

in-system serial programming

liquid crystal display

low dropout (regulator)

least-significant bit

low voltage detect

micro-controller unit

mega instructions per second

master in slave out

master out slave in

degree Celsius

decibels

femtofarad

gram

2

I C

ICE

IDAC

ILO

IMO

I/O

ISSP

LCD

LDO

LSB

g

Hz

KB

Kbit

KHz

Ksps

k

MHz

M

A

F

H

s

W

mA

ms

mV

nA

nF

ns

hertz

1024 bytes

1024 bits

kilohertz

kilo samples per second

kilohm

megahertz

megaohm

LVD

microampere

microfarad

microhenry

microsecond

microwatt

milliampere

millisecond

millivolt

nanoampere

nanofarad

MCU

MIPS

MISO

MOSI

MSB

OCD

POR

PPOR

PSRR

most-significant bit

on-chip debugger

power on reset

precision power on reset

power supply rejection ratio

PWRSYS power system

®

nanosecond

nanovolt

ohm

PSoC

SLIMO

SRAM

SNR

QFN

SCL

SDA

SDATA

SPI

SS

SSOP

TC

Programmable System-on-Chip

nV

W

slow internal main oscillator

static random access memory

signal to noise ratio

quad flat no-lead

serial I2C clock

serial I2C data

serial ISSP data

serial peripheral interface

slave select

shrink small outline package

test controller

pA

pF

pp

ppm

ps

sps

s

V

picoampere

picofarad

peak-to-peak

parts per million

picosecond

samples per second

sigma: one standard deviation

volt

W

watt

USB

universal serial bus

USB Data+

USB Data–

wafer level chip scale package

crystal

USB D+

USB D–

WLCSP

XTAL

Document Number: 001-54459 Rev. *T

Page 43 of 51

CY8C20XX6A/S

Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).

Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended

lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.

Glossary

Crosspoint connection

Differential non-linearity

Connection between any GPIO combination via analog multiplexer bus.

Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly

one LSB apart. Differential non-linearity is a measure of the worst case deviation from the

ideal 1 LSB step.

Hold time

Hold time is the time following a clock event during which the data input to a latch or flip-flop

must remain stable in order to guarantee that the latched data is correct.

2

I C

It is a serial multi-master bus used to connect low speed peripherals to MCU.

Integral nonlinearity

It is a term describing the maximum deviation between the ideal output of a DAC/ADC and

the actual output level.

Latch-up current

Current at which the latch-up test is conducted according to JESD78 standard (at 125

degree Celsius)

Power supply rejection ratio (PSRR)

The PSRR is defined as the ratio of the change in supply voltage to the corresponding

change in output voltage of the device.

Scan

The conversion of all sensor capacitances to digital values.

Setup time

Period required to prepare a device, machine, process, or system for it to be ready to

function.

Signal-to-noise ratio

SPI

The ratio between a capacitive finger signal and system noise.

Serial peripheral interface is a synchronous serial data link standard.

Document Number: 001-54459 Rev. *T

Page 44 of 51

CY8C20XX6A/S

Errata

®

This section describes the errata for the PSoC CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families. Details include errata

trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Repre-

sentative if you have questions.

Qualification Status

Product Status: Production released.

Errata Summary

The following Errata items apply to CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H families.

1. Wakeup from sleep may intermittently fail

■ Problem Definition

When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms

(default), the device may not come out of sleep when a sleep-ending input is received.

■ Parameters Affected

None

■ Trigger Condition(S)

By default, when the device is in the Standby or I2C_USB sleep modes, the bandgap circuit is powered-up approximately every 8

ms to facilitate detection of POR or LVD events. This interval can be lengthened or the periodic power-up disabled to reduce sleep

current by setting the ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively. If

the bandgap circuit refresh interval is set longer than the default 8 ms, the device may fail to wakeup from sleep and enter a locked

up state that can only be recovered by Watchdog Reset, XRES, or POR.

■ Scope of Impact

The trigger conditions outlined above may cause the device to never wakeup.

■ Workaround

Prior to entering Standby or I2C_USB sleep modes, do not lengthen or disable the bandgap refresh interval by manipulating the

ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively.

■ Fix Status

This issue will not be corrected in the next silicon revision.

2. I²C Errors

■ Problem Definition

2

The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is

transitioning in to or out of sleep mode.

■ Parameters Affected

2

Affects reliability of I C communication to device, and between I C master and third party I C slaves.

■ Trigger Condition(S)

Triggered by transitions into and out of the device’s sleep mode.

■ Scope of Impact

2

Data errors result in incorrect data reported to the I C master, or incorrect data received from the master by the device. Bus

2

corruption errors can corrupt data in transactions between the I C master and third party I C slaves.

■ Workaround

2

Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I C block from the bus

2

prior to going to sleep modes. I C transactions during sleep are supported by a protocol in which the master wakes the device prior

2

to the I C transaction.

■ Fix Status

To be fixed in future silicon.

Document Number: 001-54459 Rev. *T

Page 45 of 51

CY8C20XX6A/S

■ Changes

None

3. DoubleTimer0 ISR

■ Problem Definition

When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is

used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice.

■ Parameters Affected

No datasheet parameters are affected.

■ Trigger Condition(S)

Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode.

■ Scope of Impact

The ISR may be executed twice.

■ Workaround

In the ISR, firmware should clear the one-shot bit with a statement such as “and reg[B0h], FDh”

■ Fix Status

Will not be fixed

■ Changes

None

4. Missed GPIO Interrupt

■ Problem Definition

When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may

be missed, and the corresponding GPIO ISR not run.

■ Parameters Affected

No datasheet parameters are affected.

■ Trigger Condition(S)

Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt.

■ Scope of Impact

The GPIO interrupt service routine will not be run.

■ Workaround

The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake

the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt.

Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0.

Alternatively, the ISR’s for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system

has attempted to generate a GPIO interrupt.

■ Fix Status

Will not be fixed

■ Changes

None

Document Number: 001-54459 Rev. *T

Page 46 of 51

CY8C20XX6A/S

5. Missed Interrupt During Transition to Sleep

■ Problem Definition

If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be

missed.

■ Parameters Affected

No datasheet parameters are affected.

■ Trigger Condition(S)

Triggered by enabling sleep mode just prior to an interrupt.

■ Scope of Impact

The relevant interrupt service routine will not be run.

■ Workaround

None.

■ Fix Status

Will not be fixed

■ Changes

None

6. Wakeup from sleep with analog interrupt

■ Problem Definition

Device wakes up from sleep when an analog interrupt is trigger

■ Parameters Affected

No datasheet parameters are affected.

■ Trigger Condition(S)

Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 °C or above

■ Scope of Impact

Device unexpectedly wakes up from sleep

■ Workaround

Disable the analog interrupt before entering sleep and turn it back on upon wakeup.

■ Fix Status

Will not be fixed

■ Changes

None

Document Number: 001-54459 Rev. *T

Page 47 of 51

CY8C20XX6A/S

Document History Page

DocumentTitle:CY8C20XX6A/S, 1.8VProgrammableCapSense^®ControllerwithSmartSense™Auto-tuning1–33Buttons,

0–6 Sliders

Document Number: 001-54459

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

2737924

2764528

SNV

07/14/09

New silicon and document

*A

MATT

09/16/2009 Updated AC Chip Level Specifications

Updated ADC User Module Electrical Specifications table

Added Note 5.

Added SR

parameter.

POWER_UP

Updated Ordering information.

Updated Capacitance on Crystal Pins

*B

*C

2803229

2846083

VZD

11/10/09

Added “Contents” on page 3. Added Note 6 on page 20. Edited Features section

to include reference to Incremental ADC.

DST /

KEJO

01/12/2010 Updated “AC Programming Specifications” on page 30 per CDT 56531.

Updated Idd typical values in “DC Chip-Level Specifications” on page 20.

Added 30-pin WLCSP pin and package details.

Added Contents on page 2.

*D

2935141 KEJO/ISW 03/05/2010 Updated “Features” on page 1. Added “SmartSense” on page 4.

®

/ SSHH

Updated “PSoC Functional Overview” on page 4.

Removed SNR statement regarding on page 4 (Analog Multiplexer section).

Updated “” on page 7 with the I2C enhanced slave interface point.

Removed references to “system level” in “Designing with PSoC Designer” on

page 8.

Changed TC CLK and TC DATA to ISSP CLK and ISSP DATA respectively in

all the pinouts.

Modified notes in Pinouts.

Updated 30-ball pin diagram.

Removed IMO frequency trim options diagram in “Electrical Specifications” on

page 19.

Updated and formatted values in DC and AC specifications.

Updated Ordering information table.

Updated 48-pin SSOP package diagram. Added 30-Ball WLCSP package spec

001-50669.

Removed AC Analog Mux Bus Specifications section.

Added SPI Master and Slave mode diagrams.

Modified Definition for Timing for Fast/Standard Mode on the I2C Bus on page

28.

Updated “Thermal Impedances” on page 37.

Combined Development Tools with “Development Tool Selection” on page 38.

Removed references to “system level”.

Updated “Evaluation Tools” on page 38.

Added “Ordering Code Definitions” on page 42.

Updated “Acronyms” on page 43.

Added Glossary and “Reference Documents” on page 43.

Changed datasheet status from Preliminary to Final

*E

*F

3043291

3071632

SAAC

09/30/10

10/26/10

Change: Added the line “Supports SmartSense” in the “Low power CapSense^®

block” bullet in the Features section.

Impact: Helps to know that this part has the feature of Auto Tuning.

Change: Replaced pod MPNs.

Areas affected: Foot kit column of table 37.

Change: Template and Styles update.

Areas affected: Entire datasheet.

Impact: Datasheet adheres to Cypress standards.

JPX

In Table 36 on page 33, modified t

and t

min values to 42. Updated

HIGH

LOW

t

min value to 50; removed max value.

SS_HIGH

Document Number: 001-54459 Rev. *T

Page 48 of 51

CY8C20XX6A/S

Document History Page (continued)

DocumentTitle:CY8C20XX6A/S, 1.8VProgrammableCapSense^®ControllerwithSmartSense™Auto-tuning1–33Buttons,

0–6 Sliders

Document Number: 001-54459

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*G

3247491 TTO/JPM/

ARVM / BVI

06/16/11

Add 4 new parameters to Table 14 on page 21, and 2 new parameters to Table

15 on page 22.

Changed Typ values for the following parameters: I

I

V

DD24, DD12, DD6, OSLPC.

Added footnote # 40 and referred it to pin numbers 1, 14, 15, 42, and 43 under

Table 10 on page 18.

Added footnote # 43 and referred it to parameter V

under Table 11 on page 19.

IOZ

Added “t

” parameter to Table 27 on page 27.

JIT_IMO

Included footnote # 59 and added reference to t

27 on page 27.

specification under Table

JIT_IMO

Updated Solder Reflow Specifications on page 37 as per specs 25-00090 and

25-00103.

I

Max value changed from 0.5 µA to 1.1 µA in Table 13 on page 20.

SB0

Added Table 26 on page 26.

Updated part numbers for “SmartSense_EMC” enabled CapSense controller.

”

*H

*I

3367332

3371807

BTK /

SSHH /

JPM/TTO/

VMAD

09/09/11

Added parameter “t

Added parameter “I

to Table 27 on page 27.

” to Table 13 on page 20.

OS

SBI2C

Added Table 24 on page 26.

Added Table 25 on page 26.

Replaced text “Port 2 or 3 pins” with “Port 2 or 3 or 4 pins” in Table 14, Table 15,

Table 16, and Table 28.

MATT

09/30/2011 Updated Packaging Information (Updated the next revision package outline for

Figure 20, Figure 23 and included a new package outline Figure 25).

Updated Ordering Information (Added new part numbers

CY8C20636A-24LQXI, CY8C20636A-24LQXIT, CY8C20646A-24LQXI,

CY8C20646A-24LQXIT, CY8C20666A-24LQXI, CY8C20666A-24LQXIT,

CY8C20666AS-24LQXI, CY8C20666AS-24LQXIT, CY8C20646AS-24LQXI

and CY8C20646AS-24LQXIT).

Updated in new template.

*J

3401666

3414479

MATT

KPOL

10/11/2011 No technical updates.

*K

10/19/2011 Removed clock stretching feature on page 1.

2

Removed I C enhanced slave interface point from Additional System

Resources.

*L

3452591 BVI / UDYG 12/01/2011 Changed document title.

Updated DC Chip-Level Specifications table.

Updated Solder Reflow Specifications section.

Updated Getting Started and Designing with PSoC Designer sections.

Included Development Tools section.

Updated Software under Development Tool Selection section.

*M

*N

3473330

3587003

ANBA

DST

12/22/2011 Updated DC Chip-Level Specifications under Electrical Specifications (updated

maximum value of I

parameter from 1.1 µA to 1.05 µA).

SB0

04/16/2012 Added note for WLCSP package on page 1.

Added Sensing inputs to pin table captions.

Updated Conditions for DC Reference Buffer Specifications.

Updated t

Added note for t

description in AC Chip-Level Specifications.

JIT_IMO

, t

, and t

specs.

VDDWAIT VDDXRES ACQ

XRESINI

Removed WLCSP package outline.

*O

3638569

BVI

06/06/2012 Updated F

parameter in the Table 36, “SPI Slave AC Specifications,” on

SCLK

page 33.

Changed t

page 32.

to t

in Table 35, “SPI Master AC Specifications,” on

OUT_H

OUT_HIGH

Updated package diagram 001-57280 to *C revision.

Document Number: 001-54459 Rev. *T

Page 49 of 51

CY8C20XX6A/S

Document History Page (continued)

DocumentTitle:CY8C20XX6A/S, 1.8VProgrammableCapSense^®ControllerwithSmartSense™Auto-tuning1–33Buttons,

0–6 Sliders

Document Number: 001-54459

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

10/11/2012 Updated min value of parameter F (from 19 to 15) in the Table 27, “AC

32K1

*P

3774062

UBU

Chip-Level Specifications,” on page 27.

Updated Packaging Information for 001-09116 (*F to *G), 001-13937 (*D to *E),

51-85061 (*E to *F), 001-13191 (*F to *G), and 001-57280 (*C to *D).

*Q

*R

3807186

3836626

PKS

15/11/2012 No content update; appended to EROS document.

SRLI

01/03/2013 Updated Document Title to read as “CY8C20XX6A/S, 1.8 V Programmable

®

CapSense Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6

Sliders”.

Updated Features.

®

Updated PSoC Functional Overview:

Replaced “CY8C20X36A/46A/66A/96A/46AS/66AS” with “CY8C20XX6A/S”.

Updated Getting Started:

Replaced “CY8C20X36A/46A/66A/96A/46AS/66AS” with “CY8C20XX6A/S”.

Updated Pinouts:

Updated 16-pin QFN (10 Sensing Inputs)[3, 4]:

Replaced “12 Sensing Inputs” with “10 Sensing Inputs” in heading, added Note

3 only.

Updated 24-pin QFN (17 Sensing Inputs) [7]:

Replaced “12 Sensing Inputs” with “17 Sensing Inputs” in heading, added Note

7 only.

Updated 24-pin QFN (15 Sensing Inputs (With USB)) [11]:

Replaced “18 Sensing Inputs” with “15 Sensing Inputs” in heading, added Note

11 only.

Updated 30-ball WLCSP (24 Sensing Inputs) [15]:

Replaced “26 Sensing Inputs” with “24 Sensing Inputs” in heading, added Note

15 only.

Updated 32-pin QFN (25 Sensing Inputs) [18]:

Replaced “27 Sensing Inputs” with “25 Sensing Inputs” in heading, added Note

18 only.

updated 32-pin QFN (22 Sensing Inputs (With USB)) [22]:

Replaced “24 Sensing Inputs” with “22 Sensing Inputs” in heading, added Note

22 only.

Updated 48-pin SSOP (31 Sensing Inputs) [26]:

Replaced “33 Sensing Inputs” with “31 Sensing Inputs” in heading, added Note

26 only.

Updated 48-pin QFN (33 Sensing Inputs) [29]:

Replaced “35 Sensing Inputs” with “33 Sensing Inputs” in heading, added Note

29 only.

Updated 48-pin QFN (33 Sensing Inputs (With USB)) [33]:

Replaced “35 Sensing Inputs” with “33 Sensing Inputs” in heading, added Note

33 only.

Updated 48-pin QFN (OCD) (33 Sensing Inputs) [37]:

Added “33 Sensing Inputs” in heading, added Note 37 only.

Updated Packaging Information:

spec 001-42168 – Changed revision from *D to *E.

spec 001-57280 – Changed revision from *D to *E.

*S

*T

3997568

4044148

BVI

05/11/2013 Added Errata.

06/28/2013 Added Errata Footnotes. Updated Template

Updated Packaging Information:

spec 001-09116 – Changed revision from *G to *H.

Document Number: 001-54459 Rev. *T

Page 50 of 51

CY8C20XX6A/S

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

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any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-54459 Rev. *T

Revised June 28, 2013

Page 51 of 51

®

PSoC Designer™ is a trademark and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation.

2

Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided

2

that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.

All products and company names mentioned in this document may be the trademarks of their respective holders.


型号：	CY8C20246AS-24LKXI
厂家：	CYPRESS
描述：	1.8 V Programmable CapSenseÂ® Controller with SmartSenseâ¢ Auto-tuning 1â33 Buttons, 0â6 Sliders 1.8 V可编程CapSenseÂ®控制器SmartSenseâ ?? ¢自动调谐1A ???? 33按钮， 0A ???? 6滑块控制器
文件：	总51页 (文件大小：782K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C20246AS-24LKXI [CYPRESS]

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