CY8C20236A-24LKXA [CYPRESS]
Multifunction Peripheral, CMOS, QFN-16;
| 型号： | CY8C20236A-24LKXA |
| 厂家： | 
CYPRESS |
| 描述： | Multifunction Peripheral, CMOS, QFN-16 时钟 微控制器 |
| 文件： | 总29页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C20236A
Automotive CapSense® Applications
Automotive CapSense® Applications
■ Versatile analog mux
❐ Common internal analog bus
Features
■ Automotive Electronics Council (AEC) Q100 qualified
■ Operating Range: 1.71 V to 5.5 V
■ Low power CapSense® block
❐ Configurable capacitive sensing elements
❐ Supports SmartSense
❐ Simultaneous connection of I/O
❐ High power supply rejection ratio (PSRR) comparator
❐ Low-dropout voltage regulator for all analog resources
■ Additional system resources
❐ I2C Slave:
❐ Supports a combination of CapSense buttons, sliders,
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No clock stretching (under most conditions)
• Implementation during sleep modes with less than 100 µA
• Hardware address validation
❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
❐ 8 to 10-bit incremental analog-to-digital converter (ADC)
touchpads, touchscreens, and proximity sensors
■ Powerful Harvard-architecture processor
❐ M8C CPU speed can be up to 24 MHz or sourced by an
external crystal, resonator, or clock signal
❐ Low power at high speed
❐ Interrupt controller
❐ Temperature range: –40 C to +85 C
■ Flexible on-chip memory
❐ Two program/data storage size options:
• CY8C20x36A: 8 KB flash/1 KB SRAM
❐ 1,000 flash erase/write cycles
❐ Partial flash updates
❐ Two general-purpose high speed, low power analog
comparators
■ Complete development tools
❐ Flexible protection modes
❐ In-system serial programming (ISSP)
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐ Internal low speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
■ Package options
❐ CY8C20x36A:16-pin QFN (3 × 3 × 0.6 mm)
❐ Precision 32 kHz oscillator for optional external crystal
■ Programmable pin configurations
❐ Up to 36 general-purpose I/Os (GPIOs) (depending on
package)
❐ Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
❐ 25-mA sink current on each GPIO
• 120 mA total sink current on all GPIOs
❐ Pull-up, high Z, open-drain modes on all GPIOs
❐ CMOS drive mode – 5 mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
• 20 mA total source current on all GPIOs
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
❐ Hot-swap capability on all Port 1 GPIO
Cypress Semiconductor Corporation
Document Number: 001-63115 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 5, 2017
CY8C20236A
Logic Block Diagram
1.8/2.5/3V
LDO
PWRSYS
(Regulator)
[1]
Port 4 Port 3
Port 2
Port 1
Port 0
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
8K/32K Flash
1K/2K
SRAM
Supervisory ROM (SROM)
Nonvolatile Memory
Interrupt
Controller
Sleep and
Watchdog
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Analog
Reference
CapSense
Module
Two
Analog
Mux
Comparators
SYSTEM BUS
Internal
Voltage
References
POR
and
LVD
SPI
Master/
Slave
Three 16-Bit
Programmable
Timers
I2C
Slave
System
Resets
Digital
Clocks
SYSTEM RESOURCES
Note
1. Internal voltage regulator for internal circuitry.
Document Number: 001-63115 Rev. *D
Page 2 of 29
CY8C20236A
Contents
PSoC® Functional Overview ............................................4
PSoC Core ..................................................................4
CapSense System .......................................................4
Additional System Resources .....................................5
Getting Started ..................................................................5
Application Notes ........................................................5
Development Kits ........................................................5
Training .......................................................................5
CYPros Consultants ....................................................5
Solutions Library ..........................................................5
Technical Support .......................................................5
Designing with PSoC Designer .......................................6
Select Components .....................................................6
Configure Components ...............................................6
Organize and Connect ................................................6
Generate, Verify, and Debug .......................................6
Pinouts ..............................................................................7
16-pin QFN (No E-Pad) ...............................................7
Electrical Specifications ..................................................8
Absolute Maximum Ratings .........................................8
Operating Temperature ...............................................8
DC Chip-Level Specifications ......................................9
DC GPIO Specifications ............................................10
DC Analog Mux Bus Specifications ...........................12
DC Low Power Comparator Specifications ...............12
Comparator User Module Electrical Specifications ...13
ADC Electrical Specifications ....................................13
DC POR and LVD Specifications ..............................14
DC Programming Specifications ...............................14
AC Chip-Level Specifications ....................................15
AC General Purpose I/O Specifications ....................16
AC Comparator Specifications ..................................16
AC External Clock Specifications ..............................16
AC Programming Specifications ................................17
AC I2C Specifications ................................................18
Packaging Information ...................................................21
Thermal Impedances .................................................22
Solder Reflow Specifications .....................................22
Development Tool Selection .........................................23
Software ....................................................................23
Development Kits ......................................................23
Evaluation Tools .............................................................24
Device Programmers .................................................24
Accessories (Emulation and Programming) ..............24
Ordering Information ......................................................25
Ordering Code Definitions .........................................25
Acronyms ........................................................................26
Reference Documents ....................................................26
Document Conventions .................................................26
Units of Measure .......................................................26
Numeric Naming ........................................................27
Glossary ..........................................................................27
Document History Page .................................................28
Sales, Solutions, and Legal Information ......................29
Worldwide Sales and Design Support .......................29
Products ....................................................................29
PSoC® Solutions ......................................................29
Cypress Developer Community .................................29
Technical Support .....................................................29
Document Number: 001-63115 Rev. *D
Page 3 of 29
CY8C20236A
®
Figure 1. CapSense System Block Diagram
PSoC Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
CS1
CS2
IDAC
programmable component.
A
PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
CSN
Vr
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
Reference
Buffer
Cinternal
■ The Core
■ CapSense Analog System
Cexternal (P0[1]
or P0[3])
Comparator
A common, versatile bus allows connection between I/O and the
analog system.
Mux
Mux
Refs
Each CY8C20x36A PSoC device includes
a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 GPIO are also included. The GPIO
provides access to the MCU and analog mux.
Cap Sense Counters
CSCLK
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS,
CapSense
Clock Select
IMO
Oscillator
8-bit Harvard-architecture microprocessor.
Analog Multiplexer System
CapSense System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to
33 inputs[2]. Capacitive sensing is configurable on each GPIO
pin. Scanning of enabled CapSense pins are completed quickly
and easily across multiple ports.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces, such as sliders and
touchpads.
SmartSense™
■ Chip-wide mux that allows analog input from any I/O pin.
■ Crosspoint connection between any I/O pin combinations.
SmartSense is an innovative solution from Cypress that removes
manual tuning of CapSense applications. This solution is easy to
use and provides a robust noise immunity. It is the only auto-
tuning solution that establishes, monitors, and maintains all
required tuning parameters. SmartSense allows engineers to go
from prototyping to mass production without re-tuning for
manufacturing variations in PCB and/or overlay material
properties.
Note
2
2. 36 GPIOs = 33 pins for capacitive sensing+2 pins for I C + 1 pin for modulator capacitor.
Document Number: 001-63115 Rev. *D
Page 4 of 29
CY8C20236A
Additional System Resources
Getting Started
System resources provide additional capability, such as I2C
slave, SPI master, or SPI slave interfaces, three 16-bit
programmable timers, and various system resets supported by
the M8C.
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
These system resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. The merits of each system
resource are listed here:
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the
CY8C20x36A PSoC devices.
■ The I2C slave/SPI master-slave module provides
50/100/400 kHz communication over two wires. SPI
communication over three or four wires runs at speeds of
46.9 kHz to 3 MHz (lower for a slower system clock).
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
■ The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located at
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
■ The I2C enhanced slave interface appears as a 32-byte RAM
buffer to the external I2C master. Using a simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For usage
details, refer to the application note I2C Enhanced Slave
Operation - AN56007.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark. Refer to
Development Kits on page 23.
■ Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced power-
on-reset (POR) circuit eliminates the need for a system
supervisor.
Training
Free PSoC and CapSense technical training (on demand,
webinars, and workshops) is available online at
www.cypress.com/training. The training covers a wide variety of
topics and skill levels to assist you in your designs.
■ An internal reference provides an absolute reference for
capacitive sensing.
■ A register-controlled bypass mode allows the user to disable
the LDO regulator.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, create a technical support case
or call technical support at 1-800-541-4736.
Document Number: 001-63115 Rev. *D
Page 5 of 29
CY8C20236A
Organize and Connect
Designing with PSoC Designer
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called “user modules.” User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. For example,
a PWM User Module configures one or more
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Document Number: 001-63115 Rev. *D
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CY8C20236A
Pinouts
The CY8C20x36A PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not
capable of Digital I/O.
16-pin QFN (No E-Pad)
Table 1. Pin Definitions – CY8C20236A PSoC Device
Type
Pin
Name
Description
No.
Digital Analog
1
2
3
4
5
6
I/O
I
I
I
I
I
I
P2[5] ECO output (XOut)
P2[3] ECO input (XIn)
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI SCLK
Figure 2. CY8C20236A PSoC Device
I/O
I/OHR
I/OHR
I/OHR
I/OHR
P1[1] ISSP CLK[3], I2C SCL, SPI
MOSI
XOut, AI, P2[5]
Xin, AI, P2[3]
1
2
3
4
12 P0[4], AI
11 XRES
7
8
Power
VSS Ground connection
QFN
I2C SCL, SPI SS, AI, P1[7]
I2C SDA, SPI MISO, AI, P1[5]
10 P1[4], AI, EXTCLK
I/OHR
I
P1[0] ISSP DATA[3], I2C SDA, SPI
9
P1[2], AI
CLK[4]
9
I/OHR
I
I
P1[2]
10 I/OHR
P1[4] Optional external clock input
(EXTCLK)
11
Input
XRES Active high external reset with
internal pull-down
12
13
14
I/OH
Power
I
I
P0[4]
VDD Supply voltage
P0[7]
I/OH
15
16
I/OH
I/OH
I
I
P0[3] Integrating input
P0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive, R = Regulated Output.
Notes
3. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
4. Alternate SPI clock.
Document Number: 001-63115 Rev. *D
Page 7 of 29
CY8C20236A
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x36A PSoC devices. For the latest electrical
specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 3. Voltage versus CPU Frequency
5.5V
1.71V
750kHz
3 MHz
24MHz
CPU Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 2. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
Conditions
Min
Typ
Max
Units
Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55
+25
+125
C
VDD
VIO
Supply voltage relative to VSS
DC input voltage
–
–0.5
VSS – 0.5
VSS – 0.5
–25
–
–
–
–
–
–
+6.0
VDD + 0.5
VDD + 0.5
+50
V
V
–
VIOZ
IMIO
ESD
LU
DC voltage applied to tristate
Maximum current into any port pin
Electro static discharge voltage
Latch-up current
–
V
–
mA
V
Human body model ESD
2000
–
In accordance with JESD78 standard
–
200
mA
Operating Temperature
Table 3. Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Conditions
Min
Typ
Max
Units
–
–40
–
+85
C
Operational die temperature
The temperature risefrom ambient tojunction
is package specific. Refer the table Thermal
Impedances per Package on page 22. The
user must limit the power consumption to
comply with this requirement.
–40
–
+100
C
Document Number: 001-63115 Rev. *D
Page 8 of 29
CY8C20236A
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 4. DC Chip-Level Specifications
Symbol
Description
Supply voltage
Conditions
Min
Typ
Max Units
[5, 6, 7]
VDD
Refer the table DC POR and LVD
Specifications on page 14
1.71
–
5.50
V
IDD24
IDD12
IDD6
Supply current, IMO = 24 MHz Conditions are VDD 3.0 V, TA = 25 C,
CPU = 24 MHz. CapSense running at 12 MHz,
no I/O sourcing current
–
–
–
3.32
1.86
1.13
4.00
mA
Supply current, IMO = 12 MHz Conditions are VDD 3.0 V, TA = 25 C,
CPU = 12 MHz. CapSense running at
2.60
1.80
mA
mA
12 MHz, no I/O sourcing current
Supply current, IMO = 6 MHz
Conditions are VDD 3.0 V, TA = 25 C,
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
ISB0
ISB1
Deep sleep current
VDD 3.0 V, TA = 25 C, I/O regulator turned off
–
–
0.10
1.07
0.50
1.50
A
A
Standby current with POR, LVD VDD 3.0 V, TA = 25 C, I/O regulator turned off
and sleep timer
Notes
5. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µsec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
6. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a. Bring the device out of sleep before powering down.
b. Assure that VDD falls below 100 mV before powering back up.
c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
For the referenced registers, refer to the CY8C20x36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows
V
DD brown out conditions to be detected for edge rates slower than 1V/ms.
7. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can
be between 1.8 V and 5.5 V.
Document Number: 001-63115 Rev. *D
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CY8C20236A
DC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C TA 85 °C, 2.4 V to 3.0 V and –40 °C TA 85 °C, or 1.71 V to 2.4 V and –40 °C TA 85 °C, respectively. Typical
parameters apply to 5V and 3.3 V at 25 C and are for design guidance only.
Table 5. 3.0-V to 5.5-V DC GPIO Specifications
Symbol
RPU
Description
Pull-up resistor
Conditions
Min
Typ
5.60
–
Max
8
Units
k
–
4
VOH1
High output voltage
Port 2 or 3 pins
IOH < 10 A, maximum of 10 mA source VDD – 0.20
current in all I/Os
–
V
VOH2
VOH3
High output voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source VDD – 0.90
current in all I/Os
–
–
–
–
V
V
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source VDD – 0.20
current in all I/Os
VOH4
VOH5
VOH6
VOH7
VOH8
VOH9
VOH10
VOL
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH = 5 mA, maximum of 20 mA source VDD – 0.90
current in all I/Os
–
3.00
–
–
3.30
–
V
V
V
V
V
V
V
V
High output voltage
Port 1 Pins with LDO Regulator
Enabled for 3 V out
IOH < 10 A, VDD > 3.1 V, maximum of
2.85
2.20
2.35
1.90
1.60
1.20
–
4 I/Os all sourcing 5 mA
High output voltage
Port 1 pins with LDO regulator enabled 20 mA source current in all I/Os
for 3 V out
IOH = 5 mA, VDD > 3.1V, maximum of
High output voltage
Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os
out
IOH < 10 A, VDD > 2.7 V, maximum of
2.50
–
2.75
–
High output voltage
Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os
out
IOH = 2 mA, VDD > 2.7 V, maximum of
High output voltage
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
IOH < 10 A, VDD > 2.7 V, maximum of
1.80
–
2.10
–
High output voltage
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
IOH = 1 mA, VDD > 2.7 V, maximum of
Low output voltage
IOL = 25 mA, VDD > 3.3 V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
–
0.75
VIL
VIH
VH
Input low voltage
–
–
–
–
–
2.00
–
–
–
0.80
V
V
Input high voltage
–
–
1
7
Input hysteresis voltage
Input leakage (Absolute Value)
Pin capacitance
80
mV
A
pF
IIL
–
0.001
1.70
CPIN
Package and pin dependent
0.50
Temp = 25 C
Document Number: 001-63115 Rev. *D
Page 10 of 29
CY8C20236A
Table 6. 2.4-V to 3.0-V DC GPIO Specifications
Symbol
RPU
Description
Pull-up resistor
Conditions
Min
4
Typ
5.60
–
Max
8
Units
k
–
VOH1
High output voltage
Port 2 or 3 pins
IOH < 10 A, maximum of 10 mA
source current in all I/Os
VDD - 0.20
–
V
VOH2
VOH3
High output voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
source current in all I/Os
VDD - 0.40
–
–
–
–
V
V
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA
source current in all I/Os
VDD - 0.20
VOH4
VOH5A
VOH6A
VOL
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source VDD - 0.50
current in all I/Os
–
1.80
–
–
V
V
V
V
High output voltage
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
IOH < 10 A, VDD > 2.4 V, maximum of
1.50
1.20
–
2.10
–
High output voltage
Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os
out
IOH = 1 mA, VDD > 2.4 V, maximum of
Low output voltage
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
0.75
VIL
VIH
VH
Input low voltage
–
–
–
–
–
1.40
–
–
–
0.72
V
V
Input high voltage
Input hysteresis voltage
Input leakage (absolute value)
Capacitive load on pins
80
1
–
1000
7
mV
nA
pF
IIL
–
CPIN
Package and pin dependent
0.50
1.70
Temp = 25 C
Document Number: 001-63115 Rev. *D
Page 11 of 29
CY8C20236A
Table 7. 1.71-V to 2.4-V DC GPIO Specifications
Symbol
RPU
Description
Pull-up resistor
Conditions
Min
4
Typ
5.60
–
Max
8
Units
k
–
VOH1
High output voltage
Port 2 or 3 pins
IOH = 10 A, maximum of 10 mA
source current in all I/Os
VDD – 0.20
–
V
VOH2
VOH3
High output voltage
Port 2 or 3 pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os
VDD – 0.50
–
–
–
–
V
V
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 100 A, maximum of 10 mA
source current in all I/Os
VDD – 0.20
VOH4
High output voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH=2mA, maximumof10mAsource VDD – 0.50
current in all I/Os
–
–
–
V
V
VOL
Low output voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
0.40
VIL
VIH
VH
Input low voltage
–
–
–
–
–
–
–
0.30 × VDD
V
V
Input high voltage
0.65 × VDD
–
–
Input hysteresis voltage
Input leakage (absolute value)
Capacitive load on pins
–
–
80
1
mV
nA
pF
IIL
1000
7
CPIN
Package and pin dependent
temp = 25 oC
0.50
1.70
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 8. DC Analog Mux Bus Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
RSW
Switch resistance to common analog
bus
–
–
–
–
800
RGND
Resistance of initialization switch to
VSS
–
–
800
The maximum pin voltage for measuring RSW and RGND is 1.8 V
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 9. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
VLPC
Low power comparator (LPC) common Maximum voltage limited to VDD
mode
0.0
–
1.8
V
ILPC
LPC supply current
LPC voltage offset
–
–
–
–
10
40
30
A
VOSLPC
2.5
mV
Document Number: 001-63115 Rev. *D
Page 12 of 29
CY8C20236A
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40°C < TA < 85°C, 1.71V < VDD < 5.5V.
Table 10. Comparator User Module Electrical Specifications
Symbol
TCOMP
Description
Comparator response time 50 mV overdrive
Valid from 0.2 V to VDD – 0.2 V
Conditions
Min
–
Typ
70
Max
100
30
Units
ns
Offset
–
2.5
20
mV
µA
Current
Average DC current, 50 mV
overdrive
–
80
Supply voltage > 2 V
Supply voltage < 2 V
Power supply rejection ratio
–
–
0
80
40
–
–
dB
dB
V
PSRR
Power supply rejection ratio
–
Input range
1.5
ADC Electrical Specifications
Table 11. ADC User Module Electrical Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Input
VIN
Input voltage range
Input capacitance
Input resistance
–
–
0
–
–
–
VREFADC
5
V
pF
CIIN
RIN
Equivalent switched cap input 1/(500fF × 1/(400fF × 1/(300fF ×
resistance for 8-, 9-, or 10-bit data clock) data clock) data clock)
resolution
Reference
VREFADC
ADC reference voltage
Data clock
–
1.14
2.25
–
–
1.26
6
V
Conversion Rate
FCLK
Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications for accuracy
MHz
S8
8-bit sample rate
10-bit sample rate
Data clock set to 6 MHz.
sample rate = 0.001/
(2^Resolution/Data Clock)
–
–
23.43
5.85
–
–
ksps
ksps
S10
Data clock set to 6 MHz.
sample rate = 0.001/
(2^resolution/data clock)
DC Accuracy
RES
Resolution
Can be set to 8-, 9-, or 10-bit
8
–1
–2
0
–
–
10
+2
bits
LSB
DNL
Differential nonlinearity
Integral nonlinearity
Offset error
–
INL
–
–
+2
LSB
EOFFSET
8-bit resolution
10-bit resolution
For any resolution
3.20
12.80
–
19.20
76.80
+5
LSB
0
LSB
EGAIN
Power
IADC
Gain error
–5
%FSR
Operating current
–
–
–
–
2.10
24
2.60
–
mA
dB
dB
PSRR
Power supply rejection ratio PSRR (VDD > 3.0 V)
PSRR (VDD < 3.0 V)
30
–
Document Number: 001-63115 Rev. *D
Page 13 of 29
CY8C20236A
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 12. DC POR and LVD Specifications
Symbol
VPOR0
Description
Conditions
Min
1.61
–
Typ
1.66
2.36
2.60
2.82
2.45
2.71
2.92
3.02
3.13
1.90
1.80
4.73
Max
1.71
2.41
2.66
2.95
2.51
2.78
2.99
3.09
3.20
2.32
1.84
4.83
Units
1.66 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V
V
during startup, reset from the XRES pin, or
reset from watchdog.
VPOR1
VPOR2
VPOR3
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.36 V selected in PSoC Designer
2.60 V selected in PSoC Designer
2.82 V selected in PSoC Designer
2.45 V selected in PSoC Designer –
2.71 V selected in PSoC Designer
2.92 V selected in PSoC Designer
3.02 V selected in PSoC Designer
3.13 V selected in PSoC Designer
1.90 V selected in PSoC Designer
1.80 V selected in PSoC Designer
4.73 V selected in PSoC Designer
–
–
2.40
2.64[8]
2.85[9]
2.95[10]
3.06
1.84
1.75[11]
4.62
V
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Programming Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
VDDIWRITE Supply voltage for flash write
operations
–
–
1.71
–
5.25
V
IDDP
VILP
VIHP
IILP
Supply current during
programming or verify
–
–
5
–
–
–
25
VIL
–
mA
V
Input low voltage during
programming or verify
See the appropriate DC GPIO Specifica-
tions on page 10
Input high voltage during
programming or verify
See appropriate DC GPIO Specifications
on page 10 table on pages 15 or 16
VIH
–
V
Input current when Applying VILP Driving internal pull-down resistor
to P1[0] or P1[1] during
0.2
mA
programming or verify
IIHP
Input current when applying VIHP Driving internal pull-down resistor
to P1[0] or P1[1] during
–
–
1.5
mA
programming or verify
VOLP
VOHP
Output low voltage during
programming or verify
–
–
–
VSS + 0.75
VDD
V
V
Output high voltage during
programming or verify
See appropriate DC GPIO Specifications
VOH
on page 10 table on page 16. For VDD
>
3V use VOH4 in Table 3 on page 8.
FlashENPB Flash write endurance
Erase/write cycles per block
50,000
20
–
–
–
–
–
FlashDR
Flash data retention
Following maximum Flash write cycles;
ambient temperature of 55 °C
Years
Notes
8. Always greater than 50 mV above VPPOR1 voltage for falling supply.
9. Always greater than 50 mV above VPPOR2 voltage for falling supply.
10. Always greater than 50 mV above VPPOR3 voltage for falling supply.
11. Always greater than 50 mV above VPPOR0 voltage for falling supply.
Document Number: 001-63115 Rev. *D
Page 14 of 29
CY8C20236A
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. AC Chip-Level Specifications
Symbol
FIMO24
Description
Conditions
Min
Typ
Max
Units
Internal main oscillator frequency at 24 MHz
Setting
–
–
–
22.8
24
25.2
MHz
FIMO12
FIMO6
Internal main oscillator frequency at 12 MHz
setting
11.4
5.7
12
12.6
6.3
MHz
MHz
Internal main oscillator frequency at 6 MHz
setting
6.0
FCPU
CPU frequency
–
–
–
0.75
19
–
25.20
50
MHz
kHz
kHz
F32K1
F32K_U
Internal low speed oscillator frequency
32
32
Internal low speed oscillator (ILO) untrimmed
frequency)
13
82
DCIMO
DCILO
Duty cycle of IMO
–
–
40
40
–
50
50
–
60
60
250
–
%
%
Internal low speed oscillator duty cycle
SRPOWER_UP Power supply slew rate
VDD slew rate during power-up
After supply voltage is valid
V/ms
ms
s
tXRST
External reset pulse width at power-up
External reset pulse width after power-up[12] Applies after part has booted
1
–
tXRST2
10
–
–
Note
12. The minimum required XRES pulse length is longer when programming the device (see Table 18 on page 17).
Document Number: 001-63115 Rev. *D
Page 15 of 29
CY8C20236A
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 15. AC GPIO Specifications
Symbol
FGPIO
Description
Conditions
Min
Typ
Max
6 MHz for
1.71 V <VDD < 2.40 V
Units
GPIO operating frequency
Normal strong mode Port 0, 1
0
–
MHz
0
–
–
–
–
–
–
–
12 MHz for
2.40 V < VDD< 5.50 V
MHz
ns
tRISE23
tRISE23L
tRISE01
tRISE01L
tFALL
Rise time, strong mode, Cload = 50 pF VDD = 3.0 to 3.6 V, 10% to 90%
Ports 2 or 3
15
15
10
10
10
10
80
80
50
80
50
70
Rise time, strong mode low supply,
Cload = 50 pF, Ports 2 or 3
VDD = 1.71 to 3.0 V, 10% to 90%
ns
Rise time, strong mode, Cload = 50 pF VDD = 3.0 to 3.6 V, 10% to 90%
ns
Ports 0 or 1
LDO enabled or disabled
Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
VDD = 1.71 to 3.0 V, 10% to 90%
LDO enabled or disabled
ns
Fall time, strong mode, Cload = 50 pF VDD = 3.0 to 3.6 V, 10% to 90%
all ports
ns
tFALLL
Fall time, strong mode low supply,
Cload = 50 pF, all ports
VDD = 1.71 to 3.0 V, 10% to 90%
ns
Figure 4. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TRise23L
TRise01L
TFall
TFallL
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 16. AC Low Power Comparator Specifications
Symbol
tLPC
Description
Conditions
Min
Typ
Max
Units
Comparator response time,
50 mV overdrive
50 mV overdrive does not include
offset voltage.
–
–
100
ns
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 17. AC External Clock Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
FOSCEXT
Frequency (external oscillator
frequency)
–
0.75
–
25.20
MHz
High period
–
–
–
20.60
20.60
150
–
–
–
5300
ns
ns
s
Low period
–
–
Power-up IMO to switch
Document Number: 001-63115 Rev. *D
Page 16 of 29
CY8C20236A
AC Programming Specifications
Figure 5. AC Waveform
SCLK (P1[1])
TRSCLK
TFSCLK
SDATA (P1[0])
TSSCLK
THSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
Description
Rise time of SCLK
Conditions
Min
1
Typ
–
Max
20
20
–
Units
ns
–
–
–
–
–
–
–
Fall time of SCLK
1
–
ns
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
tERASEB
tWRITE
tDSCLK
tDSCLK3
tDSCLK2
tXRST3
Flash erase time (block)
–
–
18
25
60
85
130
–
Flash block write time
–
–
Data out delay from falling edge of SCLK 3.6 VDD
–
–
Data out delay from falling edge of SCLK 3.0 VDD 3.6
Data out delay from falling edge of SCLK 1.71 VDD 3.0
–
–
ns
–
–
ns
External reset pulse width after power-up Required to enter programming mode
when coming out of sleep
300
–
s
tXRES
XRES pulse length
–
–
–
–
–
300
0.1
–
–
–
–
–
–
1
s
ms
ms
ms
ms
tVDDWAIT VDD stable to wait-and-poll hold off
tVDDXRES VDD stable to XRES assertion delay
14.27
0.01
3.20
–
tPOLL
tACQ
SDATA high pulse time
200
19.60
“Key window” time after a VDD ramp
acquire event, based on 256 ILO clocks.
tXRESINI
“Key window” time after an XRES event,
based on 8 ILO clocks
–
98
–
615
s
Document Number: 001-63115 Rev. *D
Page 17 of 29
CY8C20236A
2
AC I C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. AC Characteristics of the I2C SDA and SCL Pins
Standard
Fast Mode
Mode
Symbol
fSCL
Description
Units
Min
0
Max
100
–
Min
0
Max
SCL clock frequency
400 kHz
tHD;STA
Hold time (repeated) START condition. After this period, the first clock pulse is
generated
4.0
0.6
–
µs
tLOW
LOW period of the SCL clock
4.7
4.0
4.7
0
–
–
1.3
0.6
0.6
0
100[13]
0.6
1.3
0
–
–
µs
µs
µs
µs
ns
µs
µs
ns
tHIGH
HIGH Period of the SCL clock
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Setup time for a repeated START condition
Data hold time
–
–
3.45
–
0.90
–
Data setup time
250
4.0
4.7
–
Setup time for STOP condition
–
–
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
–
–
tSP
–
50
Figure 6. Definition for Timing for Fast/Standard Mode on the I2C Bus
Note
13. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-63115 Rev. *D
Page 18 of 29
CY8C20236A
Table 20. SPI Master AC Specifications
Symbol Description
FSCLK SCLK clock frequency
Conditions
Min
Typ
Max
Units
VDD 2.4 V
–
–
–
–
6
3
MHz
MHz
VDD < 2.4 V
–
DC
SCLK duty cycle
–
50
–
%
tSETUP
MISO to SCLK setup time
VDD 2.4 V
60
100
–
–
–
–
ns
ns
V
–
–
–
DD < 2.4 V
tHOLD
SCLK to MISO hold time
SCLK to MOSI valid time
MOSI high time
40
–
–
–
–
–
40
–
ns
ns
ns
tOUT_VAL
tOUT_HIGH
40
Figure 7. SPI Master Mode 0 and 2
SPI Master, modes 0 and 2
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TSETUP
THOLD
MISO
(input)
LSB
MSB
TOUT_SU
TOUT_H
MOSI
(output)
Figure 8. SPI Master Mode 1 and 3
SPI Master, modes 1 and 3
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TSETUP
THOLD
MISO
(input)
MSB
LSB
TOUT_SU
TOUT_H
MOSI
(output)
LSB
MSB
Document Number: 001-63115 Rev. *D
Page 19 of 29
CY8C20236A
Table 21. SPI Slave AC Specifications
Symbol Description
FSCLK
Conditions
Min
Typ
Max
Units
SCLK clock frequency
VDD 2.4 V
VDD < 2.4 V
–
–
–
–
12
6
MHz
MHz
tLOW
SCLK low time
–
–
–
–
–
–
–
–
–
42
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHIGH
SCLK high time
42
tSETUP
tHOLD
MOSI to SCLK setup time
SCLK to MOSI hold time
SS high to MISO valid
SCLK to MISO valid
SS high time
30
–
50
–
–
tSS_MISO
tSCLK_MISO
tSS_HIGH
tSS_CLK
tCLK_SS
153
125
–
–
50
Time from SS low to first SCLK
Time from last SCLK to SS high
2/SCLK
2/SCLK
–
–
Figure 9. SPI Slave Mode 0 and 2
SPI Slave, modes 0 and 2
TSS_HIGH
TCLK_SS
TSS_CLK
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TOUT_H
TSS_MISO
MISO
(output)
TSETUP
THOLD
MOSI
(input)
LSB
MSB
Figure 10. SPI Slave Mode 1 and 3
SPI Slave, modes 1 and 3
TSS_CLK
TCLK_SS
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TOUT_H
TSCLK_MISO
TSS_MISO
MISO
(output)
MSB
LSB
TSETUP
THOLD
MOSI
(input)
MSB
LSB
Document Number: 001-63115 Rev. *D
Page 20 of 29
CY8C20236A
Packaging Information
This section illustrates the packaging specifications for the CY8C20x36A PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Figure 11. 16-pin QFN (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116
001-09116 *J
Important Note For information on the preferred dimensions for mounting QFN packages, refer to Application Note, Application Notes
for Surface Mount Assembly of Amkor’s MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
Document Number: 001-63115 Rev. *D
Page 21 of 29
CY8C20236A
Thermal Impedances
Table 22. Thermal Impedances per Package
[14]
Package
Typical JA
33 C/W
16-pin QFN
Solder Reflow Specifications
Table 23 shows the solder reflow temperature limits that must not be exceeded.
Table 23. Solder Reflow Specifications
Package
Maximum Time above TC – 5 C
30 seconds
Maximum Peak Temperature (TC)
16-pin QFN
260 C
Note
14. TJ = TA + Power ×
.
JA
Document Number: 001-63115 Rev. *D
Page 22 of 29
CY8C20236A
capability to program single devices. The emulator consists of a
base unit that connects to the PC by way of a USB port. The base
unit is universal and operates with all PSoC devices. Emulation
pods for each device family are available separately. The
emulation pod takes the place of the PSoC device in the target
board and performs full speed (24MHz) operation.
Development Tool Selection
Software
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer. Utilized by thousands of PSoC developers, this
robust software has been facilitating PSoC designs for years.
PSoC Designer is available free of charge at
http://www.cypress.com. PSoC Designer comes with a free C
compiler.
Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36A family of parts. However, the additional trace
length and a minimal ground plane in the Flex-Pod can create
noise problems that make it difficult to debug the design. A
custom bonded On-Chip Debug (OCD) device is available in a
48-pin QFN package. The OCD device is recommended for
debugging designs that have high current and/or high analog
accuracy requirements. The QFN package is compact and is
connected to the ICE through a high density connector.
PSoC Designer Software Subsystems
You choose a base device to work with and then select different
onboard analog and digital components called user modules that
use the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters. You configure the user modules
for your chosen application and connect them to each other and
to the proper pins. Then you generate your project. This
prepopulates your project with APIs and libraries that you can
use to program your application.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube in-circuit emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration allows for changing configurations at run time.
Code Generation Tools PSoC Designer supports multiple third-
party C compilers and assemblers. The code generation tools
work seamlessly within the PSoC Designer interface and have
been tested with a full range of debugging tools. The choice is
yours.
Development Kits
All development kits are sold at the Cypress Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all the features of C tailored to
the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■ PSoC Designer Software CD
■ ICE-Cube In-Circuit Emulator
■ ICE Flex-Pod for CY8C29x66A Family
■ Cat-5 Adapter
■ Mini-Eval Programming Board
■ 110 ~ 240 V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466A-24PXI 28-PDIP Chip Samples
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
Document Number: 001-63115 Rev. *D
Page 23 of 29
CY8C20236A
CY3280-20x66 Universal CapSense Controller
Evaluation Tools
The CY3280-20X66 CapSense Controller Kit is designed for
easy prototyping and debug of CY8C20xx6A CapSense Family
designs with pre-defined control circuitry and plug-in hardware.
Programming hardware and an I2C-to-USB bridge are included
for tuning and data acquisition.
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
The kit includes:
■ CY3280-20x66 CapSense Controller Board
■ CY3240-I2USB Bridge
■ MiniProg Programming Unit
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443A-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
■ CY3210 MiniProg1 Programmer
■ USB 2.0 Retractable Cable
■ CY3280-20x66 Kit CD
Device Programmers
■ Getting Started Guide
All device programmers are purchased from the Cypress Online
Store.
■ USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
CY3210-PSoCEval1
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 110 ~ 240 V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
Accessories (Emulation and Programming)
Table 24. Emulation and Programming Accessories
Flex-Pod Kit[15]
Foot Kit[16]
Adapter[17]
Part Number
Pin Package
16-pin QFN
CY8C20236A-24LKXA
CY3250-20246QFN
CY3250-16QFN-FK
–
Notes
15. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
16. Foot kit includes surface mount feet that can be soldered to the target PCB.
17. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-63115 Rev. *D
Page 24 of 29
CY8C20236A
Ordering Information
The following table lists the CY8C20x36A PSoC devices' key package features and ordering codes..
Table 25. PSoC Device Key Features and Ordering Information
Flash
(Bytes) (Bytes)
SRAM
CapSense Digital I/O
XRES
ADC
Analog
Inputs
Package
Ordering Code
18
[
]
Blocks
Pins
Pin
Yes
Yes
16-Pin (3 × 3 × 0.6 mm) QFN CY8C20236A-24LKXA
8K
8K
1K
1K
1
1
13
13
Yes
Yes
16-Pin (3 × 3 × 0.6 mm) QFN CY8C20236A-24LKXAT
(Tape and Reel)
13
13
Ordering Code Definitions
A = Automotive
Note
18. Dual-function Digital I/O Pins also connect to the common analog mux.
Document Number: 001-63115 Rev. *D
Page 25 of 29
CY8C20236A
Acronyms
Reference Documents
The following table lists the acronyms that are used in this
document.
■ Technical reference manual for CY8C20xx6 devices
Table 26. Acronyms Used in this Document
■ In-system Serial Programming (ISSP) protocol for 20xx6
(AN2026C)
Acronym
AC
ADC
API
CMOS
CPU
DAC
DC
Description
alternating current
■ Host Sourced Serial Programming for 20xx6 devices
(AN59389)
analog-to-digital converter
application programming interface
complementary metal oxide semiconductor
central processing unit
digital-to-analog converter
direct current
Document Conventions
Units of Measure
Table 27 lists all the abbreviations used to measure the PSoC
devices.
EOP
FSR
GPIO
GUI
end of packet
full scale range
Table 27. Units of Measure
general purpose input/output
graphical user interface
inter-integrated circuit
in-circuit emulator
digital analog converter current
internal low speed oscillator
internal main oscillator
input/output
in-system serial programming
liquid crystal display
low dropout (regulator)
least-significant bit
Symbol
C
dB
fF
Unit of Measure
degree Celsius
decibels
femto farad
gram
2
I C
ICE
IDAC
ILO
IMO
I/O
ISSP
LCD
LDO
LSB
LVD
g
Hz
KB
Kbit
KHz
Ksps
k
MHz
M
A
F
H
s
W
mA
ms
mV
nA
ns
hertz
1024 bytes
1024 bits
kilohertz
kilo samples per second
kilohm
megahertz
megaohm
low voltage detect
MCU
MIPS
MISO
MOSI
MSB
OCD
POR
PPOR
PSRR
PWRSYS
micro-controller unit
mega instructions per second
master in slave out
microampere
microfarad
microhenry
microsecond
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
master out slave in
most-significant bit
on-chip debugger
power on reset
precision power on reset
power supply rejection ratio
power system
Programmable System-on-Chip
slow internal main oscillator
static random access memory
signal to noise ratio
®
PSoC
SLIMO
SRAM
SNR
QFN
SCL
SDA
SDATA
SPI
nV
W
ohm
pA
pF
picoampere
picofarad
quad flat no-lead
serial I2C clock
serial I2C data
serial ISSP data
pp
ppm
ps
sps
s
V
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
serial peripheral interface
slave select
shrink small outline package
test controller
SS
SSOP
TC
W
watt
USB
universal serial bus
WLCSP
XTAL
wafer level chip scale package
crystal
Document Number: 001-63115 Rev. *D
Page 26 of 29
CY8C20236A
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Glossary
Crosspoint connection
Differential non-linearity
Connection between any GPIO combination via analog multiplexer bus.
Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the worst case deviation from the
ideal 1 LSB step.
Hold time
Hold time is the time following a clock event during which the data input to a latch or flip-
flop must remain stable in order to guarantee that the latched data is correct.
I2C
It is a serial multi-master bus used to connect low speed peripherals to MCU.
Integral nonlinearity
It is a term describing the maximum deviation between the ideal output of a DAC/ADC and
the actual output level.
Latch-up current
Current at which the latch-up test is conducted according to JESD78 standard (at
125 degree celsius)
Power supply rejection ratio (PSRR)
The PSRR is defined as the ratio of the change in supply voltage to the corresponding
change in output voltage of the device.
Scan
The conversion of all sensor capacitances to digital values.
Setup time
Period required to prepare a device, machine, process, or system for it to be ready to
function.
Signal-to-noise ratio
SPI
The ratio between a capacitive finger signal and system noise.
Serial peripheral interface is a synchronous serial data link standard.
Document Number: 001-63115 Rev. *D
Page 27 of 29
CY8C20236A
Document History Page
Document Title: CY8C20236A, Automotive CapSense® Applications
Document Number: 001-63115
Origin of Submission
Revision
ECN
Description of Change
Change
Date
**
2989484
3262255
BTK
07/21/10
05/19/11
New data sheet.
*A
BTK
Changed status from Advance to Preliminary.
Added preliminary information to data sheet.
*B
*C
3311559
4478256
BTK
KUK
07/13/11
Changed status from Preliminary to Final.
Removed “Capacitance on Crystal Pins” section.
08/19/2014 Updated Document Title as “CY8C20236A, Automotive CapSense®
Applications”.
Removed CY8C20566A related information in all instances across the
document.
Removed 48-pin SSOP package related information in all instances across the
document.
Updated PSoC® Functional Overview:
Updated description.
Updated Electrical Specifications:
Updated DC Chip-Level Specifications:
Updated Table 4:
Removed the Note “For USB mode, the VDD supply for bus-powered
application should be limited to 4.35 V–5.35 V. For self-powered application,
VDD should be 3.15 V–3.45 V.” and its reference in VDD parameter.
Updated Packaging Information:
spec 001-09116 – Changed revision from *E to *J.
Removed spec 51-85061 *D
Updated Ordering Information:
Updated part numbers.
Removed the column “USB”.
Updated to new template.
Completing Sunset Review.
*D
5873117
SNPR
09/05/2017 Updated to new template.
Completing Sunset Review.
Document Number: 001-63115 Rev. *D
Page 28 of 29
CY8C20236A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2010–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-63115 Rev. *D
Revised September 5, 2017
Page 29 of 29
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
2
2
2
Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided
2
that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
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