CY8C20110-LDX2I [CYPRESS]
CapSenseLITE - 10 Configurable IOs; CapSenseLITE - 10个可配置的IO
| 型号： | CY8C20110-LDX2I |
| 厂家： | 
CYPRESS |
| 描述： | CapSenseLITE - 10 Configurable IOs |
| 文件： | 总12页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C20110
CapSenseLITE - 10 Configurable IOs
Features
Overview
■ Ten configurable IOs supporting
❐ CapSense buttons
❐ LED drive
❐ Interrupt outputs
❐ WAKE on interrupt input
❐ User defined input/output
The CapSenseLITE controller allows the control of ten IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
The user has the ability to configure buttons, outputs, and
parameters, through specific commands sent to the I2C port. The
IOs have the flexibility in mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSenseLITE products are
designed for easy integration into complex products.
■ 2.4V to 5.25V operating voltage
■ Industrial temperature range: –40°C to +85°C
■ I2C slave interface for configuration
■ Reduce BOM cost
❐ Internal oscillator - no external oscillators or crystal
❐ Free development tool - no external tuning components
Architecture
■ Low operating current
❐ Active current: continuous sensor scan - 1mA
❐ Sleep current: no scan, continuous sleep - 2.6uA
The logic block diagram illustrates the internal architecture of
CY8C20110.
The user is able to configure registers with parameters needed
to adjust the operation and sensitivity of the CapSense system.
CY8C20110 supports a standard I²C serial communication
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
■ Available in 16-pin QFN and 16-pin SOIC packages
The CapSenseLITE Core
The CapSenseLITE Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, along with sleep and watchdog timers.
System resources provide additional capability, such as a config-
urable I2C slave communication interface and various system
resets. The Analog system contains the CapSense PSoC block
and an internal 1.8V analog reference, which together support
capacitive sensing of up to 10 inputs.
Cypress Semiconductor Corporation
Document Number: 001-17345 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•408-943-2600
Revised November 22, 2007
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CY8C20110
Logic Block Diagram
External
Vcc
2.4 - 5.25
10 Configurable IOs
2KB Flash
CapSenseLITE
Core
512B
SRAM
Document Number: 001-17345 Rev. *B
Page 2 of 12
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CY8C20110
Pinouts
Figure 1. Pin Diagram - 16 QFN
CSInt GP0[3]
GP0[4]
VDD
GP0[0]
GP0[1]
GP0[2]
XRES
I2C SCL
I2C SDA
GP1[4]
GP1[3]
GP1[0]
GP1[2]
GP1[1]
VSS
Table 1. Pin Definitions - 16 QFN
Pin Number
Name
GP0[0]
GP0[1]
I2C SCL
I2C SDA
GP1[0]
GP1[1]
VSS
Description
1
2
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
I2C clock
3
4
I2C data
5
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Ground connection
6
7
8
GP1[2]
GP1[3]
GP1[4]
XRES
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as Capsense or GPIO
Active HIGH external reset with internal pull down
Configurable as CapSense or GPIO
Supply voltage
9
10
11
12
13
14
15
16
GP0[2]
VDD
GP0[3]
CSInt
Configurable as CapSense or GPIO
Integrating Capacitor Input
GP0[4]
Configurable as CapSense or GPIO
Document Number: 001-17345 Rev. *B
Page 3 of 12
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CY8C20110
Figure 2. Pin Diagram - 16 SOIC
GP0[3]
CSInt
1
VDD
16
2
GP0[2]
15
GP0[4]
GP0[0]
GP0[1]
I2CSCL
I2CSDA
3
XRES
GP1[4]
GP1[3]
GP1[2]
14
4
5
13
12
SOIC
(Top View)
6
7
8
11
10
9
V
SS
GP1[0]
GP1[1]
Table 2. Pin Definitions - 16 SOIC
Pin Number
Name
GP0[3]
CSInt
Description
1
2
Configurable as CapSense or GPIO
Integrating Capacitor Input
3
GP0[4]
GP0[0]
GP0[1]
I2C SCL
I2C SDA
GP1[0]
GP1[1]
VSS
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
I2C clock
4
5
6
7
I2C data
8
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Ground connection
9
10
11
12
13
14
15
16
GP1[2]
GP1[3]
GP1[4]
XRES
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Active HIGH external reset with internal pull down.
Configurable as CapSense or GPIO
Supply voltage
GP0[2]
VDD
Document Number: 001-17345 Rev. *B
Page 4 of 12
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CY8C20110
2
The CapSense Analog System
I C Interface
The CapSense analog system contains the capacitive sensing
hardware. The CapSense Successive Approximation (CSA)
algorithm is supported. This hardware performs capacitive
sensing and scanning without external components. Capacitive
sensing is configurable on each pin.
The two modes of operation for the I2C interface are:
■ Device register configuration and status read or write for
controller
■ Command execution
The I2C address is programmable during configuration. It can be
locked to prevent accidental change by setting a flag in a config-
uration register.
Additional System Resources
System Resources provide additional capability useful to
complete systems. Additional resources are low voltage
detection and Power On Reset (POR).
CapSenseLITE Software Tool
■ The I2C slave provides 50, 100, or 400 kHz communication
over two wires.
An easy to use software tool integrated with PSoC Express is
available for configuring and tuning CapSenseLITE devices.
Refer to the Application Note AN42137 for details of the software
tool.
■ Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels and the advanced POR circuit elimi-
nates the need for a system supervisor.
An internal 1.8V reference provides an absolute reference for
capacitive sensing.
Electrical Specifications
Absolute Maximum Ratings
Parameter
Description
Storage temperature
Min
Typ
Max
Unit
Notes
TSTG
–55
25
+100
°C Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25°C ± 25°C.
Extended duration storage tempera-
tures above 65°C degrades reliability.
TA
Ambient temperature with power
applied
–40
–
+85
°C
VDD
VIO
Supply voltage on VDD relative to VSS
DC input voltage
–0.5
VSS – 0.5
VSS – 0.5
–25
–
–
–
–
–
–
+6.0
VDD + 0.5
VDD + 0.5
+50
V
V
VIOZ
IMIO
ESD
LU
DC voltage applied to tri-state
Maximum current into any GPIO pin
Electrostatic discharge voltage
Latch up current
V
mA
2000
-
V
Human body model ESD
-
200
mA
Operating Temperature
Parameter
Description
Min
–40
–40
Typ
–
Max
+85
Unit
ºC
Notes
TA
TJ
Ambient temperature
Junction temperature
–
+100
ºC
Document Number: 001-17345 Rev. *B
Page 5 of 12
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CY8C20110
DC Electrical Characteristics
DC Chip Level Specifications
Parameter
VDD
Description
Supply voltage
Min
2.40
–
Typ
–
Max
5.25
2.5
4
Unit
Notes
V
IDD
Supply current
1.5
2.6
mA Conditions are Vdd = 3.0V, TA = 25°C
ISB27
Sleep mode current with POR and
LVD active. Mid temperature range
–
µA
VDD = 2.55V, 0°C < TA < 40°C
ISB
Sleep mode current with POR and
LVD active.
–
2.8
5
µA
VDD = 3.3V, –40°C < TA < 85°C
5V and 3.3V DC General Purpose IO Specifications
Parameter
RPU
Description
Pull up resistor
Min
4
Typ
5.6
–
Max
8
Unit
kΩ
V
Notes
VOH1
High output voltage
Port 0 pins
VDD – 0.2
–
IOH < 10 µA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
VOH2
VOH3
VOH4
VOH5
High output voltage
Port 0 pins
VDD – 0.9
VDD – 0.2
VDD – 0.9
2.75
–
–
–
–
V
V
V
V
IOH = 1 mA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
High output voltage
Port 1 pins
IOH < 10 µA, Vdd> 3.0V, maximum of
10 mA source current in all IOs.
High output voltage
Port 1 pins
–
–
IOH = 5 mA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
High output voltage
Port 1 pins with 3.0V LDO regulator
enabled
3.0
3.2
IOH < 10 µA, Vdd> 3.1V, maximum of
4 IOs all sourcing 5mA.
VOH6
VOH7
VOH8
VOL
High Output Voltage
Port 1 pins with 3.0V LDO regulator
enabled
2.2
2.1
2
–
2.4
–
–
2.5
–
V
V
V
IOH = 5 mA, Vdd > 3.1V, maximum of
20 mA source current in all IOs.
High Output Voltage
Port 1 pins with 2.4V LDO regulator
enabled
IOH < 10 µA, Vdd > 3.0V, maximum of
20 mA source current in all IOs.
High Output Voltage
Port 1 pins with 2.4V LDO regulator
enabled
IOH < 200 µA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
Low output voltage
–
–
0.75
V
IOL = 20 mA, Vdd > 3V, maximum of 60
mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA
sink current on odd port pins (for
example, P0[3] and P1[3]).
VIL
VIH
VH
IIL
Input low voltage
–
2.0
–
–
–
0.8
–
V
V
Vdd = 3.6 to 5.25V.
Vdd = 3.6 to 5.25V.
Input high voltage
Input hysteresis voltage
Input leakage
140
1
–
mV
nA
pF
–
–
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
5
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
Document Number: 001-17345 Rev. *B
Page 6 of 12
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CY8C20110
2.7V DC General Purpose IO Specifications
Parameter
RPU
Description
Pull up resistor
Min
4
Typ
5.6
–
Max
8
Unit
kΩ
V
Notes
VOH1
High output voltage
Port 0 Pins
VDD – 0.2
–
IOH<10µA, maximumof10mA source
current in all IOs.
VOH2
VOH3
VOH4
VOL
High output voltage
Port 0 Pins
VDD – 0.5
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
–
V
V
V
V
IOH = 0.2 mA, maximum of 10 mA
source current in all IOs.
High output voltage
Port 1 Pins
IOH < 10 µA, maximum of 10 mA
source current in all IOs.
High output voltage
Port 1 Pins
–
IOH = 2 mA, maximum of 10 mA source
current in all IOs.
Low output voltage
0.75
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2]andP1[4])and30mAsinkcurrent
on odd port pins (for example, P0[3]
and P1[3]).
VOLP1
Low Output Voltage Port 1 Pins
–
–
0.4
V
IOL=5mA Maximum of 50mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 50mA sink current
on odd port pins (for example, P0[1]
and P1[3]). 2.4<=Vdd<=3.6V
VIL
Input low voltage
–
1.4
1.6
–
–
–
0.75
V
V
Vdd = 2.4 to 3.6V.
Vdd = 2.4 to 2.7V.
Vdd = 2.7 to 3.6V
VIH1
VIH2
VH
Input high voltage
–
–
–
–
5
Input high voltage
–
V
Input hysteresis voltage
Input leakage
60
1
mV
nA
pF
IIL
–
Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
DC POR and LVD Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VDD Value PPOR Trip
VDD= 2.7V
Vdd must be greater than or equal to
2.5V during startup, reset from the
XRES pin, or reset from Watchdog.
VPPOR0
VPPOR1
–
–
2.36
2.60
2.40
2.65
V
V
VDD= 3.3V,5V
V
DD Value for LVD trip
VLVD0
VLVD2
VLVD6
VDD= 2.7V
2.39
2.75
3.98
2.45
2.92
4.05
2.51
2.99
4.12
V
V
V
V
V
DD= 3.3V
DD= 5V
Document Number: 001-17345 Rev. *B
Page 7 of 12
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CY8C20110
AC Electrical Characteristics
5.0V and 3.3V AC General Purpose IO Specifications
Parameter
Description
Rise time, strong mode,
Cload = 50pF, Port 0
Min
Max
Unit
Notes
TRise0
15
80
ns
Vdd = 3.0V to 3.6V and 4.75V to 5.25V,
10% - 90%
TRise1
TFall
Rise time, strong mode,
Cload = 50pF, Port 1
10
10
50
50
ns
ns
Vdd = 3.0V to 3.6V, 10% - 90%
Fall time, strong mode,
Cload = 50pF, all ports
Vdd = 3.0V to 3.6V and 4.75V to 5.25V,
10% - 90%
AC I2C Specifications
Standard Mode
Fast Mode
Parameter
Description
SCL clock frequency
Unit
Notes
Min
Max
Min
Max
FSCLI2C
0
100
0
400
KHz Fast mode not supported for
VDD < 3.0V
THDSTAI2C Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
µs
TLOWI2C
THIGHI2C
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
µs
µs
µs
TSUSTAI2C Setup time for a repeated START
condition
THDDATI2C Data hold time
0
–
–
–
–
0
–
–
–
–
µs
ns
µs
µs
TSUDATI2C Data setup time
250
4.0
4.7
100
0.6
1.3
TSUSTOI2C Setup time for STOP condition
TBUFI2C
BUS free time between a STOP
and START condition
TSPI2C
Pulse width of spikes suppressed
by the input filter
–
–
0
50
ns
2.7V AC General Purpose IO Specifications
Parameter
Description
Rise time, strong mode,
Cload = 50pF, Port 0
Min
Max
Unit
Notes
TRise0
15
10
10
100
ns
Vdd = 2.4V to 3.0V, 10% - 90%
TRise1
TFall
Rise time, strong mode,
Cload = 50pF, Port 1
70
ns
ns
Vdd = 2.4V to 3.0V, 10% - 90%
Vdd = 2.4V to 3.0V, 10% - 90%
Fall time, strong mode,
Cload = 50pF, all ports
70
Document Number: 001-17345 Rev. *B
Page 8 of 12
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CY8C20110
Figure 3. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
T
SPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
T
BUFI2C
T
T
SUSTOI2C
T
SUSTAI2C
T
T
HIGHI2C
S
HDDATI2C
Sr
P
S
HDSTAI2C
Document Number: 001-17345 Rev. *B
Page 9 of 12
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CY8C20110
Ordering Information
Operating
Temperature
Ordering Code
Package Diagram
Package Type
CY8C20110-LDX2I
CY8C20110-SX2I
001-09116
51-85068
16 QFN
16 SOIC
Industrial
Industrial
Thermal Impedances by Package
[1]
Package
Typical θJA
46 °C/W
79.96 °C/W
16 QFN
16 SOIC
Note
1.
T = T + Power x θ
J A JA
Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[2]
Maximum Peak Temperature
16 QFN
240 °C
240 °C
260 °C
260 °C
16 SOIC
Note
2. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Package Diagram
Figure 4. 16 - Pin Chip On Pb-free 3x3 mm (Sawn) QFN
DIMENSIONS IN mm MIN.
MAX.
2.9
3.1
0.20 min
0.45
0.55
1.5 (NOM)
PIN #1 ID
1
2
2
1
2.9
3.1
0.152 REF.
0.05 MAX
0.20 DIA TYP.
0.30
0.18
0.60 MAX
0.50
SEATING PLANE
1.5
SIDE VIEW
BOTTOM VIEW
TOP VIEW
JEDEC # MO-220
DESCRIPTION
PART NO.
Package Weight: 0.014g
LEAD-FREE
STANDARD
LG16A
LD16A
001-09116-*C
Document Number: 001-17345 Rev. *B
Page 10 of 12
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CY8C20110
Figure 5. 16 - Pin (150-Mil) SOIC
51-85068-*B
Document Number: 001-17345 Rev. *B
Page 11 of 12
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CY8C20110
Document History Page
Document Title: CY8C20110 CapSenseLITE - 10 Configurable IOs
Document Number: 001-17345
Orig. of
Change
REV.
ECN.
Issue Date
Description of Change
**
1341766 See ECN
1494145 See ECN
TUP/SFV New Data Sheet
*A
TUP/AESA Changed to FINAL Datasheet
Removed table - 2.7V DC General Purpose IO Specifications - Open Drain with
a pull up to 1.8V
Updated Logic Block Diagram
*B
1773608 See ECN
TUP/AESA Removed table - 3V DC General Purpose IO Specifications
Updated Logic Block Diagram
Updated table - DC POR and LVD Specifications
Updated table - DC Chip Level Specifications
Updated table - 5V and 3.3V DC General Purpose IO Specifications
Updated table - 2.7V DC General Purpose IO Specifications
Updated table - AC GPIO Specifications and split it into two tables for 5V/3.3V
and 2.7V
Added section on CapSenseLITE Software tool
Updated 16-QFN Package Diagram
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-17345 Rev. *B
Revised November 22, 2007
Page 12 of 12
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
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Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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