CY8C20110_12 [CYPRESS]
CapSense® Express⢠Button Capacitive Controllers; CapSense® Expressâ ?? ¢键电容式控制器
| 型号： | CY8C20110_12 |
| 厂家： | 
CYPRESS |
| 描述： | CapSense® Express⢠Button Capacitive Controllers |
| 文件： | 总43页 (文件大小：1510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
CapSense® Express™ Button
Capacitive Controllers
CapSense® Express™ Button Capacitive Controllers
■ Wide range of operating voltages
❐ 2.4 V to 2.9 V
❐ 3.10 V to 3.6 V
❐ 4.75 V to 5.25 V
■ I2C communication
Features
■ 10/8/6/4 capacitive button input
❐ Robust sensing algorithm
❐ High sensitivity, low noise
❐ Immunity to RF and AC noise
❐ Low radiated EMC noise
❐ Supported from 1.8 V
❐ Internal pull-up resistor support option
❐ Data rate up to 400 kbps
❐ Configurable I2C addressing
❐ Supports wide range of input capacitance, sensor shapes,
and sizes
■ Target applications
❐ Printers
■ Industrial temperature range: –40 °C to +85 °C.
❐ Cellular handsets
❐ LCD monitors
❐ Portable DVD players
■ Available in 16-pin QFN, 8-pin, and 16-pin SOIC packages
Overview
■ Low operating current
❐ Active current: continuous sensor scan: 1.5 mA
❐ Deep sleep current: 4 µA
These CapSense Express™ controllers support four to ten
capacitive sensing (CapSense) buttons. The device functionality
is configured through an I2C port and can be stored in onboard
nonvolatile memory for automatic loading at power-on. The
CY8C20110 is optimized for dimming LEDs in 15 selectable duty
cycles for back light applications. The device can be configured
to have up to 10 GPIOs connected to the PWM output. The PWM
duty cycle is programmable for variable LED intensities.
■ Industry's best configurability
❐ Custom sensor tuning, one optional capacitor
❐ Output supports strong drive for LED
❐ Output state can be controlled through I2C or directly from
CapSense® input state
The four key blocks that make up these devices are: a robust
capacitive sensing core with high immunity against radiated and
conductive noise, control registers with nonvolatile storage,
configurable outputs, and I2C communications. The user can
configure registers with parameters needed to adjust the
operation and sensitivity of the CapSense buttons and outputs
and permanently store the settings. The standard I2C serial
communication interface enables the host to configure the
device and read sensor information in real time. The I2C address
is fully configurable without any external hardware strapping.
❐ Run time reconfigurable over I2C
■ Advanced features
❐ All GPIOs support LED dimming with configurable delay
option in CY8C20110
❐ Interrupt outputs
❐ User defined inputs
❐ Wake on interrupt input
❐ Sleep control pin
❐ Nonvolatile storage of custom settings
❐ Easy integration into existing products – configure output to
match system
❐ No external components required
❐ World class free configuration tool
Cypress Semiconductor Corporation
Document Number: 001-54606 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 31, 2012
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................3
Pinouts ..............................................................................4
Pin Definitions ..................................................................4
Pinouts ..............................................................................5
Pin Definitions ..................................................................5
Typical Circuits .................................................................6
I2C Interface ......................................................................8
I2C Device Addressing ................................................8
I2C Clock Stretching ....................................................8
Format for Register Write and Read ...........................9
Operating Modes of I2C Commands .............................10
Normal Mode .............................................................10
Setup Mode ...............................................................10
Device Operation Modes ................................................10
Active Mode ...............................................................10
Periodic Sleep Mode .................................................10
Deep Sleep Mode ......................................................10
Sleep Control Pin ............................................................10
Interrupt Pin to Master ...................................................10
LED Dimming ..................................................................10
LED Dimming Mode 1: Change Intensity
on ON/OFF Button Status ................................................11
LED Dimming Mode 2: Flash Intensity
on ON Button Status .........................................................11
LED Dimming Mode 3: Hold Intensity
After ON/OFF Button Transition .......................................12
LED Dimming Mode 4: Toggle Intensity on ON/OFF
or OFF/ON Button Transitions ..........................................12
Registers .........................................................................13
Register Map .............................................................13
Device IDs .................................................................17
CapSense Express Commands ................................17
Register Conventions ................................................17
Layout Guidelines and Best Practices .........................18
CapSense Button Shapes .........................................18
Button Layout Design ................................................18
Recommended via Hole Placement ..........................18
Example PCB Layout Design with
Two CapSense Buttons and Two LEDs ...........................20
Operating Voltages .........................................................21
CapSense Constraints ...................................................21
Absolute Maximum Ratings ..........................................22
Operating Temperature ..................................................22
Electrical Specifications ................................................23
DC Electrical Specifications ......................................23
CapSense Electrical Characteristics .........................26
AC Electrical Specifications .......................................26
Appendix .........................................................................29
Examples of Frequently Used I2C Commands .........29
Ordering Information ......................................................30
Ordering Code Definitions .........................................30
Thermal Impedances .....................................................31
Solder Reflow Specifications ........................................31
Package Diagrams ..........................................................32
Acronyms ........................................................................35
Reference Documents ....................................................35
Document Conventions .................................................35
Units of Measure .......................................................35
Numeric Conventions ................................................35
Glossary ..........................................................................36
Document History Page .................................................41
Sales, Solutions, and Legal Information ......................43
Worldwide Sales and Design Support .......................43
Products ....................................................................43
PSoC Solutions .........................................................43
Document Number: 001-54606 Rev. *G
Page 2 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Pinouts
Figure 1. 16-pin QFN (3 × 3 × 0.6 mm) (no e-pad) pinout [1]
QFN
Pin Definitions
16-pin QFN (no e-pad) [1, 2]
Pin No.
Pin Name
GP0[0]
Description
1
2
Configurable as CapSense or GPIO
GP0[1]
Configurable as CapSense or GPIO
I2C clock
I2C data
3
I2C SCL
I2C SDA
GP1[0]
4
5
Configurable as CapSense or GPIO
6
GP1[1] [3] Configurable as CapSense or GPIO
VSS Ground connection
GP1[2] [3] Configurable as CapSense or GPIO
7
8
9
GP1[3]
GP1[4]
XRES
GP0[2]
VDD
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
10
11
12
13
14
15
Active high external reset with internal pull-down
Configurable as CapSense or GPIO
Supply voltage
GP0[3]
CSInt
Configurable as CapSense or GPIO
Integrating capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved.
Typical range is 1 nF to 4.7 nF
16
GP0[4]
Configurable as CapSense or GPIO
Notes
1. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons)
2. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
3. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
Document Number: 001-54606 Rev. *G
Page 3 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Pinouts
Figure 2. 16-pin SOIC (150 Mils) pinout [4]
Pin Definitions
16-pin SOIC [4, 5]
Pin No.
Name
Description
1
2
GP0[3]
CSint
Configurable as CapSense or GPIO
Integrating capacitor input. The external capacitance is required only if 5:1 SNR cannot be achieved.
Typical range is 1 nF to 4.7 nF.
3
4
GP0[4]
GP0[0]
GP0[1]
I2C SCL
I2C SDA
GP1[0]
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
I2C clock
5
6
7
I2C data
8
Configurable as CapSense or GPIO
9
GP1[1] [6] Configurable as CapSense or GPIO
VSS Ground connection
GP1[2] [6] Configurable as CapSense or GPIO
10
11
12
13
14
15
16
GP1[3]
GP1[4]
XRES
GP0[2]
VDD
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Active high external reset with internal pull-down
Configurable as CapSense or GPIO
Supply voltage
Notes
4. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons)
5. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
6. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
Document Number: 001-54606 Rev. *G
Page 4 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Pinouts
Figure 3. 8-pin SOIC (150 Mils) pinout
CY8C20142 (4 Button)
Pin Definitions
8-pin SOIC
CY8C20142 (4 Button)
Pin No.
Name
VSS
I2C SCL
Description
1
2
3
4
5
6
7
8
Ground
I2C Clock
I2C Data
I2C SDA
GP1[0] [7] Configurable as CapSense or GPIO
GP1[1] [7] Configurable as CapSense or GPIO
GP0[0]
GP0[1]
VDD
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Supply voltage
Important Note For information on the preferred dimensions for mounting QFN packages, see the "Application Notes for Surface
Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
Note
7. Avoid using GP1[0] and GP1[1] for driving LED. These two pins have special functions during power up which is used at factory. LEDs connected to these two pins
will blink during power up of the device.
Document Number: 001-54606 Rev. *G
Page 5 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Typical Circuits
Figure 4. Circuit 1 – Five Buttons and Five LEDs with I2C Interface
Capsense
sensor
B2
B3
VD D_C E
VDD_CE
C2
R1
C1
R2
560E
1. 2nF 560E
0.1uF
VDD_CE
U1
D1
D2
LED
Capsense
sensor
R5
R7
560E
560E
1
2
3
4
12
11
10
9
R6
560E
B4
GPO[0]
GPO[2]
XR E S
VDD_CE
R3
4.7K
R4
4. 7K
LED
GPO[1]
VDD_CE
CY8C20110
R8
330E
R9
560E
560E
D3
D4
LED
LED
I2C_SCL
I2C_SDA
GP1[4]
GP1[3]
R10
330E
R11
R12
R13
R14
560E
560E
560E
D5
LED
B1
B0
VDD_CE
Capsense
sensor
Figure 5. Circuit 2 – Two Buttons and Two LEDs with I2C Interface
Document Number: 001-54606 Rev. *G
Page 6 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Typical Circuits (continued)
Figure 6. Circuit 3 – Compatibility with 1.8 V I2C Signaling [8, 9]
Figure 7. Circuit 4 – Powering Down CapSense Express Device for Low Power Requirements [10]
Output
enable
Output
VDD
LDO
I2C Pull
UPs
LED
Master
Or
Host
SDA
SCL
CapSense Express
I2C
BUS
Notes
8. 1.8 V VDD_I2C VDD_CE and 2.4 V VDD_CE 5.25 V.
9. The I2C drive mode of the CapSense device should be configured properly before using in an I2C environment with external pull-ups. Please refer to I2C_ADDR_DM
register and its factory setting.
2
10. For low power requirements, if V is to be turned off, this concept can be used. The requirement is that the V
of CapSense Express, I C pull-ups, and LEDs
2
DD
DDs
should be from the same source such that turning off the V ensures that no signal is applied to the device while it is unpowered. The I C signals should not be
DD
driven high by the master in this situation. If a port pin or group of port pins of the master can cater to the power supply requirements of the circuit, the LDO can be
avoided.
Document Number: 001-54606 Rev. *G
Page 7 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
2
I C Interface
The CapSense Express devices support the industry standard I2C protocol, which can be used for:
■ Configuring the device
■ Reading the status and data registers of the device
■ Controlling device operation
■ Executing commands
The I2C address can be modified during configuration.
2
I C Device Addressing
The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending a one byte address:
the first 7 bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction
from master and one indicates read transfer by the master. The following table shows examples for different I2C addresses.
Table 1. I2C Address Examples
7-bit Slave Address
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
8-bit Slave Address
1
1
0(W)
1(R)
0(W)
1(W)
02
03
96
97
0
0
0
0
0
0
1
75
75
1
0
0
1
0
1
1
1
0
0
1
0
1
1
If the I2C master does not support clock stretching (a bit banged
software I2C Master), the master must wait for a specific amount
of time (as specified in Format for Register Write and Read on
page 9) for each register write and read operation before the next
bit is transmitted. The I2C master must check the SCL status (it
should be high) before the I2C master initiates any data transfer
with CapSense Express. If the master fails to do so and
continues to communicate, the communication is erroneous.
2
I C Clock Stretching
‘Clock stretching’ or ‘bus stalling’ in I2C communication protocol
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait till
the SCL is released by the slave.
When an I2C master communicates with the CapSense Express
device, the CapSense Express stalls the I2C bus after the
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I2C compliant master to communicate
with the CapSense Express device.
The following diagrams represent the ACK time delays shown in
Format for Register Write and Read on page 9 for write and read.
Document Number: 001-54606 Rev. *G
Page 8 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Figure 8. Write ACK Time Representation [11]
Figure 9. Read ACK Time Representation [12]
Format for Register Write and Read
Register write format
Start
Slave Addr + W
A
Reg Addr
A
Data
A
Data
A
. . . . .
Data
A
Stop
Register read format
Start
Start
Slave Addr + W
Slave Addr + R
A
A
Reg Addr
Data
A
A
Stop
Data
A
. . . . .
Data
N
Stop
Legends:
Master
Slave
A – ACK
N – NAK
Notes
11. Time to process the received data.
12. Time taken for the device to send next byte.
Document Number: 001-54606 Rev. *G
Page 9 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
2
Deep Sleep Mode
Operating Modes of I C Commands
Deep sleep mode provides the lowest power consumption
because there is no operation running. All CapSense scanning
is disabled during this mode. In this mode, the device wakes up
only using an external GPIO interrupt. A sleep timer interrupt
cannot wake up a device from deep sleep mode. This is treated
as a continuous sleep mode without periodic wakeups. Refer to
the application note “CapSense Express Power and Sleep
Considerations” - AN44209 for details on different sleep modes.
To get the lowest power during this mode the sleep timer
frequency should be set to 1 Hz.
Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The timings remain approximately the same for
different configurations of the slave. To reduce the
acknowledgment times in normal mode, the registers
0x06–0x09, 0x0C, 0x0D, 0x10–0x17, 0x50, 0x51, 0x57–0x60,
0x7E are given only read access. Write to these registers can be
done only in setup mode.
Setup Mode
Sleep Control Pin
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
The devices require a dedicated sleep control pin to enable
reliable I2C communication in case any sleep mode is enabled.
This is achieved by pulling the sleep control pin low to wake up
the device and start I2C communication. The sleep control pin
can be configured on any GPIO.
Device Operation Modes
Interrupt Pin to Master
CapSense Express devices are configured to operate in any of
the following three modes to meet different power consumption
requirements:
To inform the master of any button press a GPIO can be
configured as interrupt output and all CapSense buttons can be
connected to this GPIO with an OR logic operator. This can be
configured using the software tool.
■ Active Mode
■ Periodic Sleep Mode
■ Deep Sleep Mode
LED Dimming
To change the brightness and intensity of the LEDs, the host
master (MCU, MPU, DSP, and so on) must send I2C commands
and program the PWM registers to enable output pins, set duty
cycle, and mode configuration. The single PWM source is
connected to all GPIO pins and has a common user defined duty
cycle. Each PWM enabled pin has two possible outputs: PWM
and 0/1 (depending on the configuration). Four different modes
of LED dimming are possible, as shown in LED Dimming Mode
1: Change Intensity on ON/OFF Button Status on page 11 to LED
Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON
Button Transitions on page 12. The operation mode and duty
cycle of the PWM enabled pins is common. This means that one
pin cannot behave as in Mode 1 and another pin as in Mode 2.
Active Mode
In the active mode, all the device blocks including the CapSense
sub system are powered. Typical active current consumption of
the device across the operating voltage range is 1.5 mA.
Periodic Sleep Mode
Sleep mode provides an intermediate power operation mode. It
is enabled by configuring the corresponding device registers
(0x7E, 0x7F). The device goes into sleep after there is no event
for stay awake counter (Reg 0x80) number of sleep intervals.
The device wakes up on sleep interval and It scans the
capacitive sensors before going back to sleep again. If any
sensor is active, then the device wakes up. The device can also
wake up from sleep mode with a GPIO interrupt. The following
sleep intervals are supported in CapSense Express. The sleep
interval is configured through registers.
■ 1.95 ms (512 Hz)
■ 15.6 ms (64 Hz)
■ 125 ms (8 Hz)
■ 1 s (1 Hz)
Document Number: 001-54606 Rev. *G
Page 10 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
LED Dimming Mode 1: Change Intensity on ON/OFF Button Status
LED Dimming Mode 2: Flash Intensity on ON Button Status
Document Number: 001-54606 Rev. *G
Page 11 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
LED Dimming Mode 3: Hold Intensity After ON/OFF Button Transition
LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions
Note LED DIMMING is available only in CY8C20110.
Document Number: 001-54606 Rev. *G
Page 12 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Registers
Register Map
Register
Address
(in Hex)
Factory Default
I2C Max ACK
I2C Max ACK
Time in Setup
Mode (ms)
Writable Only in
SETUP Mode [13]
Name
Access
Values of Registers Time in Normal
(in Hex)
00
Mode (ms)
0.1
0.1
0.1
0.1
0.1
0.1
–
INPUT_PORT0
INPUT_PORT1
STATUS_POR0
STATUS_POR1
OUTPUT_PORT0
OUTPUT_PORT1
CS_ENABL0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
R
–
–
–
–
R
00
R
–
00
–
R
–
00
–
W
–
00
–
W
–
00
–
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
YES
YES
YES
YES
–
00
11
11
11
11
–
CS_ENABLE
00
–
GPIO_ENABLE0
GPIO_ENABLE1
INVERSION_MASK0
INVERSION_MASK1
INT_MASK0
00
–
00
–
00
0.11
0.11
–
–
00
–
YES
YES
–
00
11
11
–
INT_MASK1
00
–
STATUS_HOLD_MSK0
STATUS_HOLD_MSK1
DM_PULL_UP0
DM_STRONG0
DM_HIGHZ0
03/1F [14]
03/1F [14]
00
0.11
0.11
–
–
–
YES
YES
YES
YES
YES
YES
YES
YES
–
11
11
11
11
11
11
11
11
–
00
–
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
00
–
DM_OD_LOW0
DM_PULL_UP1
DM_STRONG1
DM_HIGHZ1
00
–
00
–
00
–
00
–
DM_OD_LOW1
PWM_ENABLE0[15]
PWM_ENABLE1[15]
PWM_MODE_DC[15]
PWM_DELAY[15]
OP_SEL_00
00
–
00
0.1
0.1
0.1
0.1
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
–
00
–
–
00
–
–
00
–
–
00
11
11
11
11
11
11
11
11
11
11
11
OPR1_PRT0_00
OPR1_PRT1_00
OPR2_PRT0_00
OPR2_PRT1_00
OP_SEL_01
–
00
–
00
–
00
–
00
–
00
OPR1_PRT0_01
OPR1_PRT1_01
OPR2_PRT0_01
OPR2_PRT1_01
OP_SEL_02
–
00
–
00
–
00
–
00
–
00
Notes
13. These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
14. The factory defaults of Reg 0x0E and 0x0F is 0x03 for 20142 device and 0x1F for 20140/60/80/10 devices.
15. These registers are available only in CY8C20110.
Document Number: 001-54606 Rev. *G
Page 13 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Register Map (continued)
Register
Address
(in Hex)
Factory Default
I2C Max ACK
I2C Max ACK
Time in Setup
Mode (ms)
Writable Only in
SETUP Mode [13]
Name
Access
Values of Registers Time in Normal
(in Hex)
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
28
64
A0
00
0A
03
Mode (ms)
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.11
0.11
–
OPR1_PRT0_02
OPR1_PRT1_02
OPR2_PRT0_02
OPR2_PRT1_02
OP_SEL_03
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
–
–
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
35
35
11
11
–
–
–
OPR1_PRT0_03
OPR1_PRT1_03
OPR2_PRT0_03
OPR2_PRT1_03
OP_SEL_04
–
–
–
–
–
OPR1_PRT0_04
OPR1_PRT1_04
OPR2_PRT0_04
OPR2_PRT1_04
OP_SEL_10
–
–
–
–
–
OPR1_PRT0_10
OPR1_PRT1_10
OPR2_PRT0_10
OPR2_PRT1_10
OP_SEL_11
–
–
–
–
–
OPR1_PRT0_11
OPR1_PRT1_11
OPR2_PRT0_11
OPR2_PRT1_11
OP_SEL_12
–
–
–
–
–
OPR1_PRT0_12
OPR1_PRT1_12
OPR2_PRT0_12
OPR2_PRT1_12
OP_SEL_13
–
–
–
–
–
OPR1_PRT0_13
OPR1_PRT1_13
OPR2_PRT0_13
OPR2_PRT1_13
OP_SEL_14
–
–
–
–
–
OPR1_PRT0_14
OPR1_PRT1_14
OPR2_PRT0_14
OPR2_PRT1_14
CS_NOISE_TH
CS_BL_UPD_TH
CS_SETL_TIME
CS_OTH_SET
CS_HYSTERISIS
CS_DEBOUNCE
–
–
–
–
–
–
YES
YES
–
–
0.11
0.11
–
Document Number: 001-54606 Rev. *G
Page 14 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Register Map (continued)
Register
Factory Default
I2C Max ACK
I2C Max ACK
Time in Setup
Mode (ms)
Writable Only in
SETUP Mode [13]
Name
Address
(in Hex)
Access
Values of Registers Time in Normal
(in Hex)
14
Mode (ms)
0.11
0.11
0.11
–
CS_NEG_NOISE_TH
CS_LOW_BL_RST
CS_FILTERING
54
55
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
–
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
–
–
14
56
20
CS_SCAN_POS_00
CS_SCAN_POS_01
CS_SCAN_POS_02
CS_SCAN_POS_03
CS_SCAN_POS_04
CS_SCAN_POS_10
CS_SCAN_POS_11
CS_SCAN_POS_12
CS_SCAN_POS_13
CS_SCAN_POS_14
CS_FINGER_TH_00
CS_FINGER_TH_01
CS_FINGER_TH_02
CS_FINGER_TH_03
CS_FINGER_TH_04
CS_FINGER_TH_10
CS_FINGER_TH_11
CS_FINGER_TH_12
CS_FINGER_TH_13
CS_FINGER_TH_14
CS_IDAC_00
57
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
–
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
64
58
–
59
–
5A
5B
5C
5D
5E
5F
–
–
–
–
–
–
60
–
61
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
0.14
62
–
64
63
–
64
64
–
64
65
–
64
66
–
64
67
–
64
68
–
64
69
–
64
6A
6B
6C
6D
6E
6F
–
64
–
0A
0A
0A
0A
0A
0A
0A
0A
0A
0A
CS_IDAC_01
–
CS_IDAC_02
–
CS_IDAC_03
–
CS_IDAC_04
–
CS_IDAC_10
70
–
CS_IDAC_11
71
–
CS_IDAC_12
72
–
CS_IDAC_13
73
–
CS_IDAC_14
74
–
75 [16]
76 [16]
77 [16]
78 [16]
79
I2C_ADDR_LOCK
DEVICE_ID
RW
R
–
–
–
–
01
0.11
0.11
0.11
0.11
11
11
11
11
7A
7B
7C
42/40/60/80/10 [17]
DEVICE_STATUS
I2C_ADDR_DM
R
03
00
RW
Notes
16. The register 0x75–0x78, 0x7D and 0x8A–0x8D are reserved.
17. The Device ID for different devices are tabulated in Device IDs on page 17.
Document Number: 001-54606 Rev. *G
Page 15 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Register Map (continued)
Register
Address
(in Hex)
Factory Default
I2C Max ACK
I2C Max ACK
Time in Setup
Mode (ms)
Writable Only in
SETUP Mode [13]
Name
Access
Values of Registers Time in Normal
(in Hex)
Mode (ms)
7D [19]
SLEEP_PIN
7E
RW
RW
RW
RW
R
YES
–
00
00
00
00
00
00
00
00
00
00
00
00
0.1
0.1
11
11
11
11
11
11
11
11
11
11
11
11
SLEEP_CTRL
7F
SLEEP_SA_CNTR
CS_READ_BUTTON
CS_READ_BLM
80
–
0.1
81
–
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
0.12
82
–
CS_READ_BLL
83
R
–
CS_READ_DIFFM
CS_READ_DIFFL
CS_READ_RAWM
CS_READ_RAWL
CS_READ_STATUSM
CS_READ_STATUSL
84
R
–
85
R
–
86
R
–
87
R
–
88
R
–
89
R
–
8A [19]
8B [19]
8C [19]
8D [19]
A0
COMMAND_REG
W
–
00
0.1
11
Notes
18. These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
19. The register 0x75–0x78, 0x7D and 0x8A–0x8D are reserved.
Document Number: 001-54606 Rev. *G
Page 16 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Device IDs
Part Number
Device ID
CY8C20142
CY8C20140
CY8C20160
CY8C20180
CY8C20110
42
40
60
80
10
Note All the Ack times specified are maximum values with all buttons enabled and filer enabled with maximum order.
CapSense Express Commands
Duration the Device is not accessible
Command [20]
Description
Executable Mode
after ACK (in ms)
W 00 A0 00 Get firmware revision
Setup/Normal
Setup/Normal
Setup/Normal
Setup/Normal
Setup/Normal
Setup/Normal
Setup
0
120
120
120
5
W 00 A0 01 Store current configuration to NVM
W 00 A0 02 Restore factory configuration
W 00 A0 03 Write NVM POR defaults
W 00 A0 04 Read NVM POR defaults
W 00 A0 05 Read current configurations (RAM)
W 00 A0 06 Reconfigure device (POR)
W 00 A0 07 Set normal mode of operation
W 00 A0 08 Set setup mode of operation
W 00 A0 09 Start scan
5
5
Setup/Normal
Setup/Normal
Setup/Normal
Setup/Normal
Setup/Normal
0
0
10
5
W 00 A0 0A Stop scan
W 00 A0 0B Get CapSense scan status
0
Register Conventions
This table lists the register conventions that are specific to this section.
Convention
Description
RW
R
Register has both read and write access
Register has only read access
Note
20. The ‘W’ indicates the write transfer. The next byte of data represents the 7-bit I2C address.
Document Number: 001-54606 Rev. *G
Page 17 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Layout Guidelines and Best Practices
CapSense Button Shapes
Button Layout Design
X: Button to ground clearance (Refer to Table 2 on page 18)
Y: Button to button clearance (Refer to Table 2 on page 18)
Recommended via Hole Placement
Table 2. Recommended Layout Guidelines and Best Practices
S. No.
Category
Button shape
Min
Max
Recommendations/Remarks
1
–
–
Solid round pattern, round with LED hole, rectangle with round
corners
2
3
Button size
5 mm
15 mm 10 mm
Button-button spacing
Equal to
button
–
8 mm [X]
ground
clearance
4
5
6
7
Button ground clearance
Ground flood-top layer
Ground flood-bottom layer
0.5 mm
2 mm
Button ground clearance = Overlay thickness [Y]
Hatched ground 7-mil trace and 45-mil grid (15% filling)
Hatched ground 7-mil trace and 70-mil grid (10% filling)
–
–
–
–
–
Trace length from sensor to
PSoC-buttons
200 mm < 100 mm
8
Trace width
0.17 mm
0.20 mm 0.17 mm (7-mil)
Document Number: 001-54606 Rev. *G
Page 18 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Table 2. Recommended Layout Guidelines and Best Practices (continued)
S. No.
Category
Trace routing
Min
Max
Recommendations/Remarks
9
–
–
Traces should be routed on the non sensor side. If any non
CapSense trace crosses CapSense trace, ensure that
intersection is orthogonal.
10
Via position for the sensors
–
–
Via should be placed near the edge of the button/slider to
reduce trace length thereby increasing sensitivity.
11
12
13
Via hole size for sensor traces
Number of vias on sensor trace
–
1
–
–
2
10-mil
1
CapSense series resistor
placement
10 mm Place CapSense series resistors close to PSoC for noise
suppression. CapSense resistors have highest priority place
them first.
14
15
DistancebetweenanyCapSense
trace to ground flood
10-mil
–
20-mil
20-mil
Device placement
–
Mount the device on the layer opposite to sensor. The
CapSense trace length between the device and sensors should
be minimum
16
17
Placement of components in
2-layer PCB
–
–
–
–
Top layer – sensor pads and
bottom layer – PSoC, other components, and traces.
Placement of components in
4-layer PCB
Top layer – sensor pads,
second layer – CapSense traces,
third layer – hatched ground,
bottom layer – PSoC, other components, and non CapSense
traces
18
19
Overlay material
–
–
–
–
Should to be non conductive material. Glass, ABS plastic,
Formica
Overlay adhesives
Adhesive should be non conductive and dielectrically
homogenous. 467MP and 468MP adhesives made by 3M are
recommended.
20
21
LED back lighting
Board thickness
–
–
–
–
Cut a hole in the sensor pad and use rear mountable LEDs.
Refer the PCB layout below.
Standard board thickness for CapSense FR4 based designs is
1.6 mm.
The recommended maximum overlay thickness is 5 mm (with external CSInt)/ 2 mm (without external CSInt). For more details refer
to the section “The Integrating Capacitor (Cint)” in AN53490.
Note Some device packages does not have CSInt pin and external capacitor cannot be connected.
Document Number: 001-54606 Rev. *G
Page 19 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Example PCB Layout Design with Two CapSense Buttons and Two LEDs
Figure 10. Top Layer
Figure 11. Bottom Layer
Document Number: 001-54606 Rev. *G
Page 20 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Operating Voltages
For details on I2C 1x ACK time, refer to Register Map on page 13 and CapSense Express Commands on page 17. I2C 4x ACK time
is approximately four times the values mentioned in these tables.
CapSense Constraints
Parameter
Min
Typ
Max
Units
Notes
Parasitic capacitance (CP) of the CapSense
sensor
–
–
30
pF
Supply voltage variation (VDD
)
–
–
±5%
–
Document Number: 001-54606 Rev. *G
Page 21 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Absolute Maximum Ratings
Parameter
TSTG
Description
Min
Typ
Max
Unit
Notes
Storage temperature
–55
25
+100
°C Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C (0 °C
to 50 °C). Extended duration
storage temperatures above 65 °C
degrade reliability
TBAKETEMP
Bake temperature
Bake time
–
125
–
See
Package
label
°C
tBAKETIME
See
package
label
72
Hours
TA
Ambient temperature with power
applied
–40
–
–
+85
°C
V
VDD
Supply voltage on VDD relative to
VSS
–0.5
+6.0
VIO
DC input voltage
VSS – 0.5
VSS – 0.5
–25
–
–
–
VDD + 0.5
VDD + 0.5
+50
V
V
VIOZ
IMIO
DC voltage applied to tristate
Maximum current into any GPIO
pin
mA
ESD
LU
Electro static discharge voltage
Latch-up current
2000
–
–
–
–
V
Human body model ESD
200
mA
Operating Temperature
Parameter
TA
TJ
Description
Min
–40
–40
Typ
–
Max
+85
Unit
°C
Notes
Ambient temperature
Junction temperature
–
+100
°C
Document Number: 001-54606 Rev. *G
Page 22 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Electrical Specifications
DC Electrical Specifications
DC Chip Level Specifications
Table 3. DC Chip Level Specifications
Parameter
VDD
Description
Supply voltage
Min
2.40
–
Typ
–
Max
5.25
2.5
Unit
Notes
V
IDD
ISB
ISB
ISB
Supply current
1.5
mA Conditions are VDD = 3.10 V,
TA = 25 °C
Deep sleep mode current with
POR and LVD active
–
–
–
2.6
2.8
5.2
4
5
µA VDD = 2.55 V, 0 °C < TA < 40 °C
µA VDD = 3.3 V, –40 °C < TA < 85 °C
µA VDD = 5.25 V, –40 °C < TA < 85 °C
Deep sleep mode current with
POR and LVD active
Deep sleep mode current with
POR and LVD active
6.4
DC GPIO Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design
guidance only.
Table 4. 5-V and 3.3-V DC GPIO Specifications
Parameter
VOH1
Description
Min
Typ
Max
Unit
Notes
High output voltage on Port 0 pins VDD – 0.2
High output voltage on Port 0 pins VDD – 0.9
High output voltage on Port 1 pins VDD – 0.2
High output voltage on Port 1 pins VDD – 0.9
–
–
V
IOH < 10 µA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
VOH2
VOH3
VOH4
VOL
–
–
–
–
–
–
V
V
V
V
IOH = 1 mA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
IOH < 10 µA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
–
IOH = 5 mA, VDD > 3.10 V, maximum
of 20 mA source current in all I/Os.
Low output voltage
–
0.75
IOL = 20 mA/pin, VDD > 3.10,
maximum of 40/60 mA sink current
on even port pins and of 40/60 mA
sink current on odd port pins.[21]
IOH1
IOH2
IOL
High output current on Port 0 pins
High output current on Port 1 pins
Low output current
0.01
0.01
–
–
–
–
1
5
mA VDD 3.1 V, maximum of 20 mA
source current in all IOs
mA VDD 3.1 V, maximum of 20 mA
source current in all IOs
20
mA VDD 3.1 V, maximum of 60 mA sink
current on pins P0_2, P1_2, P1_3,
P1_4 and 60 mA sink current on
pins P0_0, P0_1, P0_3, P0_4,
P1_0, P1_1
VIL
VIH
VIL
VIH
Input low voltage
Input high voltage
Input low voltage
Input high voltage
–
–
–
–
–
0.75
–
V
V
V
V
VDD = 3.10 V to 3.6 V.
VDD = 3.10 V to 3.6 V.
VDD = 4.75 V to 5.25 V.
VDD = 4.75 V to 5.25 V.
1.6
–
0.8
–
2.0
Note
21. The maximum sink current is 40 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 60 mA.
Document Number: 001-54606 Rev. *G
Page 23 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Table 4. 5-V and 3.3-V DC GPIO Specifications (continued)
Parameter
VH
Description
Input hysteresis voltage
Input leakage
Min
–
Typ
140
1
Max
Unit
mV
Notes
–
–
5
–
IIL
–
nA Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
pF Package and pin dependent.
Temp = 25 °C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF Package and pin dependent.
Temp = 25 °C.
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 2.90 V and
–40 °C < TA < 85 °C, respectively. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only.
Table 5. 2.7-V DC GPIO Specifications
Parameter
VOH1
Description
Min
Typ
Max
Unit
Notes
High output voltage on Port 0 pins VDD – 0.2
High output voltage on Port 0 pins VDD – 0.5
High output voltage on Port 1 pins VDD – 0.2
High output voltage on Port 1 pins VDD – 0.5
–
–
V
IOH <10 µA, maximum of 10 mA
source current in all I/Os.
VOH2
VOH3
VOH4
VOL1
–
–
–
–
–
–
V
V
V
V
IOH = 0.2 mA, maximum of 10 mA
source current in all I/Os.
IOH <10 µA, maximum of 10 mA
source current in all I/Os.
–
IOH = 2 mA, maximum of 10 mA
source current in all I/Os.
Low output voltage
–
0.75
IOL = 10 mA/pin, VDD > 3.10,
maximum of 20/30 mA sink current
on even port pins and of 20/30 mA
sink current on odd port pins. [22]
IOH
High output current
0.01
–
–
–
2
mA VDD < 2.9 V, maximum of 10 mA
source current in all I/Os
IOL1
Low output current on Port 0 pins
10
mA VDD < 2.9V, maximum of30mA sink
current on pins P0_2, P1_2, P1_3,
P1_4 and 30 mA sink current on
pins P0_0, P0_1, P0_3, P0_4,
P1_0, P1_1
IOL2
Low output current
–
–
20
mA VDD < 2.9V, maximum of50mA sink
current on pins P0_2, P1_2, P1_3,
P1_4 and 50 mA sink current on
pins P0_0, P0_1, P0_3, P0_4,
P1_0, P1_1
VIL
Input low voltage
–
–
0.75
V
VDD = 2.4 to 2.90 V and 3.10 V to
3.6 V.
VIH1
VIH2
Input high voltage
Input high voltage
1.4
1.6
–
–
–
–
V
V
VDD = 2.4 to 2.7 V.
VDD = 2.7 to 2.90 V and 3.10 V to
3.6 V.
VH
IIL
Input hysteresis voltage
Input leakage
–
–
60
1
–
–
5
mV
nA Gross tested to 1 µA.
CIN
Capacitive load on pins as input
0.5
1.7
pF Package and pin dependent.
Temp = 25 °C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF Package and pin dependent.
Temp = 25 °C
Note
22. The maximum sink current per port is 20 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 30 mA.
Document Number: 001-54606 Rev. *G
Page 24 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
DC POR and LVD Specifications
Table 6. DC POR and LVD Specifications
Parameter
Description
Min
Typ
Max
Unit
Notes
VDD value for PPOR trip
V
DD must be greater than or equal
VPPOR0
VPPOR1
V
DD = 2.7 V
DD = 3.3 V, 5 V
–
–
2.36
2.60
2.40
2.65
V
V
to 2.5 V during startup or internal
reset.
V
VLVD0
VLVD2
VLVD6
VDD value for LVD trip
V
V
DD = 2.7 V
DD = 3.3 V
2.39
2.75
3.98
2.45
2.92
4.05
2.51
2.99
4.12
V
V
V
VDD = 5 V
DC Flash Write Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C or 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash Endurance and Retention specifications
are valid only within the range: 25 °C ± 20 °C during the flash write operation. It is at the user’s own risk to operate out of this
temperature range. If flash writing is done out of this temperature range, the endurance and data retention reduces.
Table 7. DC Flash Write Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VDDIWRITE
Supply voltage for flash write
operations
2.7
–
–
V
IDDP
Supply current for flash write
operations
–
5
25
mA
FlashENPB
FlashDR
Flash endurance
50,000[23]
10
–
–
–
–
–
Erase/write cycles
Flash data retention
Years
DC I2C Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design
guidance only.
Table 8. DC I2C Specifications
Symbol [24]
VILI2C
Description
Input low level
Min
Typ
Max
Units
Notes
–
–
0.3 × VDD
V
2.4 V VDD 2.9 V
3.1 V VDD 3.6 V
–
0.7 × VDD
–
–
–
0.25 × VDD
V
V
V
4.75 V VDD 5.25 V
2.4 V VDD 5.25 V
IOL = 5 mA/pin
VIHI2C
VOLP
CI2C
Input high level
–
0.4
5
Low output voltage
Capacitive load on I2C pins
–
0.5
1.7
pF Package and pin dependent. Temp
= 25 °C.
RPU
Pull-up resistor
4
5.6
8
k
–
Notes
23. Commands involving flash writes (0x01, 0x02, 0x03) and flash read (0x04) must be executed only within the same V voltage range detected at POR (power on, or
CC
command 0x06) and above 2.7 V.
2
24. All GPIO meet the DC GPIO V and V specifications found in the DC GPIO Specifications sections. The I C GPIO pins also meet the above specs.
IL
IH
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CapSense Electrical Characteristics
Conditions for
Supply Voltage
Max (V)
Typ (V)
Min (V)
Result
3.6
3.3
3.1
< 2.9
The device automatically reconfigures itself to work in 2.7 V mode
of operation.
> 2.9 or < 3.10
< 2.45 V
This range is not recommended for CapSense usage.
2.90
5.25
2.7
5.0
2.45
The scanning for CapSense parameters shuts down until the
voltage returns to over 2.45 V.
> 3.10
The device automatically reconfigures itself to work in 3.3 V mode
of operation.
< 2.4 V
The device goes into reset.
4.75
< 4.73 V
The scanning for CapSense parameters shuts down until the
voltage returns to over 4.73 V.
AC Electrical Specifications
AC Chip-Level Specifications
Table 9. 5-V and 3.3-V AC Chip-Level Specifications
Parameter
F32K1
Description
Min
Typ
Max
Units
Notes
during
operations are done based on ILO
frequency.
Internal low-speed oscillator
(ILO) frequency
15
32
64
kHz Calculations
sleep
tXRST
External reset pulse width
10
–
–
–
–
Us
ms
tPOWERUP
Time from end of POR to CPU
executing code
150
SRPOWER_UP Power supply slew rate
–
–
250
V/ms
Table 10. 2.7-V AC Chip-Level Specifications
Parameter
F32K1
Description
Min
Typ
Max
Units
Notes
Internal low-speed oscillator
(ILO) frequency
8
32
96
kHz Calculations
during
sleep
operations are done based on ILO
frequency.
tXRST
External reset pulse width
10
–
–
–
–
Us
ms
tPOWERUP
Time from end of POR to CPU
executing code
600
SRPOWER_UP Power supply slew rate
–
–
250
V/ms
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AC GPIO Specifications
Table 11. 5-V and 3.3-V AC GPIO Specifications
Parameter
tRise0
Description
Min
Max
Unit
Notes
Rise time, strong mode,
Cload = 50 pF, Port 0
15
80
ns VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10%
to 90%
tRise1
tFall
Rise time, strong mode,
Cload = 50 pF, Port 1
15
10
50
50
ns VDD = 3.10 V to 3.6 V, 10% to 90%
Fall time, strong mode,
Cload = 50 pF, all ports
ns VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10%
to 90%
Table 12. 2.7-V AC GPIO Specifications
Parameter
tRise0
Description
Min
Max
Unit
Notes
Rise time, strong mode,
Cload = 50 pF, Port 0
15
100
ns VDD = 2.4 V to 2.90 V, 10% to 90%
ns VDD = 2.4 V to 2.90 V, 10% to 90%
ns VDD = 2.4 V to 2.90 V, 10% to 90%
tRise1
tFall
Rise time, strong mode,
Cload = 50 pF, Port 1
15
10
70
70
Fall time, strong mode,
Cload = 50 pF
AC I2C Specifications
Table 13. AC I2C Specifications
Standard Mode
Fast Mode
Parameter
FSCLI2C
Description
Units
Notes
Min
Max
Min
Max
SCL clock frequency
0
100
0
400
kbps Fast mode not
supported for
VDD < 3.0 V.
tHDSTAI2C
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated
4.0
–
0.6
–
µs
t
LOWI2C
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
µs
µs
µs
tHIGHI2C
tSUSTAI2C
Setup time for a repeated START
condition
t
HDDATI2C
Data hold time
0
–
–
–
–
0
–
–
–
–
µs
ns
µs
µs
tSUDATI2C
tSUSTOI2C
tBUFI2C
Data setup time
250
4.0
4.7
100
0.6
1.3
Setup time for STOP condition
BUS free time between a STOP
and START condition
tSPI2C
Pulse width of spikes suppressed
by the input filter
–
–
0
50
ns
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Figure 12. Definition of Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
I2C_SCL
TSUDATI2C
TSPI2C
TSUSTAI2C
TBUFI2C
THDDATI2C
THDSTAI2C
THIGHI2C TLOWI2C
TSUSTOI2C
P
S
S
Sr
Repeated START Condition
STOP Condition
START Condition
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Appendix
2
Examples of Frequently Used I C Commands
S. No.
Requirement
Enter into setup mode
Enter into normal mode
I2C commands [25]
Comment
1
2
3
W 00 A0 08
W 00 A0 07
Load factory defaults to RAM
registers
W 00 A0 02
4
5
6
Do a software reset
W 00 A0 08
W 00 A0 06
Enter into setup mode
Do software reset
Save current configuration to
flash
W 00 A0 01
Load factory defaults to RAM
registers and save as user
configuration
W 00 A0 08
W 00 A0 02
W 00 A0 01
W 00 A0 06
Enter into setup mode
Load factory defaults to SRAM
Save the configuration to flash. Wait for time specified in
CapSense Express Commands on page 17.
Do software reset
7
Enable GP00 as CapSense
button
W 00 A0 08
W 00 06 01
W 00 A0 01
W 00 A0 06
Enter into setup mode
Configuring CapSense buttons
Save the configuration to flash. Wait for time specified in
CapSense Express Commands on page 17.
Do software reset
8
9
Read CapSense button(GP00)
scan results
W 00 81 01
W 00 82
R 00 RD. RD. RD.
Select CapSense button for reading scan result
Set the read point to 82h
Consecutive 6 reads get baseline, difference count and raw
count (all two byte each)
Read CapSense button status
register
W 00 88
R 00 RD
Set the read pointer to 88
Reading a byte gets status CapSense inputs
Note
25. The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples. Similarly
‘R’ indicates the read transfer followed by 7-bit address and data byte read operations.
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Ordering Information
Table 14. Key Features and Ordering Information
Package
Operating
Temperature
CapSense
Block
Ordering Code
Package Type
GPIOs
XRES Pin
Diagram
CY8C20110-LDX2I
001-09116 16-pin QFN [26]
51-85068 16-pin SOIC
001-09116 16-pin QFN [26]
51-85068 16-pin SOIC
001-09116 16-pin QFN [26]
51-85068 16-pin SOIC
001-09116 16-pin QFN [26]
51-85068 16-pin SOIC
51-85066 8-pin SOIC
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10
10
08
08
06
06
04
04
04
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
CY8C20110-SX2I
CY8C20180-LDX2I
CY8C20180-SX2I
CY8C20160-LDX2I
CY8C20160-SX2I
CY8C20140-LDX2I
CY8C20140-SX2I
CY8C20142-SX1I
Note For die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY
8
C
201 XX - XX
X
X
I
Temperature Range:
I = Industrial
X = 2 or 1
2 = 16-pin device; 1 = 8-pin device
Pb-free
Package Type: XX = LD or S
LD = 16-pin QFN; S = 16-pin SOIC
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Controllers
Company ID: CY = Cypress
Note
26. Earlier termed as QFN package.
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Thermal Impedances
Table 15. Thermal Impedances by Package
[27]
Package
16-pin QFN[1]
Typical JA
46 °C/W
79.96 °C/W
127.22 °C/W
16-pin SOIC
8-pin SOIC
Solder Reflow Specifications
Table 16. Solder Reflow Specifications
Package
16-pin QFN[1]
Maximum Peak Temperature (TC)
Maximum Time above TC – 5 °C
30 seconds
260 C
260 C
260 C
16-pin SOIC
30 seconds
8-pin SOIC
30 seconds
Note
27. T = T + Power ×
J
A
JA.
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Package Diagrams
Figure 13. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116
001-09116 *F
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Package Diagrams (continued)
Figure 14. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *D
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Package Diagrams (continued)
Figure 15. 8-pin SOIC (150 Mils) S08.15/SZ08.15 Package Outline, 51-85066
51-85066 *E
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Acronyms
Table 17 lists the acronyms that are used in this document.
Table 17. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
LVD
Description
alternating current
low voltage detect
CMOS
DC
complementary metal oxide semiconductor
direct current
MCU
PCB
POR
microcontroller unit
printed circuit board
power on reset
EEPROM electrically erasable programmable read-only
memory
EMC
GPIO
I/O
electromagnetic compatibility
general-purpose I/O
input/output
PPOR
PSoC®
PWM
QFN
precision power on reset
Programmable System-on-Chip
pulse width modulator
quad flat no leads
IDAC
ILO
current DAC
internal low speed oscillator
liquid crystal display
low dropout regulator
light-emitting diode
least-significant bit
RF
radio frequency
LCD
LDO
LED
LSB
SOIC
SRAM
XRES
small-outline integrated circuit
static random access memory
external reset
Reference Documents
CapSense Express Power and Sleep Considerations – AN44209 (001-44209)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Conventions
Units of Measure
Table 18 lists the units of measures.
Table 18. Units of Measure
Symbol
C
Unit of Measure
Symbol
mm
Unit of Measure
degree Celsius
hertz
millimeter
millisecond
millivolt
Hz
ms
mV
nA
ns
%
kbps
kHz
k
kilo bits per second
kilohertz
nanoampere
nanosecond
percent
kilohm
LSB
µA
least significant bit
microampere
microfarad
pF
V
picofarad
volt
µF
µs
microsecond
milliampere
W
watt
mA
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
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Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
(ADC)
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that
create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
buffer
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
compiler
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
A program that translates a high level language, such as C, into machine language.
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Glossary (continued)
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
(DAC)
converter performs the reverse operation.
duty cycle
emulator
The relationship of a clock period high time to its low time, expressed as a percent.
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency
gain
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
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Glossary (continued)
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
routine (ISR)
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage
detect (LVD)
A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
modulator
noise
The reference to a circuit containing both analog and digital techniques and components.
A device that imposes a signal on a carrier.
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
parity
A circuit that may be crystal controlled and is used to generate a clock frequency.
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
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Glossary (continued)
PSoCDesigner™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
reset
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
shift register
slave device
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
SROM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
Document Number: 001-54606 Rev. *G
Page 39 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Glossary (continued)
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
A name for a power net meaning "voltage source." The most negative power supply signal.
VSS
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 001-54606 Rev. *G
Page 40 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Document History Page
Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142, CapSense® Express™ Button Capacitive
Controllers
Document Number: 001-54606
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
2741726
SLAN /
FSU
07/21/2009 New data sheet.
*A
*B
2821828
2892629
SSHH /
FSU
12/4/2009 Added Contents.
Updated Absolute Maximum Ratings (Added F32k u, tPOWERUP parameters
and their details).
Updated Electrical Specifications (Updated DC Electrical Specifications
(Updated DC Flash Write Specifications (Updated Note 23))).
NJF
03/15/2010 Updated Pin Definitions (Added a Note “For information on the preferred
dimensions for mounting QFN packages, see the "Application Notes for
Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages"
available at http://www.amkor.com.” below the column).
Updated Absolute Maximum Ratings (Added TBAKETEMP and TBAKETIME
parameters and their details).
Updated Package Diagrams (Updated Figure 1 (Changed 16-pin COL to
16-pin QFN).
*C
*D
3002214
3042142
SLAN
ARVM
07/29/2010 Updated Features (Changed the part number from CY8C21110 to
CY8C20110).
Added Acronyms and Units of Measure.
Minor edits across the document.
09/30/10
Updated Pin Definitions (Added Note 3 and referred the same Note in all
GP1[1] and GP1[2] pins).
Updated Pin Definitions (Added Note 6 and referred the same Note in all
GP1[1] and GP1[2] pins).
Updated Pin Definitions (Added Note 7 and referred the same Note in all
GP1[1] and GP1[2] pins).
Updated Absolute Maximum Ratings (Removed F32k u, tPOWERUP parameters
and their details).
Updated Electrical Specifications (Updated AC Electrical Specifications
(Added AC Chip-Level Specifications section)).
Updated Typical Circuits (Updated Figure 4 (Replaced with updated one)).
Updated in new template.
*E
3085081
NJF
11/12/10
Updated Electrical Specifications (Updated DC Electrical Specifications
(Updated DC GPIO Specifications (Removed sub-section “2.7-V DC Spec for
I2C Line with 1.8 V External Pull-up”), added DC I2C Specifications)), updated
AC Electrical Specifications (Updated AC I2C Specifications (Updated
Figure 12 (No specific changed were made to I2C Timing Diagram. Updated
for clearer understanding.)))).
Updated Solder Reflow Specifications (Updated Table 16).
Added Reference Documents and Glossary.
Updated in new template.
*F
3276234
ARVM
06/07/11
Updated Layout Guidelines and Best Practices (Updated Table 2 (Removed
“Overlay thickness-buttons” category),
added the following statement after Table 2 –
“The Recommended maximum overlay thickness is 5 mm (with external CSInt)
2 mm (without external CSInt). For more details refer to the section “The
Integrating Capacitor (Cint)” in AN53490.
/
Note Some device packages does not have CSInt pin and external capacitor
cannot be connected.”).
Updated CapSense Constraints (Removed the parameter “Overlay
thickness”).
Updated Solder Reflow Specifications (Updated Table 16).
Document Number: 001-54606 Rev. *G
Page 41 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Document History Page (continued)
Document Title: CY8C20110/CY8C20180/CY8C20160/CY8C20140/CY8C20142, CapSense® Express™ Button Capacitive
Controllers
Document Number: 001-54606
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*G
3631370
VAIR /
SLAN
05/31/2012 Updated Pin Definitions (Updated description of XRES pin).
Updated Pin Definitions (Updated description of XRES pin).
Updated Typical Circuits (Updated Figure 6 (Added Note 9 and referred the
same Note in Figure 6)).
Updated Package Diagrams (spec 001-09116 (Changed revision from *E to
*F), spec 51-85068 (Changed revision from *C to *D)).
Updated in new template.
Document Number: 001-54606 Rev. *G
Page 42 of 43
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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cypress.com/go/automotive
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psoc.cypress.com/solutions
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cypress.com/go/image
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PSoC
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USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54606 Rev. *G
Revised May 31, 2012
Page 43 of 43
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