CY8C20000-12LFXI [CYPRESS]
PSoC Programmable System-0n-Chip; 的PSoC可编程系统0N芯片
| 型号： | CY8C20000-12LFXI |
| 厂家： | 
CYPRESS |
| 描述： | PSoC Programmable System-0n-Chip |
| 文件： | 总34页 (文件大小：1450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C20234, CY8C20334
CY8C20434, CY8C20534
PSoC® Programmable System-0n-Chip™
Features
■ Low Power CapSense™ Block
■ Additional System Resources
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders, Touch-
pads, and Proximity Sensors
❐ Configurable Communication Speeds
• I2C: Selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: Configurable between 46.9 kHz and 3 MHz
❐ I2C Slave
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running up to 12 MHz
❐ Low Power at High Speed
❐ SPI Master and SPI Slave
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ 2.4V to 5.25V Operating Voltage
❐ Integrated Supervisory Circuit
❐ Industrial Temperature Range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ 8K Flash Program Storage
50,000 Erase/Write Cycles
Logic Block Diagram
❐ 512 Bytes SRAM Data Storage
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ Interrupt Controller
Port 3 Port 2 Port 1 Port 0 Config LDO
PSoC
CORE
System Bus
❐ In-System Serial Programming (ISSP)
■ Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator, and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
Global Analog Interconnect
SRAM
512 Bytes
SROM
Flash 8K
CPU Core
(M8C)
Sleep and
Watchdog
Interrupt
Controller
6/12 MHz Internal Main Oscillator
■ Precision, Programmable Clocking
❐ Internal ±5.0% 6/12 MHz Main Oscillator
❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and
Analog
Ref.
Sleep
ANALOG
SYSTEM
CapSense
Block
■ Programmable Pin Configurations
❐ Pull Up, High Z, Open Drain, and CMOS Drive Modes on All
GPIO
❐ Up to 28 Analog Inputs on GPIO
❐ Configurable Inputs on All GPIO
❐ Selectable, Regulated Digital I/O on Port 1
• 3.0V, 20 mA Total Port 1 Source Current
• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux
❐ Common Internal Analog Bus
POR and LVD
System Resets
I2C Slave/SPI
Master-Slave
Analog
Mux
SYSTEM RESOURCES
❐ Simultaneous Connection of I/O Combinations
❐ Comparator Noise Immunity
❐ Low Dropout Voltage Regulator for the Analog Array
Cypress Semiconductor Corporation
Document Number: 001-05356 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 16, 2009
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®
Figure 1. Analog System Block Diagram
PSoC Functional Overview
The
PSoCfamily
consists
of
many
Programmable
System-on-Chips with On-Chip Controller devices. These
devices are designed to replace multiple traditional MCU based
system components with one low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks and programmable interconnect. This architecture
enables the user to create customized peripheral configurations
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
IDAC
Vr
The PSoC architecture for this device family, as shown in
Figure 1, consists of three main areas: the Core, the System
Resources, and the CapSense Analog System. A common
versatile bus enables connection between I/O and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose IO (GPIO) are also
included. The GPIO provide access to the MCU and analog mux.
Reference
Buffer
Cinternal
Comparator
Mux
Mux
Refs
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO (Internal
Main Oscillator), and ILO (Internal Low speed Oscillator). The
CPU core, called the M8C, is a powerful processor with speeds
up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architecture
microprocessor.
Cap Sense Counters
CSCLK
Relaxation
CapSense
Clock Select
IMO
Oscillator
(RO)
System Resources provide additional capability such as a
configurable I2C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
Analog Multiplexer System
The Analog System consists of the CapSense PSoC block and
an internal 1.8V analog reference. Together they support capac-
itive sensing of up to 28 inputs.
The Analog Mux Bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins is
completed quickly and easily across multiple ports.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces such as sliders and
touch pads
■ Chip-wide mux that enables analog input from any I/O pin
■ Crosspoint connection between any I/O pin combinations
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, found under http://www.cypress.com >> DESIGN
RESOURCES >> Application Notes. In general, unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) requirement for CapSense
applications is 5:1.
Document Number: 001-05356 Rev. *H
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Additional System Resources
Application Notes
System Resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. Brief statements describing the
merits of each system resource are presented below.
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
■ TheI2CslaveorSPImaster-slavemoduleprovides50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
■ Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
■ An internal 1.8V reference provides an absolute reference for
capacitive sensing.
■ The 5V maximum input, 3V fixed output, low dropout regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.
Cypros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
For in depth information, along with detailed programming infor-
mation, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices.
Technical Support
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Document Number: 001-05356 Rev. *H
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Code Generation Tools
Development Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
PSoC Designer Software Subsystems
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication inter-
faces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
Hybrid Designs
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-05356 Rev. *H
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Organize and Connect
Designing with PSoC Designer
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
Select Components
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-05356 Rev. *H
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Units of Measure
Document Conventions
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 14 lists all the abbreviations used to
measure the PSoC devices.
Table 1 lists the acronyms that are used in this document.
Table 1. Acronyms Used
Numeric Naming
Acronym
AC
Description
Alternating Current
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers are also represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b or
01000011b). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimals.
API
Application Programming Interface
Central Processing Unit
Direct Current
CPU
DC
GPIO
GUI
General Purpose IO
Graphical User Interface
In-Circuit Emulator
ICE
ILO
Internal Low Speed Oscillator
Internal Main Oscillator
Input Or Output
IMO
I/O
LSb
Least Significant Bit
LVD
Low Voltage Detect
MSb
POR
PPOR
PSoC®
SLIMO
SRAM
Most Significant Bit
Power On Reset
Precision Power On Reset
Programmable System-on-Chip™
Slow IMO
Static Random Access Memory
Document Number: 001-05356 Rev. *H
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Pin Information
This section describes, lists, and illustrates the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device pins and pinout
configurations.
The CY8C20x34 PSoC device is available in a variety of packages that are listed and shown in the following tables. Every port pin
(labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable
of Digital I/O.
16-Pin Part Pinout
Figure 2. CY8C20234 16-Pin PSoC Device
AI, P2[5]
AI, P2[1]
1
2
P0[4], AI
XRES
P1[4], AI, EXTCLK
P1[2], AI
12
11
QFN
10
3
4
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
9
Table 2. Pin Definitions - CY8C20234 16-Pin (QFN)
Type
Pin No.
Name
Description
Digital
I/O
Analog
1
2
3
I
I
I
P2[5]
I/O
P2[1]
P1[7]
2
IOH
I C SCL, SPI SS
2
4
IOH
I
P1[5]
I C SDA, SPI MISO
SPI CLK
5
6
IOH
IOH
I
I
P1[3]
P1[1]
[1]
2
CLK , I C SCL, SPI MOSI
Ground Connection
7
8
Power
IOH
Vss
[1]
2
I
P1[0]
DATA , I C SDA
9
IOH
IOH
Input
I/O
I
I
P1[2]
P1[4]
XRES
P0[4]
Vdd
10
11
12
13
14
15
16
Optional External Clock Input (EXTCLK)
Active High External Reset with Internal Pull Down
I
Power
I/O
Supply Voltage
Integrating Input
I
I
I
P0[7]
P0[3]
P0[1]
I/O
I/O
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note
1. These are the ISSP pins, that are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 001-05356 Rev. *H
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24-Pin Part Pinout
Figure 3. CY8C20334 24-Pin PSoC Device
AI, P2[5]
18 P0[4], AI
17 P0[2], AI
16
1
2
3
4
5
6
AI, P2[3]
AI, P2[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
P0[0], AI
QFN
15 P2[0], AI
14
XRES
13
P1[6], AI
Table 3. Pin Definitions - CY8C20334 24-Pin (QFN) [2]
Type
Pin No.
Name
Description
Digital
I/O
Analog
1
I
I
I
I
P2[5]
2
3
4
I/O
P2[3]
P2[1]
P1[7]
I/O
2
IOH
I C SCL, SPI SS
2
5
IOH
I
P1[5]
I C SDA, SPI MISO
6
7
IOH
IOH
I
I
P1[3]
P1[1]
SPI CLK
[1]
2
CLK , I C SCL, SPI MOSI
No Connection
8
NC
9
Power
IOH
Vss
P1[0]
Ground Connection
[1]
2
10
I
DATA , I C SDA
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CP
IOH
IOH
IOH
Input
I/O
I
I
I
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Optional External Clock Input (EXTCLK)
Active High External Reset with Internal Pull Down
I
I
I
I
I
I/O
I/O
I/O
I/O
Analog Bypass
Supply Voltage
Power
I/O
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
Vss
I/O
I/O
Integrating Input
I/O
Power
Center Pad is connected to Ground
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note
2. The center pad on the QFN package is connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically
floated and not connected to any other signal.
Document Number: 001-05356 Rev. *H
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28-Pin Part Pinout
Figure 4. CY8C20534 28-Pin PSoC Device
AI P0[7]
AI P0[5]
AI P0[3]
Vdd
P0[6] AI
P0[4] AI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI P0[1]
P0[2] AI
P0[0] AI
P2[6] AI
AI P2[7]
AI P2[5]
AI P2[3]
AI P2[1]
P2[4] AI
P2[2] AI
SSOP
Vss
P2[0] AI
XRES
P1[6] AI
AI, I2C SCL P1[7]
AI, I2CSDA P1[5]
AI P1[3]
P1[4] EXTCLK, AI
P1[2] AI
P1[0] I2C SDA, AI
AI, I2C SCL P1[1]
Vss
Table 4. Pin Definitions - CY8C20534 28-Pin (SSOP)
Type
Pin No.
Name
Description
Digital
I/O
Analog
1
I
I
I
I
I
I
I
I
P0[7]
Analog Column Mux Input
Analog Column Mux Input and Column Output
2
I/O
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
Vss
3
I/O
Analog Column Mux Input and Column Output, Integrating Input
Analog Column Mux Input, Integrating Input
4
I/O
5
I/O
6
I/O
7
I/O
Direct Switched Capacitor Block Input
Direct Switched Capacitor Block Input
Ground Connection
8
I/O
9
Power
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I
I
I
I
P1[7]
P1[5]
P1[3]
P1[1]
Vss
I2C Serial Clock (SCL)
I/O
I2C Serial Data (SDA)
I/O
[1]
I/O
I2C Serial Clock (SCL), ISSP-SCLK
Power
I/O
Ground Connection
[1]
I
I
I
I
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I2C Serial Data (SDA), ISSP-SDATA
I/O
I/O
Optional External Clock Input (EXTCLK)
I/O
Input
I/O
Active High External Reset with Internal Pull Down
Direct Switched Capacitor Block Input
I
I
I
I
I
I
I
I
I/O
Direct Switched Capacitor Block Input
I/O
I/O
I/O
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Analog Column Mux Input
Supply Voltage
I/O
I/O
I/O
Power
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *H
Page 9 of 34
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CY8C20434, CY8C20534
32-Pin Part Pinout
Figure 5. CY8C20434 32-Pin PSoC Device
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
1
2
3
4
5
6
7
8
P0[0], AI
24
23 P2[6], AI
22 P2[4], AI
P2[2], AI
20 P2[0], AI
P3[2], AI
21
QFN
(Top View)
19
AI, P3[1]
SPI SS, P1[7]
AI, I2C SCL
18 P3[0], AI
17 XRES
Table 5. Pin Definitions - CY8C20434 32-Pin (QFN) [2]
Type
Pin No.
Name
Description
Digital
I/O
Analog
1
I
I
I
I
I
I
I
I
P0[1]
2
3
4
5
6
7
8
I/O
I/O
I/O
I/O
I/O
I/O
IOH
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
I2C SCL, SPI SS
I2C SDA, SPI MISO
9
IOH
I
P1[5]
10
11
IOH
IOH
I
I
P1[3]
P1[1]
SPI CLK
CLK[1], I2C SCL, SPI MOSI
Ground Connection
DATA[1], I2C SDA
12
13
Power
IOH
Vss
I
P1[0]
14
15
16
17
18
19
20
21
22
IOH
IOH
IOH
Input
I/O
I
I
I
P1[2]
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
Optional External Clock Input (EXTCLK)
Active High External Reset With Internal Pull Down
I
I
I
I
I
I/O
I/O
I/O
I/O
Document Number: 001-05356 Rev. *H
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Table 5. Pin Definitions - CY8C20434 32-Pin (QFN) [2] (continued)
Type
Pin No.
23
Name
P2[6]
Description
Digital
I/O
Analog
I
I
I
I
I
24
25
26
27
28
29
30
31
32
CP
I/O
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I/O
I/O
I/O
Analog Bypass
Supply Voltage
Power
I/O
I
I
I
P0[7]
P0[5]
P0[3]
Vss
I/O
I/O
Integrating Input
Power
Power
Ground Connection
Vss
Center Pad Is Connected to Ground
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *H
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48-Pin OCD Part Pinout
The 48-Pin QFN part table and pin diagram is for the CY8C20000 On-Chip Debug (OCD) PSoC device. This part is only used for
in-circuit debugging. It is NOT available for production.
Figure 6. CY8C20000 48-Pin OCD PSoC Device
NC
AI, P0[1]
36
35
34
33
32
31
30
P0[4], AI
1
2
P0[2], AI
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
AI, P2[7]
3
4
5
6
AI, P2[5]
AI, P2[3]
AI, P2[1]
OCD QFN
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
P2[0], AI
P3[2], AI
P3[0], AI
XRES
7
8
9
10
11
12
29
28
27
AI, I2C SDA, SPI MISO, P1[5]
NC
26
25
P1[6], AI
P1[4], EXTCLK, AI
NC
Table 6. Pin Definitions - CY8C20000 48-Pin OCD (QFN) [2]
Pin No. Digital Analog Name
Description
1
2
3
4
5
6
7
8
9
NC
No Connection
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH
I
I
I
I
I
I
I
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
I2C SCL, SPI SS
I2C SDA, SPI MISO
10
IOH
I/O
I
I
P1[5]
11
12
13
14
15
16
17
18
P0[1]
NC
No Connection
No Connection
No Connection
No Connection
SPI CLK
NC
NC
NC
IOH
IOH
I
I
P1[3]
P1[1]
Vss
CLK[1], I2C SCL, SPI MOSI
Power
Ground Connection
Document Number: 001-05356 Rev. *H
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Table 6. Pin Definitions - CY8C20000 48-Pin OCD (QFN) [2] (continued)
Pin No. Digital Analog Name
19 CCLK
Description
OCD CPU Clock Output
20
21
HCLK
P1[0]
OCD High Speed Clock Output
DATA[1], I2C SDA
IOH
IOH
I
I
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CP
P1[2]
NC
No Connection
NC
No Connection
NC
No Connection
IOH
IOH
I
I
P1[4]
P1[6]
XRES
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
NC
Optional External Clock Input (EXTCLK)
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Active High External Reset with Internal Pull Down
I
I
I
I
I
I
I
I
No Connection
NC
No Connection
NC
No Connection
I/O
I
P0[6]
Vdd
Analog Bypass
Power
Supply Voltage
OCDO
OCDE
P0[7]
P0[5]
P0[3]
Vss
OCD Odd Data Output
OCD Even Data I/O
I/O
I
I
I
I/O
I/O
Integrating Input
Power
Ground Connection
NC
No Connection
Power
Vss
Center Pad is connected to Ground
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Document Number: 001-05356 Rev. *H
Page 13 of 34
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Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC
devices. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ T ≤ 85oC and T ≤ 100oC as specified, except where mentioned.
A
J
Refer to Table 17 on page 20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 7. Voltage versus CPU Frequency and IMO Frequency Trim Options
5.25
4.75
5.25
SLIMO SLIMO SLIMO
Mode=1 Mode=1 Mode=0
4.75
3.60
SLIMO SLIMO
Mode=1 Mode=0
SLIMO
3.00
2.70
3.00
2.70
SLIMO
Mode=0
Mode=1
2.40
2.40
750 kHz
3 MHz
6 MHz
750 kHz
3 MHz
6 MHz
12 MHz
12 MHz
IMO Frequency
CPU Frequency
Table 7 lists the units of measure that are used in this section.
Table 7. Units of Measure
Symbol
oC
Unit of Measure
Symbol
μW
mA
ms
mV
nA
ns
Unit of Measure
degree Celsius
decibels
microwatts
milliampere
millisecond
millivolts
dB
fF
femto farad
hertz
Hz
KB
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
Kbit
kHz
kΩ
kilohertz
nV
W
kilohm
ohm
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
pA
pF
picoampere
picofarad
pp
peak-to-peak
parts per million
picosecond
samples per second
ppm
ps
sps
s
sigma: one standard deviation
volts
microvolts root-mean-square
V
Document Number: 001-05356 Rev. *H
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Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Min
Typ
Max
Units
oC
Notes
TSTG
-55
25
+100
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is +25oC ± 25oC.
Extended duration storage
temperatures above 65oC
degrades reliability.
TA
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
-0.5
–
–
–
–
–
–
–
+85
+6.0
oC
V
Vdd
VIO
VIOZ
IMIO
ESD
LU
Vss - 0.5
Vss - 0.5
-25
Vdd + 0.5
Vdd + 0.5
+50
V
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
V
mA
V
2000
–
–
Human Body Model ESD.
200
mA
Operating Temperature
Table 9. Operating Temperature
Symbol
TA
TJ
Description
Min
-40
-40
Typ
–
Max
+85
Units
oC
oC
Notes
Ambient Temperature
Junction Temperature
–
+100
The temperature rise from ambient
to junction is package specific. See
Table 15 on page 18. The user
mustlimitthepowerconsumptionto
comply with this requirement.
Document Number: 001-05356 Rev. *H
Page 15 of 34
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DC Electrical Characteristics
DC Chip Level Specifications
Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 10. DC Chip Level Specifications
Symbol
Vdd
IDD12
Description
Min
2.40
–
Typ
–
Max
5.25
2.5
Units
Notes
Supply Voltage
V
See Table 15 on page 18.
Supply Current, IMO = 12 MHz
1.5
mA
mA
μA
Conditions are Vdd = 3.0V,
TA = 25oC, CPU = 12 MHz.
IDD6
Supply Current, IMO = 6 MHz
–
–
1
1.5
4.
Conditions are Vdd = 3.0V,
TA = 25oC, CPU = 6 MHz
ISB27
Sleep (Mode) Currentwith POR, LVD, Sleep
Timer, WDT, and Internal Slow Oscillator
Active. Mid Temperature Range.
2.6
Vdd = 2.55V, 0oC ≤ TA ≤ 40oC
Vdd = 3.3V, -40oC ≤ TA ≤ 85oC
ISB
Sleep (Mode) Currentwith POR, LVD, Sleep
Timer, WDT, and Internal Slow Oscillator
Active.
–
2.8
5
μA
DC General Purpose IO Specifications
Unless otherwise noted, Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively.
Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C. These are for design guidance only.
Table 11. 5V and 3.3V DC GPIO Specifications
Symbol
RPU
Description
Pull Up Resistor
Min
4
Typ
5.6
–
Max
8
Units
kΩ
V
Notes
VOH1
VOH2
VOH3
VOH4
VOH5
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.2
–
IOH < 10 μA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.9
Vdd - 0.2
Vdd - 0.9
2.7
–
–
–
–
V
V
V
V
IOH = 1 mA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
IOH < 10 μA, Vdd > 3.0V, maximum
of 10 mA source current in all IOs.
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
–
–
IOH = 5 mA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
High Output Voltage
Port 1 Pins with 3.0V LDO Regulator
Enabled
3.0
3.3
IOH < 10 μA, Vdd > 3.1V, maximum
of 4 IOs all sourcing 5 mA.
VOH6
VOH7
VOH8
VOH9
High Output Voltage
Port 1 Pins with 3.0V LDO Regulator
Enabled
2.2
2.1
2.0
1.6
–
–
V
V
V
V
IOH = 5 mA, Vdd > 3.1V, maximum
of 20 mA source current in all IOs.
High Output Voltage
Port 1 Pins with 2.4V LDO Regulator
Enabled
2.4
–
2.7
–
IOH < 10 μA, Vdd > 3.0V, maximum
of 20 mA source current in all IOs.
High Output Voltage
Port 1 Pins with 2.4V LDO Regulator
Enabled
IOH<200μA, Vdd>3.0V, maximum
of 20 mA source current in all IOs.
High Output Voltage
Port 1 Pins with 1.8V LDO Regulator
Enabled
1.8
2.0
IOH < 10 μA
3.0V ≤ Vdd ≤ 3.6V
0oC ≤ TA ≤ 85oC
Maximum of 20 mA source current
in all IOs.
Document Number: 001-05356 Rev. *H
Page 16 of 34
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Table 11. 5V and 3.3V DC GPIO Specifications (continued)
Symbol
Description
High Output Voltage
Port 1 Pins with 1.8V LDO Regulator
Enabled
Min
Typ
Max
Units
Notes
VOH10
1.5
–
–
V
IOH < 100 μA.
3.0V ≤ Vdd ≤ 3.6V.
0oC ≤ TA ≤ 85oC.
Maximum of 20 mA source current
in all IOs.
VOL
Low Output Voltage
–
–
0.75
0.8
V
IOL = 20 mA, Vdd > 3.0V, maximum
of 60 mA sink current on even port
pins (for example, P0[2] and P1[4])
and 60 mA sink current on odd port
pins (for example, P0[3] and P1[5]).
VIL
VIH
VH
IIL
Input Low Voltage
–
2.0
–
–
–
V
3.6V ≤ Vdd ≤ 5.25V
3.6V ≤ Vdd ≤ 5.25V
Input High Voltage
V
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
140
1
–
–
5
mV
nA
pF
–
Gross tested to 1 μA
Package and pin dependent
Temperature = 25oC
CIN
0.5
1.7
COUT
Capacitive Load on Pins as Output
0.5
1.7
5
pF
Package and pin dependent
Temperature = 25oC
Table 12. 2.7V DC GPIO Specifications
Symbol Description
RPU Pull Up Resistor
Min
4
Typ
5.6
–
Max
8
Units
kΩ
V
Notes
VOH1
VOH2
VOL
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.2
–
IOH < 10 μA, maximum of 10 mA
source current in all IOs.
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.5
–
–
–
–
V
V
IOH = 2 mA, maximum of 10 mA
source current in all IOs.
Low Output Voltage
0.75
IOL = 10 mA, maximum of 30 mA
sink current on even port pins (for
example, P0[2] and P1[4]) and 30
mA sink current on odd port pins (for
example, P0[3] and P1[5]).
VOLP1
Low Output Voltage Port 1 Pins
–
–
0.4
V
IOL=5 mA
Maximum of 50 mA sink current on
even port pins (for example, P0[2]
and P3[4]) and 50 mA sink current
on odd port pins (for example, P0[3]
and P2[5]).
2.4V ≤ Vdd < 3.6V
VIL
Input Low Voltage
–
1.4
1.6
–
–
–
0.75
V
2.4V ≤ Vdd < 3.6V
2.4V ≤ Vdd < 2.7V
2.7V ≤ Vdd < 3.6V
VIH1
VIH2
VH
Input High Voltage
–
–
–
–
5
V
Input High Voltage
–
V
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
60
1
mV
nA
pF
IIL
–
Gross tested to 1 μA
Package and pin dependent
Temperature = 25oC
CIN
0.5
1.7
COUT
Capacitive Load on Pins as Output
0.5
1.7
5
pF
Package and pin dependent
Temperature = 25oC
Document Number: 001-05356 Rev. *H
Page 17 of 34
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DC Analog Mux Bus Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 13. DC Analog Mux Bus Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
RSW
Switch Resistance to Common Analog Bus
–
–
400
800
W
W
Vdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
DC Low Power Comparator Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C. These are for design guidance only.
Table 14. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VREFLPC Low power comparator (LPC) reference
voltage range
0.2
–
Vdd – 1 V
ISLPC
LPC supply current
LPC voltage offset
–
–
10
40
30
μA
mV
VOSLPC
2.5
DC POR and LVD Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 15. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Vdd is greater than or equal to 2.5V
during startup, reset from the XRES
pin, or reset from Watchdog.
VPPOR0
VPPOR1
VPPOR2
–
–
–
2.36
2.60
2.82
2.40
2.65
2.95
V
V
V
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.39
2.54
2.75
2.85
2.96
–
2.45
2.71
2.92
3.02
3.13
–
2.51[3]
2.78[4]
2.99[5]
3.09
3.20
–
V
V
V
V
V
V
V
V
–
4.52
–
4.73
–
4.83
Notes
3. Always greater than 50 mV above V
4. Always greater than 50 mV above V
5. Always greater than 50 mV above V
(PORLEV = 00) for falling supply.
(PORLEV = 01) for falling supply.
(PORLEV = 10) for falling supply.
PPOR
PPOR
PPOR
Document Number: 001-05356 Rev. *H
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DC Programming Specifications
Table 16 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
-40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Flash Endurance and Retention specifications with the use of
the EEPROM User Module are valid only within the range: 25°C +/-20C during the Flash Write operation. Reference the EEPROM
User Module data sheet instructions for EEPROM Flash Write requirements outside of the 25°C +/-20°C temperature window.
Table 16. DC Programming Specifications
Symbol
Description
Min
2.70
–
Typ
–
Max
–
Units
V
Notes
VddIWRITE Supply Voltage for Flash Write Operations
IDDP
VILP
VIHP
IILP
Supply Current During Programming or
Verify
5
25
mA
Input Low Voltage During Programming or
Verify
–
2.2
–
–
–
–
–
–
–
0.8
–
V
Input High Voltage During Programming or
Verify
V
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
0.2
1.5
mA
mA
Driving internal pull down resistor.
Driving internal pull down resistor.
IIHP
Input Current when Applying Vihp to P1[0]
or P1[1] During Programming or Verify
–
VOLV
VOHV
Output Low Voltage During Programming or
Verify
–
Vss + 0.75 V
OutputHighVoltageDuringProgrammingor Vdd –1.0
Verify
Vdd
V
FlashENPB Flash Endurance (per block)
FlashENT Flash Endurance (total)[6]
50,000
1,800,000
10
–
–
–
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.
–
FlashDR
Flash Data Retention
Years
Note
6. A maximum of 36 x 50,000 block endurance cycles is allowed. This is balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
Document Number: 001-05356 Rev. *H
Page 19 of 34
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AC Electrical Characteristics
AC Chip Level Specifications
Table 17, Table 18, and Table 19 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively.
Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 17. 5V and 3.3V AC Chip-Level Specifications
Symbol
FCPU1
Description
Min
0.75
15
Typ
–
Max
12.6 MHz
64 kHz
Units
Notes
CPU Frequency (3.3V Nominal)
Internal Low Speed Oscillator Frequency
12 MHz only for SLIMO Mode = 0
F32K1
32
12
FIMO12
Internal Main Oscillator Stability for 12 MHz 11.4
(Commercial Temperature)[7]
12.6 MHz
6.30 MHz
Trimmed for 3.3V operation using
factory trim values.
See Figure 7 on page 14,
SLIMO Mode = 0.
FIMO6
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
5.70
6.0
Trimmed for 3.3V operation using
factory trim values.
See Figure 7 on page 14,
SLIMO Mode = 1.
DCIMO
TRAMP
TXRST
Duty Cycle of IMO
40
0
50
–
60
–
%
Supply Ramp Time
μs
μs
External Reset Pulse Width
10
–
–
Table 18. 2.7V AC Chip Level Specifications
Symbol
FCPU1
Description
Min
0.75
8
Typ
–
Max
Units
Notes
CPU Frequency (2.7V Nominal)
Internal Low Speed Oscillator Frequency
3.25 MHz
96 kHz
F32K1
32
12
FIMO12
Internal Main Oscillator Stability for 12 MHz 11.0
(Commercial Temperature)[7]
12.9 MHz
6.40 MHz
Trimmed for 2.7V operation using
factory trim values.
See Figure 7 on page 14,
SLIMO Mode = 0.
FIMO6
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
5.60
6.0
Trimmed for 2.7V operation using
factory trim values.
See Figure 7 on page 14, SLIMO
Mode = 1.
DCIMO
TRAMP
TXRST
Duty Cycle of IMO
40
0
50
–
60
–
%
Supply Ramp Time
μs
μs
External Reset Pulse Width
10
–
–
Note
7. 0 to 70 °C ambient, Vdd = 3.3 V.
Document Number: 001-05356 Rev. *H
Page 20 of 34
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Table 19. 2.7V AC Chip Level Specifications
Symbol
FCPU1
Description
Min
0.75
8
Typ
–
Max
6.3
96
Units
Notes
CPU Frequency (2.7V Minimum)
Internal Low Speed Oscillator Frequency
MHz
kHz
F32K1
32
12
FIMO12
Internal Main Oscillator Stability for 12 MHz 11.0
(Commercial Temperature)[7]
12.9 MHz
Trimmed for 2.7V operation using
factory trim values.
See Figure 7 on page 14, SLIMO
Mode = 0.
FIMO6
Internal Main Oscillator Stability for 6 MHz
(Commercial Temperature)
5.60
6.0
6.40 MHz
Trimmed for 2.7V operation using
factory trim values.
See Figure 7 on page 14, SLIMO
Mode = 1.
DCIMO
TRAMP
TXRST
Duty Cycle of IMO
40
0
50
–
60
–
%
Supply Ramp Time
μs
μs
External Reset Pulse Width
10
–
–
AC General Purpose IO Specifications
Table 20 and Table 21 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical
parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 20. 5V and 3.3V AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
6
Units
MHz
ns
Notes
GPIO Operating Frequency
Normal Strong Mode, Port 1.
TRise023 Rise Time, Strong Mode, Cload = 50 pF
Ports 0, 2, 3
15
–
80
Vdd = 3.0 to 3.6V and 4.75V to 5.25V,
10% - 90%
TRise1
Rise Time, Strong Mode, Cload = 50 pF
Port 1
10
10
–
–
50
50
ns
ns
Vdd = 3.0 to 3.6V, 10% - 90%
TFall
Fall Time, Strong Mode, Cload = 50 pF
All Ports
Vdd = 3.0 to 3.6V and 4.75V to 5.25V,
10% - 90%
Table 21. 2.7V AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
Units
Notes
GPIO Operating Frequency
1.5
MHz
Normal Strong Mode, Port 1.
Vdd = 2.4 to 3.0V, 10% - 90%
TRise023 Rise Time, Strong Mode, Cload = 50 pF
Ports 0, 2, 3
15
–
100 ns
TRise1
Rise Time, Strong Mode, Cload = 50 pF
Port 1
10
10
–
–
70
70
ns
ns
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
TFall
Fall Time, Strong Mode, Cload = 50 pF
All Ports
Figure 8. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TFall
TRise023
TRise1
Document Number: 001-05356 Rev. *H
Page 21 of 34
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AC Comparator Amplifier Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 22. AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TCOMP
Comparator Response Time, 50 mV
Overdrive
100 ns
200 ns
Vdd ≥ 3.0V.
2.4V < Vcc < 3.0V.
AC Analog Mux Bus Specifications
Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 23. AC Analog Mux Bus Specifications
Symbol
FSW
Description
Min
Typ
Max
Units
Notes
Switch Rate
–
–
3.17 MHz
AC Low Power Comparator Specifications
Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V at 25°C. These are for design guidance only.
Table 24. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
Typ
Max
Units
μs
Notes
–
–
50
≥ 50 mV overdrive comparator
reference set within VREFLPC
.
AC External Clock Specifications
Table 25, Table 26, Table 27, and Table 28 list the guaranteed maximum and minimum specifications for the voltage and tempera-
ture ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C,
respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 25. 5V AC External Clock Specifications
Symbol
Description
Min
0.750
38
Typ
–
Max
Units
Notes
FOSCEXT
Frequency
High Period
Low Period
12.6 MHz
5300 ns
–
–
–
–
38
–
–
–
ns
Power Up IMO to Switch
150
–
μs
Table 26. 3.3V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU Clock divide by 1
0.750
–
12.6 MHz
Maximum CPU frequency is 12 MHz
at 3.3V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
41.7
41.7
150
–
–
–
5300 ns
–
–
ns
μs
Document Number: 001-05356 Rev. *H
Page 22 of 34
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Table 27. 2.7V (Nominal) AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU Clock divide by 1
0.750
–
3.080 MHz
Maximum CPU frequency is 3 MHz at
2.7V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.15
–
6.35 MHz
If the frequency of the external clock
is greater than 3 MHz, the CPU clock
divider is set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
160
160
150
–
–
–
5300 ns
–
–
ns
μs
Table 28. 2.7V (Minimum) AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU Clock divide by 1
0.750
–
6.30 MHz
Maximum CPU frequency is 6 MHz at
2.7V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
FOSCEXT
Frequency with CPU Clock divide by 2 or
greater
0.15
–
12.6 MHz
If the frequency of the external clock
is greater than 6 MHz, the CPU clock
divider is set to 2 or greater. In this
case, the CPU clock divider ensures
that the fifty percent duty cycle
requirement is met.
–
–
–
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
160
160
150
–
–
–
5300 ns
–
–
ns
μs
AC Programming Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 29. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
Description
Rise Time of SCLK
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
Fall Time of SCLK
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
TERASEB
TWRITE
TDSCLK
TDSCLK3
TDSCLK2
Flash Erase Time (Block)
–
15
30
–
–
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
–
45
50
70
3.6 < Vdd
–
–
ns
3.0 ≤ Vdd ≤ 3.6
2.4 ≤ Vdd ≤ 3.0
–
–
ns
Document Number: 001-05356 Rev. *H
Page 23 of 34
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AC SPI Specifications
Table 30 and Table 31 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical
parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 30. 5V and 3.3V AC SPI Specifications
Symbol
FSPIM
Description
Min
Typ
Max
Units
Notes
Maximum Input Clock Frequency Selection,
Master
–
–
6.3 MHz
Output clock frequency is half of input
clock rate.
FSPIS
TSS
Maximum Input Clock Frequency Selection,
Slave
–
–
–
2.05 MHz
Width of SS_ Negated Between Transmis-
sions
50
–
ns
Table 31. 2.7V AC SPI Specifications
Symbol
FSPIM
Description
Min
Typ
Max
Units
Notes
Maximum Input Clock Frequency Selection,
Master
–
–
3.15 MHz
Output clock frequency is half of input
clock rate.
FSPIS
TSS
Maximum Input Clock Frequency Selection,
Slave
–
–
–
1.025 MHz
Width of SS_ Negated Between Transmis-
sions
50
–
ns
AC I2C Specifications
Table 32 and Table 33 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical
parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.
Table 32. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Min
Max
Min
Max
400 kHz
FSCLI2C
0
100
0
THDSTAI2C
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated
4.0
–
0.6
–
μs
TLOWI2C
THIGHI2C
TSUSTAI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
Setup Time for a Repeated START
Condition
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
Data Hold Time
0
–
–
–
–
0
–
–
–
–
μs
ns
μs
μs
Data Setup Time
250
4.0
4.7
100[8]
Setup Time for STOP Condition
0.6
Bus Free Time Between a STOP and
START Condition
1.3
TSPI2C
PulseWidthofspikesaresuppressedbythe
input filter
–
–
0
50
ns
Note
2
2
8. A Fast Mode I C bus device is used in a Standard Mode I C bus system but the requirement tSU; DAT Š 250 ns is met. This automatically is the case if the device
does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax
2
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I C bus specification) before the SCL line is released.
Document Number: 001-05356 Rev. *H
Page 24 of 34
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Table 33. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency.
Units
Min
Max
Min
Max
FSCLI2C
THDSTAI2C
0
100
–
–
–
kHz
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
4.0
–
–
μs
TLOWI2C
THIGHI2C
TSUSTAI2C
LOW Period of the SCL Clock.
HIGH Period of the SCL Clock
4.7
4.0
4.7
–
–
–
–
–
–
–
–
–
μs
μs
μs
Setup Time for a Repeated START
Condition.
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
Data Hold Time.
0
–
–
–
–
–
–
–
–
–
–
–
–
μs
ns
μs
μs
Data Setup Time.
250
4.0
4.7
Setup Time for STOP Condition.
Bus Free Time Between a STOP and
START Condition.
TSPI2C
Pulse Width of spikes are suppressed by
the input filter.
–
–
–
–
ns
Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
SCL
TSPI2C
TLOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Document Number: 001-05356 Rev. *H
Page 25 of 34
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Packaging Dimensions
This section illustrates the packaging specifications for the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC devices
along with the thermal impedances for each package.
It is important to note that emulation tools require a larger area on the target PCB than the chip’s footprint. For a detailed description
of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 10. 16-Pin Chip On Lead 3 X 3 mm Package Outline (Sawn)
001-09116 *D
Document Number: 001-05356 Rev. *H
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Figure 11. 24-Pin (4 x 4 x 0.6 mm) Sawn QFN
19
24
18
1
6
13
7
12
NOTES :
1.
HATCH IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC # MO-248
3. UNIT PACKAGE W EIGHT : 0.024 grams
4. ALL DIMENSIONS ARE IN MILLIMETERS
001-13937 *B
Figure 12. 28-Pin (210-Mil) SSOP
51-85079 *C
Document Number: 001-05356 Rev. *H
Page 27 of 34
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Figure 13. 32-Pin QFN 5 x 5 mmX 0.60 Max (Sawn)
001-48913 *A
Figure 14. 32-Pin (5 x 5 mm 0.60 MAX) QFN
001-06392 *A
Document Number: 001-05356 Rev. *H
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Figure 15. 48-Pin (7 x 7 mm) QFN
SOLDERABLE
EXPOSED
PAD
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
001-12919 *A
LF48A
LY48A
STANDARD
LEAD FREE
For information on the preferred dimensions for mounting the QFN packages, see the application note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
It is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Thermal Impedances
Solder Reflow Peak Temperature
Table 34 illustrates the minimum solder reflow peak temperature
to achieve good solderability.
Table 35 illustrates the minimum solder reflow peak temperature
to achieve good solderability.
Table 34. Thermal Impedances Per Package
Table 35. Solder Reflow Peak Temperature
[9]
Package
16 QFN
24 QFN
28 SSOP
32 QFN
48 QFN
Min Peak Temperature [11] Max Peak Temperature
Package
16 QFN
24 QFN[10]
Typical θJA
46 oC/W
25 oC/W
96 oC/W
27 oC/W
28 oC/W
240oC
240oC
240oC
240oC
240oC
260oC
260oC
260oC
260oC
260oC
28 SSOP
32 QFN[10]
48 QFN[10]
Notes
9.
T = T + Power x θ
J A JA.
10. To achieve the thermal impedance specified for the QFN package, the center thermal pad is soldered to the PCB ground plane.
11. Higher temperatures is required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-05356 Rev. *H
Page 29 of 34
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CY3210-ExpressDK PSoC Express Development Kit
Development Tool Selection
The CY3210-ExpressDK is for advanced prototyping and devel-
opment with PSoC Express (used with ICE-Cube In-Circuit
Emulator). It provides access to I2C buses, voltage reference,
switches, upgradeable modules, and more. The kit includes:
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. This is used by thousands of PSoC developers. This
robust software is facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
■ PSoC Express Software CD
■ Express Development Board
■ Four Fan Modules
■ Two Proto Modules
PSoC Programmer
■ MiniProg In-System Serial Programmer
■ MiniEval PCB Evaluation Board
■ Jumper Wire Kit
PSoC Programmer is flexible enough and is used on the bench
in development and also suitable for factory programming. PSoC
Programmer works either as a standalone programming
application or operates directly from PSoC Designer or PSoC
Express. PSoC Programmer software is compatible with both
PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC
■ USB 2.0 Cable
■ Serial Cable (DB9)
programmer
is
available
free
of
charge
at
http://www.cypress.com/psocprogrammer.
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples
■ 2 CY8C27443-24PXI 28-PDIP Chip Samples
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
C Compilers
PSoC Designer comes with a free HI-TECH C Lite C compiler.
The HI-TECH C Lite compiler is free, supports all PSoC devices,
integrates fully with PSoC Designer and PSoC Express, and
runs on Windows versions up to 32-bit Vista. Compilers with
additional features are available at additional cost from their
manufactures.
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
■ HI-TECH C PRO for the PSoC is available from
http://www.htsoft.com.
CY3210-MiniProg1
■ ImageCraft Cypress Edition Compiler is available from
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
http://www.imagecraft.com.
Development Kits
All development kits are sold at the Cypress Online Store.
■ MiniProg Programming Unit
CY3215-DK Basic Development Kit
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■ Getting Started Guide
■ PSoC Designer Software CD
■ ICE-Cube In-Circuit Emulator
■ USB 2.0 Cable
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
■ Mini-Eval Programming Board
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
Document Number: 001-05356 Rev. *H
Page 30 of 34
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CY8C20434, CY8C20534
CY3210-PSoCEval1
■ MIniProg Programming Unit
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■ Mini USB Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
Device Programmers
All device programmers are purchased from the Cypress Online
Store.
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■ USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a devel-
opment board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■ Modular Programmer Base
■ 3 Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ PSoCEvalUSB Board
■ LCD Module
■ USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the
MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
Accessories (Emulation and Programming)
Table 36. Emulation and Programming Accessories
Pin
Package
Prototyping
Module
Part Number
Flex-Pod Kit [12]
Foot Kit [13]
Adapter [14]
CY8C20234-12LKXI
CY8C20334-12LQXI
CY8C20534-12PVXI
CY8C20434-12LKXI
16 SOIC
-
CY3250-16QFN-FK
CY3250-24QFN-FK
CY3250-28SSOP-FK
CY3250-32QFN-FK
CY3210-0X34
CY3210-0X34
CY3210-0X34
CY3210-0X34
-
24 QFN
28 SSOP
32 QFN
CY3250-20334QFN
-
AS-24-28-01ML-6
-
CY3250-20434QFN
AS-32-28-03ML-6
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools are specially designed by the following third party
vendors to accompany PSoC devices during development and
production. Specific details of each of these tools are found at
http://www.cypress.com under DESIGN RESOURCES >>
Evaluation Boards.
For details on emulating the circuit before going to volume pro-
duction using an on-chip debug (OCD) non-production PSoC
device, see Application Note AN2323 “Debugging - Build a
PSoC Emulator into Your Board” at http://www.cypress.com.
Notes
12. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
13. Foot kit includes surface mount feet that is soldered to the target PCB.
14. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at
http://www.emulation.com.
Document Number: 001-05356 Rev. *H
Page 31 of 34
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CY8C20234, CY8C20334
CY8C20434, CY8C20534
Ordering Information
Table 37 lists the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device’s key package features and ordering codes.
Table 37. PSoC Device Key Features and Ordering Information
Flash
SRAM Digital CapSense Digital
Analog Analog XRES
Ordering Code
Package
(Bytes) (Bytes) Blocks
Blocks
I/O Pins Inputs Outputs
Pin
13[15]
CY8C20234-12LKXI 16-Pin (3x3 mm 0.60
MAX) Sawn QFN
8K
8K
512
512
0
0
1
13
13
0
0
Yes
13[15]
CY8C20234-12LKXIT 16-Pin (3x3 mm 0.60
MAX) Sawn QFN
1
Yes
(Tape and Reel)
20[15]
20[15]
CY8C20334-12LQXI 24-Pin (4x4 mm 0.60
MAX) SAWN QFN
8K
8K
512
512
0
0
1
1
20
20
0
0
Yes
Yes
CY8C20334-12LQXIT 24-Pin (4x4 mm 0.60
MAX) Sawn QFN
(Tape and Reel)
28[15]
28[15]
CY8C20434-12LKXI 32-Pin (5x5 mm 0.60
MAX) QFN
8K
8K
512
512
0
0
1
1
28
28
0
0
Yes
Yes
CY8C20434-12LKXIT 32-Pin (5x5 mm 0.60
MAX) QFN
(Tape and Reel)
CY8C20434-12LQXI 32-Pin (5x5 mm 0.60
MAX) Thin Sawn QFN
8K
8K
512
512
0
0
1
1
28
28
28
28
0
0
Yes
Yes
CY8C20434-12LQXIT 32-Pin (5x5 mm 0.60
MAX) Thin Sawn QFN
(Tape and Reel)
CY8C20534-PVXI
CY8C20534-PVXIT
28-Pin (210-Mil) SSOP
8K
8K
512
512
0
0
1
1
24
24
24
24
0
0
Yes
Yes
28-Pin (210-Mil) SSOP
(Tape and Reel)
48-Pin OCD QFN[16]
28[15]
CY8C20000-12LFXI
8K
512
0
1
28
0
Yes
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Figure 16. Ordering Code Definitions
CY 8 C 20 xxx- 12 xx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
E = Extended
LFX/LKX/LQX = QFN Pb-Free
AX = TQFP Pb-Free
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Notes
15. Dual function Digital I/O Pins also connect to the common analog mux.
16. This part may be used for in-circuit debugging. It is NOT available for production.
Document Number: 001-05356 Rev. *H
Page 32 of 34
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CY8C20234, CY8C20334
CY8C20434, CY8C20534
Document History Page
Document Title: CY8C20234/CY8C20334/CY8C20434/CY8C20534 PSoC® Programmable System-on-Chip™
Document Number: 001-05356
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
New silicon and document (Revision **).
**
404571
418513
HMT
See ECN
See ECN
*A
HMT
Updated Electrical Specifications, including Storage Temperature and
Maximum Input Clock Frequency. Updated Features and Analog System
Overview. Modified 32-pin QFN E-PAD dimensions. Added new 32-pin QFN.
Add High Output Drive indicator to all P1[x] pinouts. Updated trademarks.
*B
490071
788177
HMT
See ECN
See ECN
Made data sheet “Final”. Added new Development Tool section. Added OCD
pinout and package diagram. Added 16-pin QFN. Updated 24-pin and 32-pin
QFN package diagrams to 0.60 MAX thickness. Changed from commercial
to industrial temperature range. Updated Storage Temperature specification
and notes. Updated thermal resistance data. Added development tool kit part
numbers. Finetuned features and electrical specifications.
*C
*D
HMT
Added CapSense SNR requirement reference. Added Low Power
Comparator (LPC) AC/DC electrical specifications tables. Added 2.7V
minimum specifications. Updated figure standards. Updated Technical
Training paragraph. Added QFN package clarifications and dimensions.
Updated ECN-ed Amkor dimensioned QFN package diagram revisions.
1356805 HMT/SFVTMP See ECN
3/HCL/SFV
Updated 24-pin QFN Theta JA. Added External Reset Pulse Width, TXRST,
specification. Fixed 48-pin QFN.vsd. Updated the table introduction and high
output voltage description in section two. The sentence: "Exceeding
maximum ratings may shorten the battery life of the device.” does not apply
to all data sheets. Therefore, the word "battery" is changed to "useful.” Took
out tabs after table and figure numbers in titles and added two hard spaces.
Updated the section, DC General Purpose IO Specifications on page 16 with
new text. Updated VOH5 and VOH6 to say, ”High Output Voltage, Port 1 Pins
with 3.0V LDO Regulator Enabled.” Updated VOH7 and VOH8 with the text,
“maximum of 20 mA source current in all IOs.”Added 28-pin SSOP part,
pinout, package. Updated specs. Modified dev. tool part numbers.
Document Number: 001-05356 Rev. *H
Page 33 of 34
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CY8C20234, CY8C20334
CY8C20434, CY8C20534
Document History Page (continued)
Document Title: CY8C20234/CY8C20334/CY8C20434/CY8C20534 PSoC® Programmable System-on-Chip™
Document Number: 001-05356
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Added 32-pin Sawn QFN Pin diagram
*E
2197347 UVS/AESA
See ECN
Removed package diagram: 32-Pin (5 X 5 mm) SAWN QFN(001-42168 *A)
Updated Ordering Information table with CY8C20434-12LQXI and
CY8C20434-12LQXIT ordering details.
Corrected Table 16. DC Programming Specifications - Included above the
table "Flash Endurance and Retention specifications with the use of the
EEPROM User Module are valid only within the range: 25°C +/-20C during
the Flash Write operation. Refer the EEPROM User Module data sheet
instructions for EEPROM Flash Write requirements outside of the 25°C
+/-20°C temperature window."
*F
2542938 RLRM/AESA
07/30/2008 Corrected Ordering Information format. Updated package diagrams
001-13937 and 001-30999. Updated data sheet template. Corrected Figure
6 (28-pin diagram).
*G
*H
2610469 SNV/PYRS
2693024 DPT/PYRS
11/20/08
Updated VOH5, VOH7, and VOH9 specifications
04/16/2009 Changed title from PSoC® Mixed Signal Array to PSoC® Programmable
System-on-Chip™
Replaced package outline drawing for 32-Pin Sawn QFN
Updated “Development Tool Selection” on page 30
Updated “Development Tools” on page 4 and “Designing with PSoC
Designer” on page 5
Updated “Getting Started” on page 3
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-05356 Rev. *H
Revised April 16, 2009
Page 34 of 34
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
2
2
herein are property of the respective corporations.Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights
2
2
to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.All products and company names mentioned in this document
may be the trademarks of their respective holders.
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