CY7C199C_06 [CYPRESS]
256K (32K x 8) Static RAM; 256K （ 32K ×8 ）静态RAM
| 型号： | CY7C199C_06 |
| 厂家： | 
CYPRESS |
| 描述： | 256K (32K x 8) Static RAM |
| 文件： | 总13页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C199C
256K (32K x 8) Static RAM
Features
General Description
• Fast access time: 12 ns
The CY7C199C is a high-performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL–compatible Inputs and Outputs
• 2.0V Data Retention
See the Truth Table in this data sheet for a complete
description of read and write modes
• Low CMOS standby power
• Automated Power-down when deselected
• Available in Pb-free and non Pb-free 28-pin (300-Mil)
Molded SOJ, 28-pin (300-Mil) DIP and 28-pin TSOP I
packages
Logic Block Diagram
Input Buffer
32K x 8
ARRAY
I/Ox
CE
WE
OE
Power
Down
Circuit
Column Decoder
A X
X
Product Portfolio
12 ns
15 ns
15
20 ns
20
Unit
ns
Maximum Access Time
12
85
Maximum Operating Current
Maximum CMOS Standby Current (L)
80
75
mA
µA
500
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05408 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C199C
Pin Layout and Specifications
28 DIP (6.9 x 35.6 x 3.5 mm)
A5
A6
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
2
A7
3
A8
4
A3
A9
5
A2
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
VSS
6
A1
7
OE
A0
8
9
CE
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A14
A13
A12
28 TSOP I (8 x 13.4 mm)
9
10
11
12
13
14
A8
A9
A10
A11
28 SOJ
A5
A6
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
2
A7
3
A8
4
A3
A9
5
A2
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
VSS
6
A1
7
OE
A0
8
9
CE
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
Document #: 38-05408 Rev. *C
Page 2 of 13
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CY7C199C
Pin Description
Pin
Type
Input
Description
DIP
SOJ
TSOP I
AX
Address Inputs
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 2, 3, 4, 5, 8, 9, 10, 11, 12,
21, 23, 24, 25, 26
21, 23, 24, 25, 26
13, 14, 15, 16, 17, 28
CE
Control
Chip Enable
20
20
27
I/OX
Input or
Output
Data
Input/Outputs
11, 12, 13, 15, 16, 17, 11, 12, 13, 15, 16, 17, 18, 18, 19, 20, 22, 23, 24, 25,
18, 19
19
22
28
14
27
26
OE
Control
Supply
Supply
Control
Output Enable
Power (5.0V)
Ground
22
1
VCC
VSS
WE
28
7
14
21
6
Write Enable
27
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)
Parameter
TSTG
Description
Value
–65 to +150
Unit
°C
°C
V
Storage Temperature
TAMB
Ambient Temperature with Power Applied (i.e., case temperature)
Core Supply Voltage Relative to VSS
–55 to +125
–0.5 to +7.0
–0.5 to VCC + 0.5
20
VCC
VIN, VOUT
IOUT
DC Voltage Applied to any Pin Relative to VSS
Output Short-Circuit Current
V
mA
V
VESD
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Latch-up Current
> 2001
ILU
> 200
mA
Operating Range
Range
Ambient Temperature (TA)
0°C to 70°C
Voltage Range (VCC
)
Commercial
Industrial
5.0V ± 10%
–40°C to 85°C
5.0V ± 10%
DC Electrical Characteristics Over the Operating Range [2]
12 ns
Max.
2.2 VCC + 0.3 2.2 VCC + 0.3 2.2 VCC + 0.3
15 ns
20 ns
Parameter
VIH
Description
Condition
Min.
Min.
Max.
Min.
Max.
Unit
V
Input HIGH Voltage
Input LOW Voltage
VIL
–0.5
2.4
0.8
–0.5
2.4
0.8
–0.5
2.4
0.8
V
VOH
OutputHIGHVoltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
V
VOL
0.4
+5
0.4
+5
0.4
+5
V
IIX
Input Leakage
Current
GND ≤ VI ≤ VCC
–5
–5
–5
–5
–5
–5
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC, Output
+5
85
30
+5
80
+5
75
30
µA
Disabled
ICC
ISB1
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = FMAX = 1/tRC
mA
Automatic CE
Power-down Current VIH or VIN ≤ VIL, f = FMAX
TTL Inputs
Max. VCC, CE ≥ VIH, VIN
≥
30
10
mA
mA
L
L
ISB2
Automatic CE
Power-down Current VIN ≥ VCC – 0.3V, or VIN
CMOS Inputs 0.3V, f = 0
Max. VCC, CE ≥ VCC – 0.3V,
10
10
10
mA
≤
500
µA
Note:
2.
V (min) = –2.0V for pulse durations of less than 20 ns.
IL
Document #: 38-05408 Rev. *C
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CY7C199C
Capacitance[3]
Max.
Parameter
CIN
Description
Conditions
ALL – PACKAGES
Unit
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
8
8
pF
COUT
Thermal Resistance[4]
Parameter
Description
Conditions
TSOP I
SOJ
DIP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5
square inch, two–layer printed
circuit board
88.6
79
69.33
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
21.94
41.42
31.62
AC Test Loads and Waveforms
R1
R1
ALL INPUT PULSES
90%
VCC
VCC
3.0V
90%
10%
10%
GND
C1
C2
R2
R2
≤ 1V/ns
≤ 1V/ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIGAND
SCOPE
(a)
(b)
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
output load
output load for
tHZOE, HZCE, HZWE
t
t
Rth
VT
Notes:
3. Tested initially and after any design or process change that may affect these parameters.
4. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
Document #: 38-05408 Rev. *C
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CY7C199C
AC Test Conditions
Parameter
Description
Nom.
30
Unit
C1
Capacitor 1
pF
C2
Capacitor 2
5
R1
Resistor 1
480
255
167
1.73
Ω
R2
Resistor 2
RTH
VTH
Resistor Thevenin
Voltage Thevenin
V
AC Electrical Characteristics[5, 6, 7]
12 ns
15 ns
20 ns
Parameter
tRC
Description
Read Cycle Time
Min
Max
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
20
tAA
Address to Data Valid
Data Hold from Addres Change
CE to Data Valid
12
15
20
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
3
12
5
15
7
20
9
OE to Data Valid
OE to Low Z
0
3
0
0
3
0
0
3
0
OE to High Z
5
5
7
7
9
9
CE to Low Z
CE to High Z
CE to Power-up
tPD
CE to Power-down
Write Cycle Time
12
15
20
tWC
12
9
15
10
10
0
20
15
15
0
tSCE
tAW
CE to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
9
tHA
0
tSA
0
0
0
tPWE
tSD
8
9
15
10
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
8
9
tHD
0
0
tHZWE
tLZWE
7
7
10
3
3
3
Notes:
5. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write.
7.
t
, t
, t
are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage.
HZOE HZCE HZWE
Document #: 38-05408 Rev. *C
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CY7C199C
Data Retention Characteristics[8]
ALL
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Condition
Min.
2.0
–
Max.
–
Unit
V
ICCDR
VCC = VDR=2.0V, CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
150
–
µA
ns
tCDR
Chip Deselect to Data
Retention Time
0
tR
Operation Recovery Time
200
–
µs
Timing Waveforms
Data Retention Waveform
VCC
DATA RETENTION MODE
tCDR
tR
CE
Read Cycle No. 1[11, 10]
tRC
Address
Data Out
tAA
tOHA
Previous Data Valid
Data Valid
Notes:
8. L-version only.
9. Device is continuously selected. OE = V = CE.
IL
10. WE is HIGH for Read Cycle.
Document #: 38-05408 Rev. *C
Page 6 of 13
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CY7C199C
Timing Waveforms (continued)
Read Cycle No. 2[11, 12]
tRC
Address
CE
tHZCE
tACE
OE
tDOE
tHZOE
tLZOE
High Z
High Z
Data Out
Data Valid
tLZCE
tPU
tPD
ICC
VCC
50%
50%
ISB
Current
Write Cycle No. 1 (WE Controlled)[13, 14, 15]
tWC
Address
CE
tSCE
tAW
tHA
tPWE
tSA
WE
OE
tHD
tHZOE
tSD
Undefined
Data In/Out
Data-In Valid
see footnotes
Notes:
11. This cycle is OE Controlled and WE is HIGH read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. This cycle is WE controlled, OE is HIGH during write.
14. Data In/Out is high impedance if OE = V
.
IH
15. During this period the I/Os are in output state and input signals should not be applied.
Document #: 38-05408 Rev. *C
Page 7 of 13
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CY7C199C
Timing Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[14, 16, 17]
tWC
Address
CE
tSCE
tSA
tHA
tAW
WE
tSD
Data-In Valid
tHD
High Z
High Z
Data In/Out
Write Cycle No. 3 (WE Controlled, OE Low)[18]
tWC
Address
CE
tSCE
tAW
tHA
tPWE
tSA
WE
tHD
tSD
Data-In Valid
Data
In/Out
Undefined
See Footnotes
Undefined
see footnotes
tHZWE
tLZWE
Notes:
16. This cycle is CE controlled.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of t
and t
.
HZWE
SD
Document #: 38-05408 Rev. *C
Page 8 of 13
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CY7C199C
Truth Table
CE
H
L
WE
X
OE
X
Input/Output
Mode
Deselect/Power-Down
Read
Power
High Z
Standby (ISB
)
H
L
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC)
)
L
L
X
Write
)
L
H
H
Deselect
Ordering Information
Package
Operating
Range
Speed
Ordering Code
CY7C199C–12VC
CY7C199C–12VXC
CY7C199C–12ZXC
CY7C199C–12VI
Name
Package Type
12
51-85031
28-pin (300-Mil) Molded SOJ
Commercial
28-pin (300-Mil) Molded SOJ (Pb-Free)
28-pin TSOP I (Pb-Free)
51-85071
51-85031
51-85014
28-pin (300-Mil) Molded SOJ
28-pin (300-Mil) DIP
Industrial
15
CY7C199C–15PC
CY7C199C–15PXC
CY7C199C–15ZC
CY7C199C–15ZXC
CY7C199C–15VC
CY7C199C–15VXC
CY7C199CL–15VC
CY7C199CL–15VXC
CY7C199C–15VI
Commercial
28-pin (300-Mil) DIP (Pb-Free)
28-pin TSOP I
51-85071
51-85031
28-pin TSOP I (Pb-Free)
28-pin (300-Mil) Molded SOJ
28-pin (300-Mil) Molded SOJ (Pb-Free)
28-pin (300-Mil) Molded SOJ
28-pin (300-Mil) Molded SOJ (Pb-Free)
28-pin (300-Mil) Molded SOJ
28-pin TSOP I (Pb-Free)
51-85031
51-85071
Industrial
Industrial
20
CY7C199C–20ZXI
Document #: 38-05408 Rev. *C
Page 9 of 13
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CY7C199C
Package Diagrams
28-pin TSOP 1 (8 x 13.4 mm) (51-85071)
51-85071-*G
Document #: 38-05408 Rev. *C
Page 10 of 13
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CY7C199C
Package Diagrams (continued)
28-pin (300-Mil) Molded SOJ (51-85031)
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
3. DIMENSIONS IN INCHES
MAX.
DETAIL
A
PIN 1 ID
EXTERNAL LEAD DESIGN
14
1
0.291
0.300
0.330
0.350
0.026
0.032
0.013
0.019
15
28
0.014
0.020
OPTION 1
OPTION 2
0.697
0.713
SEATING PLANE
0.120
0.140
0.007
0.013
0.004
A
0.262
0.272
0.050
TYP.
0.025 MIN.
51-85031-*C
Document #: 38-05408 Rev. *C
Page 11 of 13
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CY7C199C
Package Diagrams (continued)
28-pin (300-Mil) PDIP (51-85014)
SEE LEAD END OPTION
14
1
MIN.
DIMENSIONS IN INCHES [MM]
MAX.
REFERENCE JEDEC MO-095
PACKAGE WEIGHT: 2.15 gms
0.260[6.60]
0.295[7.49]
15
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.009[0.23]
0.012[0.30]
0.115[2.92]
0.160[4.06]
3° MIN.
0.015[0.38]
0.060[1.52]
0.055[1.39]
0.065[1.65]
0.310[7.87]
0.385[9.78]
0.090[2.28]
0.110[2.79]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
51-85014-*D
LEAD END OPTION
(LEAD #1, 14, 15 & 28)
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05408 Rev. *C
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C199C
Document History Page
Document Title: CY7C199C 256K (32K x 8) Static RAM
Document Number: 38-05408
Issue
Date
Orig. of
Change
REV.
**
ECN No.
129233
129697
Description of Change
09/11/03
09/15/03
HGK
KKV
New Data Sheet
Minor change:
*A
Move Product Portfolio from page 4 to page 1
Move Truth table from page 9 to page 3
*B
*C
341574
492500
See ECN
See ECN
PCI
Added Lead-Free part to Ordering info on Page #10
Removed 25 ns speed bin
Changed the description of IIX from Input Load Current to Input Leakage
NXR
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the ordering information table
Document #: 38-05408 Rev. *C
Page 13 of 13
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