CY7C199D-10VXIT [CYPRESS]
256 K (32 K Ã 8) Static RAM; 256 K（ 32 K A ?? 8 ）静态RAM
| 型号： | CY7C199D-10VXIT |
| 厂家： | 
CYPRESS |
| 描述： | 256 K (32 K Ã 8) Static RAM |
| 文件： | 总14页 (文件大小：476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C199D
256 K (32 K × 8) Static RAM
256
K (32 K × 8) Static RAM
Features
Functional Description
■ Temperature ranges
❐ –40 °C to 85 °C
The CY7C199D is a high performance CMOS static RAM
organized as 32,768 words by 8-bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
output enable (OE) and tri-state drivers. This device has an
automatic power-down feature, reducing the power consumption
when deselected. The input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE LOW and WE LOW).
■ Pin and function compatible with CY7C199C
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 80 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 3 mA
Write to the device by taking chip enable (CE) and write enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A14).
■ 2.0 V data retention
■ Automatic power-down when deselected
Read from the device by taking chip enable (CE) and output
enable (OE) LOW while forcing write enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appears on the I/O pins.
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 28-pin 300-Mil-wide molded small outline
J-lead package (SOJ) and 28-pin thin small outline package
(TSOP) I packages
Logic Block Diagram
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Cypress Semiconductor Corporation
Document Number: 38-05471 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 2, 2011
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CY7C199D
Contents
Pin Configuration .............................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Switching Characteristics ................................................6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
Switching Waveforms ......................................................7
Truth Table ........................................................................9
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagrams ..........................................................10
Acronyms ........................................................................12
Document Conventions .................................................12
Units of Measure .......................................................12
Document History Page .................................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC Solutions .........................................................14
Document Number: 38-05471 Rev. *I
Page 2 of 14
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CY7C199D
Pin Configuration
Figure 1. 28-pin SOJ (Top View)
Figure 2. 28-pin TSOP I (Top View)
OE
22
23
24
25
26
27
28
1
2
3
4
5
6
A
0
21
A
A
A
A
1
2
3
4
20 CE
A
A
A
A
A
V
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CC
19
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
WE
A
4
A
3
WE
A
TSOP I
Top View
(not to scale)
V
2
CC
A
A
A
A
A
A
10
11
12
13
14
1
A
A
5
6
7
GND
I/O
OE
13
2
1
0
A
A
A
A
0
12 I/O
CE
I/O
I/O
I/O
I/O
I/O
8
9
11
10
9
I/O
7
A
A
A
14
I/O
I/O
I/O
A
A
0
1
2
6
5
4
3
10
11
13
12
7
8
GND
Selection Guide
Description
-10 (Industrial)
Unit
ns
Maximum access time
10
80
3
Maximum operating current
mA
mA
Maximum CMOS standby current
Document Number: 38-05471 Rev. *I
Page 3 of 14
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CY7C199D
DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage ........................................ > 2,001 V
(per MIL-STD-883, method 3015)
Storage temperature ................................ –65 C to +150 C
Latch-up current ................................................... > 140 mA
Ambient temperature with
power applied .......................................... –55 C to +125 C
Operating Range
Supply voltage on
CC to relative GND [1] ................................–0.5 V to +6.0 V
Ambient
V
Range
VCC
Speed
Temperature
DC voltage applied to outputs
in high Z State [1] ................................–0.5 V to VCC + 0.5 V
Industrial –40 C to +85 C 5 V 0.5 V
10 ns
Electrical Characteristics
Over the operating range
CY7C199D-10
Parameter
VOH
Description
Test Conditions
Unit
Min
2.4
–
Max
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [1]
Input LOW voltage [1]
Input leakage current
Output leakage current
IOH = –4.0 mA
IOL = 8.0 mA
–
0.4
V
VOL
VIH
VIL
IIX
V
2.2
–0.5
–1
–1
–
VCC + 0.5
0.8
V
V
GND < VI < VCC
+1
µA
µA
mA
mA
mA
mA
mA
IOZ
ICC
GND < VO < VCC, output disabled
+1
VCC operating supply current VCC = VCC(max)
OUT = 0 mA,
f = fmax = 1/tRC
,
100 MHz
83 MHz
66 MHz
40 MHz
80
I
–
72
–
58
–
37
ISB1
ISB2
Automatic CE power-down
current— TTL Inputs
VCC = VCC(max), CE > VIH,
VIN > VIH or VIN < VIL, f = fmax
–
10
Automatic CE power-down
current— CMOS Inputs
VCC = VCC(max), CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0
–
3
mA
Note
1.
V
= –2.0 V and V
= V + 1 V for pulse durations of less than 5 ns.
IH(max) CC
IL(min)
Document Number: 38-05471 Rev. *I
Page 4 of 14
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CY7C199D
Capacitance
Parameter [2]
Description
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max
Unit
pF
CIN
Input capacitance
8
8
COUT
Output capacitance
pF
Thermal Resistance
Parameter [2]
Description
Test Conditions
28-pin SOJ 28-pin TSOP I Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.16
54.65
C/W
JC
Thermal resistance
(junction to case)
40.84
21.49
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [3]
Z = 50
ALL INPUT PULSES
90%
OUTPUT
3.0 V
10%
GND
90%
10%
50
1.5 V
30pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time: 3 ns
Fall Time: 3 ns
(b)
(a)
High Z characteristics:
R1 480
5 V
OUTPUT
R2
255
5 pF
INCLUDING
JIG AND SCOPE
(c)
Notes
2. Tested initially and after any design or process changes that may affect these parameters.
3. AC characteristics (except high Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 3 (c).
Document Number: 38-05471 Rev. *I
Page 5 of 14
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CY7C199D
Switching Characteristics
Over the operating range
CY7C199D-10
Parameter [4]
Description
Unit
Min
Max
Read Cycle
[5]
tpower
tRC
VCC(typical) to the first access
100
10
–
–
–
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
tAA
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
10
–
tOHA
tACE
tDOE
3
–
10
5
–
[6]
tLZOE
tHZOE
tLZCE
tHZCE
0
–
[6, 7]
[6]
OE HIGH to high Z
–
5
CE LOW to low Z
3
–
[6, 7]
CE HIGH to high Z
–
5
[8]
tPU
CE LOW to power-up
CE HIGH to power-down
0
–
[8]
tPD
–
10
Write Cycle [9, 10]
tWC
tSCE
tAW
Write cycle time
10
7
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
7
tHA
0
tSA
0
tPWE
tSD
7
Data setup to write end
Data hold from write end
WE LOW to high Z
6
tHD
0
[6]
tHZWE
–
[6, 7]
tLZWE
WE HIGH to low Z
3
Notes
4. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the
specified I /I and 30-pF load capacitance.
OL OH
5.
t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
POWER CC
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7.
t
, t
, and t
are specified with C = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured 200 mV from steady-state voltage.
HZOE HZCE
HZWE L
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write
by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t .
SD
HZWE
Document Number: 38-05471 Rev. *I
Page 6 of 14
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CY7C199D
Data Retention Characteristics
Over the operating range
Parameter
VDR
ICCDR
Description
VCC for data retention
Conditions
Min
2.0
–
Max
–
Unit
V
Data retention current
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
3
mA
[11]
tCDR
Chip deselect to data retention time
Operation recovery time
0
–
–
ns
ns
[12]
tR
15
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
4.5 V
4.5 V
V
DR
> 2 V
t
t
R
CDR
Switching Waveforms
Figure 4. Read Cycle No. 1: Address Transition Controlled [13, 14]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
Figure 5. Read Cycle No. 2 OE Controlled [14, 15]
DATA VALID
t
RC
CE
OE
t
ACE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
VCC
SUPPLY
CURRENT
ICC
ISB
50%
50%
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V ramp from V to V > 50 µs or stable at V > 50 µs.
CC(min)
CC
DR
CC(min)
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05471 Rev. *I
Page 7 of 14
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CY7C199D
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1: CE Controlled [16, 17, 18]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Figure 7. Write Cycle No. 3 WE Controlled, OE LOW [18, 19]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
NOTE 20
DATAIN VALID
DATA IO
t
t
LZWE
HZWE
Notes
16. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
17. Data I/O is high impedance if OE = V
.
IH
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
20. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 38-05471 Rev. *I
Page 8 of 14
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CY7C199D
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
Mode
Deselect/power-down
Read
Power
High Z
Data out
Data in
High Z
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
)
L
L
X
Write
)
L
H
H
Deselect, output disabled
)
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
CY7C199D-10VXI
CY7C199D-10ZXI
10
51-85031 28-pin (300-Mil) Molded SOJ (Pb-free)
51-85071 28-pin TSOP Type I (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
I
CY
7
C
1
9
9
D - XX
X
X
Temperature Grade: I
I = Industrial
Pb-free
Package Type: V or Z
V = 28 pin (300-Mil) Molded SOJ
Z = 28 pin TSOP Type 1
Speed Grade: 10 ns
Process Technology: 90 nm
Bus Width = × 8
Density = 256 K
Fast SRAM Family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05471 Rev. *I
Page 9 of 14
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CY7C199D
Package Diagrams
Figure 8. 28-pin SOJ 300-Mils V28.3 (Molded SOJ V21)
51-85031 *D
Document Number: 38-05471 Rev. *I
Page 10 of 14
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CY7C199D
Package Diagrams (continued)
Figure 9. 28-pin TSOP Type 1 (8 × 13.4 × 1.2 mm) Z28 (Standard)
51-85071 *I
Document Number: 38-05471 Rev. *I
Page 11 of 14
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CY7C199D
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
chip enable
Symbol
°C
Unit of Measure
CMOS
I/O
complementary metal oxide semiconductor
input/output
degree Celsius
micro Amperes
micro seconds
milli Amperes
milli meter
µA
µs
mA
mm
ns
OE
output enable
SOJ
SRAM
TSOP
TTL
small outline J-lead
static random access memory
thin small outline package
transistor-transistor logic
write enable
nano seconds
pico Farad
Volts
pF
V
WE
W
Watts
Document Number: 38-05471 Rev. *I
Page 12 of 14
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CY7C199D
Document History Page
Document Title: CY7C199D, 256 K (32 K × 8) Static RAM
Document Number: 38-05471
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
201560
233728
SWI
See ECN Advance Information datasheet for C9 IPP
*A
RKF
See ECN DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in Ordering Information
*B
262950
RKF
See ECN Removed 28-LCC Pinout and Package Diagrams
Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics table
Shaded Ordering Information
*C
*D
307594
820660
RKF
VKN
See ECN Reduced Speed bins to -10, -12 and -15 ns
See ECN Converted from Preliminary to Final
Removed 12 ns and 15 ns speed bin
Removed Commercial Operating range
Removed “L” part
Removed 28-pin PDIP and 28-pin SOIC package
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2
Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin
Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins
Updated Thermal Resistance table
Updated Ordering Information Table
*E
2745093
VKN
See ECN Included 28-Pin SOIC package
Changed VIH level from 2.0V to 2.2V
For Industrial grade, changed tSD from 5 ns to 6 ns, and tHZWE from 6 ns to 5 ns
Included Automotive-E information
*F
2897087
3023234
AJU
03/22/10
Removed obsolete parts from ordering information table
Updated package diagrams
*G
RAME
09/06/2010 Added Auto-E SOIC package related info
Changed TDOE spec from 10 ns to 11 ns in CY7C199D-25.
Added Ordering Code Definitions.
Added Acronyms and Document Conventions.
*H
*I
3130763
3271782
PRAS
PRAS
01/07/11
Dislodged Automotive information to a new datasheet (001-65530)
06/02/2011 Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM System
Guidelines.”).
Updated Package Diagrams.
Updated in new template.
Document Number: 38-05471 Rev. *I
Page 13 of 14
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CY7C199D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05471 Rev. *I
Revised June 2, 2011
Page 14 of 14
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