CY7C199D-10VXI [CYPRESS]
256K (32K x 8) Static RAM; 256K （ 32K ×8 ）静态RAM
| 型号： | CY7C199D-10VXI |
| 厂家： | 
CYPRESS |
| 描述： | 256K (32K x 8) Static RAM |
| 文件： | 总10页 (文件大小：930K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C199D
256K (32K x 8) Static RAM
Features
Functional Description [1]
• Pin- and function-compatible with CY7C199C
• High speed
The CY7C199D is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE) and tri-state drivers. This device has
an automatic power-down feature, reducing the power
consumption when deselected. The input and output pins (IO0
through IO7) are placed in a high-impedance state when:
— tAA = 10 ns
• Low active power
— ICC = 80 mA @ 10 ns
• Low CMOS standby power
— ISB2 = 3 mA
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• 2.0V Data Retention
• When the write operation is active(CE LOW and WE LOW)
• Automatic power-down when deselected
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight IO pins (IO0
through IO7) is then written into the location specified on the
address pins (A0 through A14).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the IO pins.
• Available in Pb-free 28-pin 300-Mil wide Molded SOJ and
28-pin TSOP I packages
Logic Block Diagram
IO
0
INPUT BUFFER
IO
1
A
0
A
1
IO
2
A
2
A
3
4
5
6
7
8
9
32K x 8
ARRAY
IO
3
A
A
A
A
A
A
IO
4
IO
5
IO
6
CE
IO
POWER
DOWN
7
COLUMN DECODER
WE
OE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05471 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 01, 2007
[+] Feedback
CY7C199D
Pin Configurations
SOJ
Top View
22
23
OE
A
21
20
A
0
A
A
V
CC
28
27
26
1
2
3
4
5
6
5
1
CE
IO
IO
IO
IO
IO
GND
IO
IO
1
IO
WE
A
4
6
A
A
A
24
2
3
4
19
18
17
16
7
6
A
A
7
25
26
27
28
1
8
A
3
25
24
5
4
3
A
9
TSOP I
Top View
(not to scale)
A
2
A
1
WE
A
10
A
11
23
22
V
CC
15
14
13
A
A
A
A
A
7
5
6
7
OE
A
0
A
12
A
13
A
14
2
3
21
20
19
18
17
16
15
8
9
10
11
12
13
2
CE
IO
12
11
4
5
8
9
0
7
A
A
A
10
9
IO
IO
IO
IO
IO
14
0
1
2
6
5
A
6
7
10
13
12
A
11
8
IO
IO
4
3
GND
14
Selection Guide
CY7C199D-10
Unit
Maximum Access Time
10
80
3
ns
Maximum Operating Current
mA
mA
Maximum CMOS Standby Current
Document #: 38-05471 Rev. *D
Page 2 of 10
[+] Feedback
CY7C199D
DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current ................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND [2] ... –0.5V to +6.0V
Operating Range
Ambient
Range
VCC
Speed
DC Voltage Applied to Outputs
in High-Z State [2]...................................–0.5V to VCC + 0.5V
Temperature
Industrial
–40°C to +85°C 5V ± 0.5V
10 ns
Electrical Characteristics (Over the Operating Range)
7C199D-10
Parameter
Description
Output HIGH Voltage
Test Conditions
Min
Max
Unit
V
VOH
VOL
VIH
VIL
IOH=–4.0 mA
2.4
Output LOW Voltage
IOL=8.0 mA
0.4
VCC + 0.5
0.8
V
Input HIGH Voltage [2]
Input LOW Voltage [2]
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
2.0
–0.5
–1
V
V
IIX
GND < VI < VCC
+1
µA
µA
mA
mA
mA
mA
mA
IOZ
ICC
GND < VO < VCC, Output Disabled
–1
+1
VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
80
83 MHz
66 MHz
40 MHz
72
58
37
ISB1
ISB2
Automatic CE
Power-down Current— TTL Inputs
Max VCC, CE > VIH,
IN > VIH or VIN < VIL, f = fmax
10
V
Automatic CE
Max VCC, CE > VCC – 0.3V
3
mA
Power-down Current— CMOS Inputs
VIN > VCC – 0.3V or VIN < 0.3V, f = 0
Note:
2. V (min) = –2.0V and V (max) = V + 1V for pulse durations of less than 5 ns.
IL
IH
CC
Document #: 38-05471 Rev. *D
Page 3 of 10
[+] Feedback
CY7C199D
Capacitance [3]
Parameter
Description
Test Conditions
Max
8
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz, VCC = 5.0V
COUT
8
pF
Thermal Resistance [3]
Parameter
Description
Test Conditions
SOJ
TSOP I
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.16
54.65
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
40.84
21.49
°C/W
AC Test Loads and Waveforms [4]
Z = 50Ω
ALL INPUT PULSES
90%
OUTPUT
3.0V
GND
90%
10%
10%
50Ω
30pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Rise Time: ≤ 3 ns
Fall Time: ≤ 3 ns
(b)
(a)
High-Z characteristics:
R1 480Ω
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND SCOPE
(c)
Notes:
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05471 Rev. *D
Page 4 of 10
[+] Feedback
CY7C199D
Switching Characteristics (Over the Operating Range) [5]
7C199D-10
Parameter
Read Cycle
Description
Min
Max
Unit
[6]
tpower
tRC
VCC(typical) to the first access
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
10
tOHA
tACE
tDOE
3
10
5
[7]
tLZOE
tHZOE
tLZCE
tHZCE
0
3
0
[7, 8]
[7]
OE HIGH to High-Z
5
5
CE LOW to Low-Z
[7, 8]
CE HIGH to High-Z
[9]
tPU
CE LOW to Power-up
CE HIGH to Power-down
[9]
tPD
10
Write Cycle [10, 11]
tWC
tSCE
tAW
tHA
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
7
0
tSA
0
tPWE
tSD
7
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
5
tHD
0
[7]
tHZWE
6
[7, 8]
tLZWE
WE HIGH to Low-Z
3
Notes:
5. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of
the specified I /I and 30-pF load capacitance.
OL OH
6. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
CC
POWER
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
[4]
HZWE
LZWE
8. t
, t
, and t
are specified with C = 5 pF as in part (b) of “AC Test Loads and Waveforms ” on page 4. Transition is measured ±200 mV from steady-state voltage.
HZOE HZCE
HZWE L
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05471 Rev. *D
Page 5 of 10
[+] Feedback
CY7C199D
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min
Max
Unit
V
VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0
ICCDR
Data Retention Current
3
mA
ns
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[12]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
4.5V
4.5V
V
DR
> 2V
t
t
R
CDR
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [13, 14]
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Read Cycle No. 2 (OE Controlled) [14, 15]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
VCC
SUPPLY
CURRENT
ICC
ISB
50%
50%
Notes:
12. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V > 50 µs.
CC(min)
CC
DR
CC(min)
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05471 Rev. *D
Page 6 of 10
[+] Feedback
CY7C199D
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [10, 16, 17]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA IO
DATA VALID
IN
Write Cycle No. 2 (WE Controlled) [10, 16, 17]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
OE
t
SD
t
HD
NOTE 18
DATAIN VALID
DATA IO
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW) [11, 17]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
NOTE 18
DATAIN VALID
DATA IO
t
t
LZWE
HZWE
Notes:
16. Data IO is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During this period the IOs are in the output state and input signals should not be applied.
Document #: 38-05471 Rev. *D
Page 7 of 10
[+] Feedback
CY7C199D
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Deselect/Power-down
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
Data Out
Data In
High Z
Read
)
L
L
X
Write
)
L
H
H
Deselect, Output disabled
)
Ordering Information
Speed
Package
Diagram
Operating
(ns)
Ordering Code
CY7C199D-10VXI
CY7C199D-10ZXI
Package Type
Range
10
51-85031 28-pin (300-Mil) Molded SOJ (Pb-Free)
51-85071 28-pin TSOP Type I (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
3. DIMENSIONS IN INCHES
MAX.
DETAIL
A
PIN 1 ID
EXTERNAL LEAD DESIGN
14
1
0.291
0.300
0.330
0.350
0.026
0.032
0.013
0.019
15
28
0.014
0.020
OPTION 1
OPTION 2
0.697
0.713
SEATING PLANE
0.120
0.140
0.007
0.013
0.004
A
0.262
0.272
0.050
TYP.
0.025 MIN.
51-85031-*C
Document #: 38-05471 Rev. *D
Page 8 of 10
[+] Feedback
CY7C199D
Package Diagrams (continued)
Figure 2. 28-pin Thin Small Outline Package Type 1 (8x13.4 mm), 51-85071
51-85071-*G
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05471 Rev. *D
Page 9 of 10
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C199D
Document History Page
Document Title: CY7C199D, 256K (32K x 8) Static RAM
Document Number: 38-05471
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Advance Information data sheet for C9 IPP
201560
233728
See ECN
See ECN
SWI
RKF
*A
DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in Ordering Information
*B
262950
See ECN
RKF
Removed 28-LCC Pinout and Package Diagrams
Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics table
Shaded Ordering Information
*C
*D
307594
820660
See ECN
See ECN
RKF
VKN
Reduced Speed bins to -10, -12 and -15 ns
Converted from Preliminary to Final
Removed 12 ns and 15 ns speed bin
Removed Commercial Operating range
Removed “L” part
Removed 28-pin PDIP and 28-pin SOIC package
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2
Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin
Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins
Updated Thermal Resistance table
Updated Ordering Information Table
Document #: 38-05471 Rev. *D
Page 10 of 10
[+] Feedback
相关型号：
©2020 ICPDF网 联系我们和版权申明