CY7C1470BV33-200BZCT [CYPRESS]
ZBT SRAM, 2MX36, 3ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, , FBGA-165;型号: | CY7C1470BV33-200BZCT |
厂家: | CYPRESS |
描述: | ZBT SRAM, 2MX36, 3ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, , FBGA-165 时钟 静态存储器 内存集成电路 |
文件: | 总34页 (文件大小:845K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2
M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■ Pin-compatible and functionally equivalent to ZBT™
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are 3.3 V, 2 M × 36/4 M × 18/1 M × 72 Synchronous pipelined
burst SRAMs with No Bus Latency™ (NoBL logic,
respectively. They are designed to support unlimited true
back-to-back read or write operations with no wait states. The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are
equipped with the advanced (NoBL) logic required to enable
consecutive read or write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent read or write
transitions. The CY7C1470BV33, CY7C1472BV33, and
CY7C1474BV33 are pin compatible and functionally equivalent
to ZBT devices.
■ Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■ Internally self timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ Single 3.3 V power supply
■ 3.3 V/2.5 V I/O power supply
■ Fast clock-to-output time
❐ 3.0 ns (for 250 MHz device)
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
■ Clock Enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ CY7C1470BV33,
CY7C1472BV33
available
in
Write operations are controlled by the Byte Write Selects
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV33
available in Pb-free and non-Pb-free 209-ball FBGA package
(BWa–BWd
for
CY7C1470BV33,
BWa–BWb
for
CY7C1472BV33, and BWa–BWh for CY7C1474BV33) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self timed write circuitry.
■ IEEE 1149.1 JTAG Boundary Scan compatible
■ Burst capability – linear or interleaved burst order
■ “ZZ” Sleep Mode option and Stop Clock option
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum Access Time
250 MHz
3.0
200 MHz
3.0
167 MHz Unit
3.4
450
120
ns
Maximum Operating Current
500
500
mA
mA
Maximum CMOS Standby Current
120
120
Cypress Semiconductor Corporation
Document Number: 001-15031 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 20, 2014
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Logic Block Diagram – CY7C1470BV33
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
U
T
O
U
T
S
E
D
A
T
P
U
T
N
S
P
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
F
E
R
S
S
T
E
E
R
I
DQ s
WRITE
DRIVERS
BW
a
DQ P
DQ P
DQ P
DQ P
a
b
c
A
M
P
BW
BW
BW
b
c
S
T
E
R
S
d
d
S
WE
E
E
N
G
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1472BV33
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
U
T
O
U
T
P
U
T
S
E
P
U
T
D
A
T
ADV/LD
N
S
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
F
E
R
S
DQ s
DQ P
DQ P
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
b
S
T
E
R
S
b
S
N
G
WE
E
E
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
CE1
CE2
CE3
READ LOGIC
Sleep
Control
ZZ
Document Number: 001-15031 Rev. *M
Page 2 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Logic Block Diagram – CY7C1474BV33
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
WRITE ADDRESS
REGISTER 2
1
O
U
T
O
U
T
P
U
T
S
E
P
U
T
D
A
T
ADV/LD
N
S
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
BW
BW
BW
BW
BW
a
R
E
G
I
MEMORY
ARRAY
E
B
U
F
F
E
R
S
DQ s
WRITE
DRIVERS
b
S
T
E
E
R
I
A
M
P
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
a
b
c
c
d
e
S
T
E
R
S
S
d
e
f
BW
f
N
G
BW
g
E
E
BW
h
g
h
WE
INPUT
REGISTER
INPUT
REGISTER 0
E
E
1
OE
CE1
CE2
CE3
READ LOGIC
Sleep
Control
ZZ
Document Number: 001-15031 Rev. *M
Page 3 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................8
Functional Overview ........................................................9
Single Read Accesses ................................................9
Burst Read Accesses ..................................................9
Single Write Accesses .................................................9
Burst Write Accesses ................................................10
Sleep Mode ...............................................................10
Interleaved Burst Address Table ...............................10
Linear Burst Address Table .......................................10
ZZ Mode Electrical Characteristics ............................10
Truth Table ......................................................................11
Partial Write Cycle Description .....................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................13
Disabling the JTAG Feature ......................................13
Test Access Port (TAP) .............................................13
PERFORMING A TAP RESET ..................................13
TAP REGISTERS ......................................................13
TAP Instruction Set ...................................................13
TAP Controller State Diagram .......................................15
TAP Controller Block Diagram ......................................16
TAP Timing ......................................................................17
TAP AC Switching Characteristics ...............................18
3.3 V TAP AC Test Conditions .......................................19
3.3 V TAP AC Output Load Equivalent .........................19
2.5 V TAP AC Test Conditions .......................................19
2.5 V TAP AC Output Load Equivalent .........................19
TAP DC Electrical Characteristics and
Identification Register Definitions ................................20
Scan Register Sizes .......................................................20
Identification Codes .......................................................20
Boundary Scan Exit Order .............................................21
Boundary Scan Exit Order .............................................21
Boundary Scan Exit Order .............................................22
Maximum Ratings ...........................................................23
Operating Range .............................................................23
Neutron Soft Error Immunity .........................................23
Electrical Characteristics ...............................................23
Capacitance ....................................................................25
Thermal Resistance ........................................................25
AC Test Loads and Waveforms .....................................25
Switching Characteristics ..............................................26
Switching Waveforms ....................................................27
Ordering Information ......................................................29
Ordering Code Definitions .........................................29
Package Diagrams ..........................................................30
Acronyms ........................................................................32
Document Conventions .................................................32
Units of Measure .......................................................32
Document History Page .................................................33
Sales, Solutions, and Legal Information ......................34
Worldwide Sales and Design Support .......................34
Products ....................................................................34
PSoC® Solutions ......................................................34
Cypress Developer Community .................................34
Technical Support .....................................................34
Operating Conditions .....................................................19
Document Number: 001-15031 Rev. *M
Page 4 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
V
V
V
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
V
SS
SS
SS
DQc
DQc
NC
NC
DQb
NC
DQb
DQb
DQb
DQb
DQPa
DQa
DQa
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
V
DQa
DQa
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
V
SS
SS
V
V
DD
NC
DD
NC
CY7C1470BV33
(2 M × 36)
CY7C1472BV33
(4 M × 18)
NC
NC
V
V
DD
DD
V
V
SS
SS
ZZ
ZZ
DQa
DQa
DQd
DQb
DQb
DQa
DQa
V
DQd
V
V
DDQ
DDQ
V
DDQ
DDQ
V
V
SS
V
SS
V
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQa
DQa
DQb
DQb
DQPb
NC
DQa
DQa
NC
NC
V
SS
V
V
V
SS
SS
SS
V
V
DDQ
V
DDQ
V
DDQ
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
NC
NC
NC
NC
NC
NC
Document Number: 001-15031 Rev. *M
Page 5 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Pin Configurations (continued)
Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm) pinout
CY7C1470BV33 (2 M × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
NC/576M
A
B
C
D
CE3
CLK
ADV/LD
OE
CE
BW
BW
BW
b
CEN
WE
1
c
NC/1G
A
CE2
A
A
NC
DQ
NC
BW
d
a
DQP
NC
DQ
V
V
V
V
V
V
V
V
V
V
V
V
V
DQP
DQ
c
DDQ
DDQ
SS
SS
SS
SS
SS
SS
DDQ
DDQ
b
DQ
V
V
V
V
V
V
V
c
c
DD
DD
SS
SS
DD
b
b
DQ
DQ
DQ
DQ
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
E
F
c
c
c
c
DDQ
DDQ
DDQ
SS
SS
SS
DD
DDQ
DDQ
DDQ
b
b
b
b
DQ
V
V
V
c
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
DD
b
b
DQ
V
V
V
G
H
J
c
SS
SS
DD
NC
NC
DQ
NC
V
V
V
NC
NC
DQ
ZZ
SS
SS
DD
DQ
V
V
V
V
V
DQ
a
d
d
DDQ
DDQ
DDQ
DDQ
SS
SS
DD
DDQ
DDQ
DDQ
DDQ
a
DQ
DQ
DQ
DQ
V
V
V
V
V
V
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
K
L
d
d
d
d
DD
DD
DD
SS
SS
SS
SS
SS
DD
a
a
a
a
a
a
DQ
V
V
V
d
SS
SS
DD
DQ
V
V
V
V
V
M
N
P
d
SS
SS
DD
DQP
NC
A
V
NC
NC
A1
NC
V
NC
A
DQP
a
d
DDQ
SS
SS
DDQ
NC/144M
MODE
A
TDI
TDO
A
NC/288M
A
A
A
A
A
A
A
TMS
A0
TCK
A
A
R
CY7C1472BV33 (4 M × 18)
1
NC/576M
NC/1G
NC
2
A
3
4
5
NC
6
7
8
9
A
10
A
11
A
A
B
C
D
CE1
CE2
BWb
NC
CE3
CLK
VSS
VSS
CEN
ADV/LD
A
A
A
NC
BWa
VSS
VSS
WE
VSS
VSS
OE
VSS
VDD
NC
DQb
VDDQ
VDDQ
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
K
L
NC
NC
DQb
DQPb
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
NC
NC
M
N
P
NC/144M
TDI
TDO
NC/288M
A
MODE
A
A
TMS
A0
TCK
A
A
A
A
R
Document Number: 001-15031 Rev. *M
Page 6 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Pin Configurations (continued)
Figure 3. 209-ball FBGA (14 × 22 × 1.76 mm) pinout
CY7C1474BV33 (1 M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQg
DQg
DQg
DQg
A
CE2
A
ADV/LD
WE
A
A
CE3
A
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
B
BWSc
BWSg
NC
BWSb
BWSf
DQg
DQg
DQg
DQg
BWSh
VSS
BWSd NC/576M CE1
NC
NC
BWSe
NC
BWSa
VSS
C
D
NC/1G
OE
NC
DQb
DQPb
DQf
E
F
DQPg
DQc
DQPc
DQc
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
NC
VDD
VSS
VDD
DQPf
DQf
VSS
VDDQ
VSS
VSS
VDDQ
VSS
G
H
J
DQc
DQc
DQc
NC
VDDQ
VSS
DQf
DQf
DQf
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
A
DQc
DQc
NC
NC
DQf
DQf
NC
VDDQ
DQc
NC
VDDQ
VDDQ
CLK
VDDQ
VSS
VDDQ
NC
NC
DQf
NC
K
L
CEN
NC
NC
NC
DQh
DQh
DQh
VDDQ
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
DQa
DQa
DQa
M
N
P
R
T
NC
VSS
VDDQ
VSS
VDDQ
NC
DQh
DQh
DQh
VSS
VDD
VSS
DQa
DQa
DQa
VDDQ
DQh
DQh
DQPd
DQd
DQd
VDDQ
VSS
NC
ZZ
DQa
DQa
DQPa
DQe
DQe
VSS
VDDQ
VDDQ
VDD
NC
A
DQPh
DQd
DQd
DQd
DQd
VDDQ
VDD
DQPe
DQe
DQe
DQe
DQe
VSS
VSS
NC
A
MODE
A
U
V
W
A
NC/288M
NC/144M
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Document Number: 001-15031 Rev. *M
Page 7 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK.
BWa, BWb,
Input-
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd, Synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
BWe, BWf,
BWg, BWh
and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf controls DQf and DQPf,
BWg controls DQg and DQPg, BWh controls DQh and DQPh.
WE
Input-
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/Load Input Used to Advance the On-chip Address Counter or Load a New Address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD must be driven
LOW to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device.
Input-
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device.
Input-
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device.
Input-
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to control
Asynchronou the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as outputs. When deasserted
s
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
DQS
Input-
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd
are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPX
I/O-
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQX. During write
Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg is controlled
by BWg, DQPh is controlled by BWh.
MODE
TDO
TDI
Input Strap Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
Pin
LOW selects the linear burst order. MODE must not change states during operation. When left floating
MODE defaults HIGH, to an interleaved burst order.
JTAG Serial Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Output
Synchronous
JTAG Serial Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
Input
Synchronous
Document Number: 001-15031 Rev. *M
Page 8 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
TMS
Test Mode This pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Select
Synchronous
TCK
VDD
JTAG Clock Clock Input to the JTAG Circuitry.
Power Supply Power Supply Inputs to the Core of the Device.
VDDQ
I/O Power Power Supply for the I/O Circuitry.
Supply
VSS
NC
Ground
Ground for the Device. Should be connected to ground of the system.
No Connects. This pin is not connected to the die.
–
–
NC(144M,
288M,
These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G
densities.
576M, 1G)
ZZ
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
Asynchronou data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
s
internal pull-down.
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 3.0 ns (250 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW to drive out the requested
data. During the second clock, a subsequent operation (read,
write, or deselect) can be initiated. Deselecting the device is also
pipelined. Therefore, when the SRAM is deselected at clock rise
by one of the chip enable signals, its output tri-states following
the next clock rise.
Functional Overview
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are synchronous-pipelined Burst NoBL SRAMs designed
specifically to eliminate wait states during read or write
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCO) is 3.0 ns (250 MHz device).
Burst Read Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the section Single Read
Accesses. The sequence of the burst counter is determined by
the MODE input signal. A LOW input on MODE selects a linear
burst mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and wraps
around when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enables inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). BW[x] can be used to conduct Byte Write
operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the signal WE is asserted
LOW. The address presented to the address inputs is loaded into
the Address Register. The write signals are latched into the
Control Logic block.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the input signal WE is
deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
Address Register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for
Document Number: 001-15031 Rev. *M
Page 9 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV33). In addition, the address for the subsequent
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
Accesses on page 9. When ADV/LD is driven HIGH on the
subsequent clock rise, the Chip Enables (CE1, CE2, and CE3)
and WE inputs are ignored and the burst counter is incremented.
The correct BW (BWa,b,c,d for CY7C1470BV33, BWa,b for
CY7C1472BV33, and BWa,b,c,d,e,f,g,h for CY7C1474BV33)
inputs must be driven in each cycle of the burst write to write the
correct bytes of data.
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for
CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV33) (or a subset for byte write operations, see
Partial Write Cycle Description on page 12 for details) inputs is
latched into the device and the write is complete.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1470BV33, BWa,b for CY7C1472BV33, and
BWa,b,c,d,e,f,g,h
for
CY7C1474BV33)
signals.
The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
provides Byte Write capability that is described in Partial Write
Cycle Description on page 12. Asserting the Write Enable input
(WE) with the selected BW input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self timed write mechanism
has been provided to simplify the write operations. Byte Write
capability has been included to greatly simplify read, modify, or
write sequences, which can be reduced to simple Byte Write
operations.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
Because the CY7C1470BV33, CY7C1472BV33, and
CY7C1474BV33 are common I/O devices, data must not be
driven into the device while the outputs are active. The OE can
be deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV33, DQa,b/DQPa,b for
CY7C1472BV33, and DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for
CY7C1474BV33) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1470BV33, DQa,b/DQPa,b for CY7C1472BV33, and
DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474BV33) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
Burst Write Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in the section Single Write
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
120
2tCYC
–
Unit
mA
ns
ZZ VDD 0.2 V
–
tZZS
ZZVDD 0.2 V
ZZ 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 001-15031 Rev. *M
Page 10 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Truth Table
The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect Cycle
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L–H
L–H
Tri-State
Tri-State
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
None
External
Next
L–H Data Out (Q)
L–H Data Out (Q)
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L–H
L–H
Tri-State
Tri-State
X
L
H
L
External
Next
L–H Data In (D)
L–H Data In (D)
X
L
H
L
X
L
L
None
H
H
X
X
L–H
L–H
L–H
X
Tri-State
Tri-State
-
Next
X
X
X
H
X
X
X
X
X
Current
None
Tri-State
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Partial Write Cycle Description on page 12 for details.
2. Write is defined by WE and BW
. See Partial Write Cycle Description on page 12 for details.
[a:d]
3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQ and DQP
= tri-state when OE is
s
[a:d]
inactive or when the device is deselected, and DQ = data when OE is active.
s
Document Number: 001-15031 Rev. *M
Page 11 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Partial Write Cycle Description
The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows. [8, 9, 10, 11]
Function (CY7C1470BV33)
WE
H
L
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
H
H
H
H
L
BWb
X
H
H
L
BWa
X
H
L
Read
Write – No bytes written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
L
L
H
L
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
L
H
H
L
H
L
L
L
Write Bytes c, b
L
L
H
L
Write Bytes c, b, a
L
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes d, b
L
L
H
L
Write Bytes d, b, a
L
L
L
Write Bytes d, c
L
L
H
H
L
H
L
Write Bytes d, c, a
L
L
L
Write Bytes d, c, b
L
L
L
H
L
Write All Bytes
L
L
L
L
Function (CY7C1472BV33)
WE
H
L
BWb
BWa
x
Read
x
H
H
L
Write – No Bytes Written
Write Byte a – (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
H
L
L
L
H
L
L
L
Function (CY7C1474BV33)
WE
H
BWx
Read
x
H
L
Write – No Bytes Written
Write Byte X(DQx and DQPx)
Write All Bytes
L
L
L
All BW = L
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Partial Write Cycle Description on page 12 for details.
9. Write is defined by WE and BW
. See Partial Write Cycle Description on page 12 for details.
[a:d]
10. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
11. Table lists only a partial listing of the Byte Write combinations. Any combination of BW
is valid. Appropriate Write is based on which Byte Write is active.
[a:d]
Document Number: 001-15031 Rev. *M
Page 12 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
During power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
incorporates a serial boundary scan test access port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
TAP Registers
Registers are connected between the TDI and TDO balls and
scans data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Three bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. During power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
must be left unconnected. During power up, the device comes
up in a reset state, which does not interfere with the operation of
the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Mode Select (TMS)
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32 bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 20.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register.
TAP Instruction Set
Overview
Performing a TAP Reset
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 20. Three of these instructions are listed as
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
Document Number: 001-15031 Rev. *M
Page 13 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
RESERVED and must not be used. The other five instructions
are described in this section in detail.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
EXTEST
EXTEST is a mandatory 1149.1 instruction which is executed
whenever the instruction register is loaded with all 0s. EXTEST
is not implemented in this SRAM TAP controller, and therefore
this device is not compliant to 1149.1. The TAP controller does
recognize an all-0 instruction.
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High Z state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
IDCODE
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
The IDCODE instruction loads a vendor-specific, 32 bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
BYPASS
The IDCODE instruction is loaded into the instruction register
during power up or whenever the TAP controller is in a test logic
reset state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High Z
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-15031 Rev. *M
Page 14 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 001-15031 Rev. *M
Page 15 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29 .
Identification Register
TDI
TDO
.
.
2
1
0
x
.
.
.
.
. 2 1
0
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
Document Number: 001-15031 Rev. *M
Page 16 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
TAP Timing
Figure 4. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 001-15031 Rev. *M
Page 17 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [12, 13]
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes
12. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
13. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-15031 Rev. *M
Page 18 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [14]
Description
Test Conditions
IOH = –4.0 mA,VDDQ = 3.3 V
IOH = –1.0 mA,VDDQ = 2.5 V
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH Voltage
–
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
IOH = –100 µA
VDDQ = 3.3 V
–
V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
–
0.4
V
IOL = 8.0 mA
IOL = 1.0 mA
IOL = 100 µA
V
–
0.4
V
–
0.2
V
–
0.2
V
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.8
V
V
VIL
V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Note
14. All voltages refer to V (GND).
SS
Document Number: 001-15031 Rev. *M
Page 19 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Identification Register Definitions
CY7C1470BV33 CY7C1472BV33 CY7C1474BV33
Instruction Field
Description
(2 M × 36)
(4 M × 18)
(1 M × 72)
Revision Number (31:29)
000
000
000
Describes the version number
Device Depth (28:24) [15]
01011
01011
01011
Reserved for internal use
Architecture/Memory Type(23:18)
001000
001000
001000
Defines memory type and
architecture
Bus Width/Density(17:12)
100100
010100
110100
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
00000110100 Enables unique identification of
SRAM vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 18)
Bit Size (× 72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
71
–
32
52
–
32
–
Boundary Scan Order – 165-ball FBGA
Boundary Scan Order – 209-ball FBGA
110
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to High Z state. This instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation. This instruction does not implement 1149.1 preload function and
is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
Note
15. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-15031 Rev. *M
Page 20 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Boundary Scan Exit Order
(2 M × 36)
Bit #
1
165-ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-ball ID
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
165-ball ID
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
K10
J10
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A9
3
E1
R4
4
D2
P6
5
E2
R6
6
F1
R8
7
G1
F2
P3
8
P4
9
G2
J1
P8
10
11
12
13
14
15
16
17
18
19
20
P9
K1
P10
R9
L1
J2
R10
R11
N11
M11
L11
M10
L10
K11
M1
N1
B9
K2
A10
B10
A8
L2
M2
R1
B8
R2
A7
Boundary Scan Exit Order
(4 M × 18)
Bit #
1
165-ball ID
D2
Bit #
14
15
16
17
18
19
20
21
22
23
24
25
26
165-ball ID
R4
Bit #
27
28
29
30
31
32
33
34
35
36
37
38
39
165-ball ID
L10
Bit #
40
41
42
43
44
45
46
47
48
49
50
51
52
165-ball ID
B10
A8
2
E2
P6
K10
J10
3
F2
R6
B8
4
G2
R8
H11
G11
F11
A7
5
J1
P3
B7
6
K1
P4
B6
7
L1
P8
E11
A6
8
M1
N1
P9
D11
C11
A11
B5
9
P10
R9
A4
10
11
12
13
R1
B3
R2
R10
R11
M10
A9
A3
R3
B9
A2
P2
A10
B2
Document Number: 001-15031 Rev. *M
Page 21 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Boundary Scan Exit Order
(1 M × 72)
Bit #
1
209-ball ID
A1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-ball ID
T1
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-ball ID
U10
T11
Bit #
85
209-ball ID
B11
B10
A11
A10
A7
2
A2
T2
86
3
B1
U1
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
87
4
B2
U2
88
5
C1
C2
D1
D2
E1
V1
89
6
V2
90
A5
7
W1
W2
T6
91
A9
8
92
U8
9
93
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E2
V3
94
D6
F1
V4
95
K6
F2
U4
96
B6
G1
G2
H1
H2
J1
W5
V6
L10
97
K3
P6
98
A8
W6
V5
J11
99
B4
J10
100
101
102
103
104
105
106
107
108
109
110
B3
U5
H11
H10
G11
G10
F11
C3
J2
U6
C4
L1
W7
V7
C8
L2
C9
M1
M2
N1
N2
P1
U7
B9
V8
F10
E10
E11
D11
D10
C11
C10
B8
V9
A4
W11
W10
V11
V10
U11
C6
B7
P2
A3
R2
R1
Document Number: 001-15031 Rev. *M
Page 22 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Ambient
Temperature
Range
VDD
VDDQ
Storage Temperature ............................... –65 °C to +150 °C
Commercial 0 °C to +70 °C
Industrial –40 °C to +85 °C
3.3 V– 5% / 2.5 V – 5% to
+10%
VDD
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC to Outputs in Tri-State .................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................–0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
LSBU
LMBU
SEL
LogicalSingle
Bit Upsets
25 °C
25 °C
85 °C
361 394
FIT/
Mb
Static Discharge Voltage
(MIL-STD-883, Method 3015) ..................................> 2001V
Logical Multi
Bit Upsets
0
0
0.01 FIT/
Mb
Latch Up Current ...................................................> 200 mA
Single Event
Latch up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
VDD
3.6
VDDQ
For 3.3 V I/O
For 2.5 V I/O
VDD
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [16]
Input LOW voltage [16]
For 3.3 V I/O, IOH =4.0 mA
For 2.5 V I/O, IOH=1.0 mA
For 3.3 V I/O, IOL=8.0 mA
For 2.5 V I/O, IOL=1.0 mA
For 3.3 V I/O
–
V
2.0
–
0.4
V
–
V
–
0.4
V
2.0
VDD + 0.3
VDD + 0.3
0.8
V
For 2.5 V I/O
1.7
V
For 3.3 V I/O
–0.3
–0.3
–5
V
For 2.5 V I/O
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
5
A
Input current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
A
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output leakage current
GND VI VDDQ, output disabled
–5
Notes
16. Overshoot: V
< V + 1.5 V (pulse width less than t
/2). Undershoot: V
> –2 V (pulse width less than t
/2).
CYC
IH(AC)
DD
CYC
IL(AC)
17. T
: assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
< V
.
power up
DD(min)
IH
DD
DDQ
DD
Document Number: 001-15031 Rev. *M
Page 23 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [16, 17]
Description
Test Conditions
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Min
Max
Unit
[18]
IDD
VDD Operating Supply
4.0-nscycle,
250 MHz
–
500
mA
5.0-nscycle,
200 MHz
–
–
–
–
–
–
500
450
245
245
245
120
mA
mA
mA
mA
mA
mA
6.0-nscycle,
167 MHz
ISB1
Automatic CE power-down
current – TTL Inputs
Max VDD, Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
4.0-nscycle,
250 MHz
5.0-nscycle,
200 MHz
6.0-nscycle,
167 MHz
ISB2
Automatic CE power-down
current – CMOS Inputs
Max VDD, Device Deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f = 0
All speed
ISB3
Automatic CE power-down
current – CMOS Inputs
Max VDD, Device Deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, 250 MHz
f = fMAX = 1/tCYC
4.0-nscycle,
–
–
–
–
245
245
245
135
mA
mA
mA
mA
5.0-nscycle,
200 MHz
6.0-nscycle,
167 MHz
ISB4
Automatic CE Power Down
Current – TTL Inputs
Max VDD, Device Deselected,
VIN VIH or VIN VIL, f = 0
All speed
grades
Note
18. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15031 Rev. *M
Page 24 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Capacitance
100-pin TQFP 165-ball FBGA 209-ball FBGA
Parameter [19]
Description
Test Conditions
Unit
Max
Max
Max
CADDRESS
CDATA
CCTRL
CCLK
Address input capacitance
Data input capacitance
Control input capacitance
Clock input capacitance
I/O capacitance
TA = 25 C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
V
DD = 3.3 V, VDDQ = 2.5 V
CIO
Thermal Resistance
100-pin TQFP 165-ballFBGA 209-ballFBGA
Parameter [19]
Description
Test Conditions
Unit
Package
Package
Package
JA
Thermal resistance
(junction to ambient)
Test
conditions
follow
24.63
16.3
15.2
C/W
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
JC
Thermal resistance
(junction to case)
2.28
2.1
1.7
C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50
0
10%
R = 50
L
GND
5 pF
R = 351
1 ns
1 ns
V = 1.5 V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R = 1538
1 ns
1 ns
V = 1.25 V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
19. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-15031 Rev. *M
Page 25 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Switching Characteristics
Over the Operating Range
-250
-200
-167
Unit
Parameter [20, 21]
Description
Min
Max
Min
Max
Min
Max
[22]
tPower
VCC(typical) to the first access read
or write
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
Maximum operating frequency
Clock HIGH
4.0
–
–
250
–
5.0
–
–
200
–
6.0
–
–
167
–
ns
MHz
ns
FMAX
tCH
2.0
2.0
2.0
2.0
2.2
2.2
tCL
Clock LOW
–
–
–
ns
Output Times
tCO
Data output valid after CLK rise
OE LOW to output valid
–
–
3.0
3.0
–
–
–
3.0
3.0
–
–
–
3.4
3.4
–
ns
ns
ns
ns
ns
ns
ns
tOEV
tDOH
Data output hold after CLK rise
Clock to high Z [23, 24, 25]
Clock to low Z [23, 24, 25]
OE HIGH to output high Z [23, 24, 25]
OE LOW to output low Z [23, 24, 25]
1.3
–
1.3
–
1.5
–
tCHZ
3.0
–
3.0
–
3.4
–
tCLZ
1.3
–
1.3
–
1.5
–
tEOHZ
tEOLZ
Setup Times
tAS
3.0
–
3.0
–
3.4
–
0
0
0
Address setup before CLK rise
Data input setup before CLK rise
CEN setup before CLK rise
WE, BWx setup before CLK rise
ADV/LD setup before CLK rise
Chip select setup
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
tALH
tCEH
Notes
20. Timing reference is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
21. Test conditions shown in (a) of Figure 5 on page 25 unless otherwise noted.
22. This part has an internal voltage regulator; t is the time power is supplied above V minimum initially, before a read or write operation can be initiated.
power
DD
23. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of Figure 5 on page 25. Transition is measured ±200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
24. At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data bus.
EOHZ
EOLZ
CHZ
CLZ
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High
Z before Low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 001-15031 Rev. *M
Page 26 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Switching Waveforms
Figure 6. Read/Write Timing [26, 27, 28]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS
CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
x
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW or CE is HIGH.
1
2
3
1
2
3
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
Document Number: 001-15031 Rev. *M
Page 27 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Switching Waveforms (continued)
Figure 7. NOP, STALL and DESELECT Cycles [29, 30, 31]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Figure 8. ZZ Mode Timing [32, 33]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW or CE is HIGH.
1
2
3
1
2
3
31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle.
32. Device must be deselected when entering ZZ mode. See Truth Table on page 11 for all possible signal conditions to deselect the device.
33. IOs are in High Z when exiting ZZ sleep mode.
Document Number: 001-15031 Rev. *M
Page 28 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
167 CY7C1470BV33-167AXC
CY7C1470BV33-167BZXC
CY7C1470BV33-167AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
lndustrial
CY7C1472BV33-167AXI
CY7C1470BV33-167BZI
51-85165 165-ball FBGA (15 × 17 × 1.4 mm)
200 CY7C1470BV33-200AXC
CY7C1472BV33-200BZXC
CY7C1474BV33-200BGXC
CY7C1470BV33-200AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
51-85167 209-ball FBGA (14 × 22 × 1.76 mm) Pb-free
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
51-85165 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Commercial
lndustrial
CY7C1470BV33-200BZXI
250 CY7C1470BV33-250BZXC
Commercial
Ordering Code Definitions
CY
7
C
14XX
B
V33 - XXX XX X X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BZ or BG
A = 100-pin TQFP
BZ = 165-ball FBGA
BG = 209-ball FBGA
Speed Grade: XXX = 167 MHz or 200 MHz or 250 MHz
V33 = 3.3 V
Die Revision
Part Identifier: 14XX = 1470 or 1472 or 1474
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-15031 Rev. *M
Page 29 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Figure 10. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Outline, 51-85165
51-85165 *D
Document Number: 001-15031 Rev. *M
Page 30 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Package Diagrams (continued)
Figure 11. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Package Outline, 51-85167
51-85167 *C
Document Number: 001-15031 Rev. *M
Page 31 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Input/Output
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
nanosecond
ohm
FBGA
I/O
MHz
µA
µs
JTAG
LSB
Joint Test Action Group
Least Significant Bit
Logical Multi Bit Upsets
Logical Single Bit Upsets
Most Significant Bit
Output Enable
mA
mm
ms
ns
LMBU
LSBU
MSB
OE
SEL
Single Event Latch-up
Static Random Access Memory
Test Access Port
%
percent
SRAM
TAP
pF
V
picofarad
volt
TCK
TDI
Test Clock
W
watt
Test Data-In
TDO
TMS
TQFP
TTL
Test Data-Out
Test Mode Select
Thin Quad Flat Pack
Transistor-Transistor Logic
Write Enable
WE
Document Number: 001-15031 Rev. *M
Page 32 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Document History Page
Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with
NoBL™ Architecture
Document Number: 001-15031
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
1032642
VKN /
KKVTMP
See ECN New data sheet.
*A
1897447
VKN /
AESA
See ECN Updated Electrical Characteristics (Added Note 18 and referred the same note
in IDD parameter).
*B
*C
2082487
2159486
VKN
See ECN Changed status from Preliminary to Final.
See ECN Minor Change (Post to external web).
VKN /
PYRS
*D
2755901
VKN
08/25/09
Included Neutron Soft Error Immunity.
Updated Ordering Information (By including parts that are available, and
modified the disclaimer for the Ordering information).
Updated Package Diagrams.
*E
2903057
VKN
04/01/10
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
*F
2953769
3052861
YHB
NJY
06/16/10
10/08/10
Updated Ordering Information (Updated part numbers).
*G
Updated Ordering Information (Removed the following pruned part numbers
from ordering information namely CY7C1474BV33-167BGC,
CY7C1470BV33-200BZC, CY7C1472BV33-200BZC) and added Ordering
Code Definitions.
*H
3253430
NJY
05/10/2011 Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
*I
*J
*K
3425159
3593603
4010294
VIDB
11/11/2011 Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
PRIT /
GOPA
04/26/2012 Updated Ordering Information (Updated part numbers).
PRIT
05/24/2013 Updated Package Diagrams:
spec 51-85167 – Changed revision from *B to *C.
Completing Sunset Review.
*L
4396527
4575272
PRIT
06/02/2014 Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated in new template.
Completing Sunset Review.
*M
PRIT
11/20/2014 Added related documentation hyperlink in page 1.
Document Number: 001-15031 Rev. *M
Page 33 of 34
CY7C1470BV33
CY7C1472BV33
CY7C1474BV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Community | Forums | Blogs | Video | Training
Technical Support
Memory
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-15031 Rev. *M
Revised November 20, 2014
Page 34 of 34
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
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