CY7C128A-15SC [CYPRESS]
2K x 8 Static RAM; 2K ×8静态RAM
| 型号： | CY7C128A-15SC |
| 厂家： | 
CYPRESS |
| 描述： | 2K x 8 Static RAM |
| 文件： | 总11页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
28A
CY7C128A
2K x 8 Static RAM
provided by an active LOW Chip Enable (CE), and active LOW
Output Enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW.
— 15 ns
Data on the eight I/O pins (I/O0 through I/O7) is written into the
memory location specified on the address pins (A0 through
A10).
• Low active power
— 660 mW (commercial)
— 688 mW (military—20 ns)
• Low standby power
Reading the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while Write Enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear on
the eight I/O pins.
— 110 mW (20 ns)
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
static discharge
The I/O pins remain in high-impedance state when Chip En-
able (CE) or Output Enable (OE) is HIGH or Write Enable (WE)
is LOW.
• VIH of 2.2V
Functional Description
The CY7C128A utilizes a die coat to insure alpha immunity.
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
Pin
Logic Block Diagram
Configurations
DIP/SOJ/SOIC
Top View
A
V
CC
1
24
23
22
7
A
A
A
A
8
A
9
2
3
4
5
6
7
8
9
6
5
4
WE
OE
21
20
19
18
17
A
A
2
3
A
10
7C128A
A
1
CE
I/O
A
0
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
0
1
2
3
4
5
6
I/O
0
16
15
14
13
INPUT BUFFER
I/O
I/O
10
11
12
I/O
I/O
5
1
4
2
A
10
GND
I/O
3
A
9
C128A–2
A
A
8
LCC
Top View
7
128 x 16 x 8
ARRAY
A
6
A
A
5
3
2 1 2423
22
4
5
6
7
8
9
A
4
A
9
WE
OE
10
4
21
20
19
18
17
16
A
3
A
2
A
A
7C128A
1
CE
WE
A
0
POWER
DOWN
CE
COLUMN
DECODER
I/O
0
I/O
I/O
7
6
10
I/O
1
I/O
11 12 13 14 15
7
OE
C128A–3
C128A–1
A
3
A
2
A
1
A
0
Selection Guide
7C128A-15
7C128A-20
7C128A-25
7C128A-35
7C128A-45
Maximum Access Time (ns)
15
120
-
20
120
125
20
25
120
125
20
35
120
125
20
45
120
125
20
Maximum Operating
Current (mA)
Commercial
Military
Maximum Standby
Current (mA)
Commercial
Military
40
-
20
20
20
20
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05028 Rev. **
Revised August 24, 2001
CY7C128A
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
Ambient
Range
Commercial
Military[1]
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
0°C to +70°C
5V ± 10%
5V ± 10%
–55°C to +125°C
DC Input Voltage............................................ –3.0V to +7.0V
Electrical Characteristics Over the Operating Range[2]
7C128A-15 7C128A-20 7C128A-25 7C128A-35,45
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
Description
Test Conditions
VCC = Min.,
IOH = –4.0 mA
VOH
Output HIGH
Voltage
2.4
2.4
2.4
2.4
V
VOL
VIH
VIL
IIX
Output LOW
Voltage
VCC = Min., IOL = 8.0 mA
0.4
0.4
0.4
0.4
VCC
0.8
V
Input HIGH
Voltage
2.2
VCC
2.2
VCC
2.2
VCC
2.2
–0.5
–10
–10
V
Input LOW
Voltage[3]
–0.5 0.8 –0.5 0.8 –0.5 0.8
–10 +10 –10 +10 –10 +10
–10 +10 –10 +10 –10 +10
V
Input Load
Current
GND < VI < VCC
+10
+10
–300
µA
µA
mA
mA
IOZ
IOS
ICC
Output Leakage GND < VI < VCC
Current
Output Disabled
Output Short
VCC = Max.,
–300
–300
–300
CircuitCurrent[4] VOUT = GND
VCC Operating
Supply Current
VCC = Max.
IOUT = 0 mA
Com’l
Mil
120
120
125
40
120
125
20
120
125
20
-
40
-
ISB1
Automatic CE
Power-Down
Current
Max. VCC
CE > VIH,
Min. Duty Cycle
= 100%
,
Com’l
Mil
mA
mA
40
40
20
ISB2
Automatic CE
Power-Down
Current
Max. VCC
,
Com’l
40
-
20
20
20
20
20
20
CE1 >VCC–0.3V,
VIN > VCC–0.3V
or VIN < 0.3V
Mil
Capacitance[5]
Parameter
CIN
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
Input Capacitance
10
pF
Output Capacitance
10
pF
COUT
Notes:
1. TA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. IL (min.) = –3.0V for pulse durations less than 30 ns.
V
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05028 Rev. **
Page 2 of 10
CY7C128A
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
≤ 5 ns
R2
255Ω
R2
255Ω
30 pF
5 pF
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
C128A–5
C128A–4
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Switching Characteristics Over the Operating Range[2, 6]
7C128A-15 7C128A-20 7C128A-25 7C128A-35 7C128A-45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
Description
READ CYCLE
tRC
Read Cycle Time
15
5
20
5
25
5
35
5
45
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[7]
CE LOW to Low Z[8]
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
15
20
25
35
45
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
15
10
20
10
25
12
35
15
45
20
3
5
0
3
5
0
3
5
0
3
5
0
3
5
0
8
8
8
8
10
10
20
12
15
20
15
15
25
tPD
15
20
WRITE CYCLE[9]
tWC
tSCE
tAW
Write Cycle Time
15
12
12
0
20
15
15
0
20
20
20
0
25
25
25
0
40
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
0
0
tPWE
tSD
12
10
0
15
10
0
15
10
0
20
15
0
20
15
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[7]
tHD
tHZWE
7
7
7
10
15
tLZWE
WE HIGH to Low Z
5
5
5
5
5
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05028 Rev. **
Page 3 of 10
CY7C128A
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C128A–6
Read Cycle No. 2[10, 12]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
C128A–7
Write Cycle No. 1 (WE Controlled)[9, ]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C128A–8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected. OE, CE = VIL.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.
Document #: 38-05028 Rev. **
Page 4 of 10
CY7C128A
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[9, 13, 14]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA VALID
IN
DATA IN
t
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C128A–9
Notes:
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.2
1.0
0.8
I
I
CC
CC
1.0
0.8
0.6
V
CC
=5.0V
0.6
0.4
60
T = 2 5°C)
A
40
V
V
IN
= 5.0V
= 5.0V
CC
0.4
0.2
0.0
20
0
I
SB
0.2
0.0
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
CC
=5.0V
1.2
1.0
T = 25°C
A
1.1
1.0
60
T = 25°C
A
V
CC
= 5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
Document #: 38-05028 Rev. **
Page 5 of 10
CY7C128A
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
CC
vs. CYCLETIME
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.4
1.3
1.2
V
= 5.0V
CC
T = 25°C
A
V
IN
= 0.5V
1.1
1.0
1.0
0.5
0.0
10.0
5.0
V
= 4.5V
CC
T = 25°C
A
0.9
0.8
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
0
10
20
30
40
SUPPLY VOLTAGE(V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
15
CY7C128A-15PC
CY7C128A-15VC
CY7C128A-15SC
CY7C128A-20PC
CY7C128A-20VC
CY7C128A-20SC
CY7C128A-20DMB
CY7C128A-20LMB
CY7C128A-25PC
CY7C128A-25VC
CY7C128A-25SC
CY7C128A-25DMB
CY7C128A-35PC
CY7C128A-35VC
CY7C128A-35SC
CY7C128A-35DMB
CY7C128A-45PC
CY7C128A-45VC
CY7C128A-45SC
CY7C128A-45DMB
CY7C128A-45LMB
P13
V13
S13
P13
V13
S13
D14
L53
P13
V13
S13
D14
P13
V13
S13
D14
P13
V13
S13
D14
L53
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
20
Commercial
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) CerDIP
Military
24-Pin Rectangular Leadless Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
25
35
45
Commercial
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) CerDIP
Military
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) CerDIP
Military
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) CerDIP
Military
24-Pin Rectangular Leadless Chip Carrier
Document #: 38-05028 Rev. **
Page 6 of 10
CY7C128A
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VOL
VIH
VIL Max.
IIX
IOZ
ICC
ISB
Switching Characteristics
Parameter
Subgroups
READ CYCLE
tRC
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tAA
tOHA
tACE
tDOE
WRITE CYCLE
tWC
tSCE
tAW
tHA
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSA
tPWE
tSD
tHD
Document #: 38-05028 Rev. **
Page 7 of 10
CY7C128A
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031
24-Pin Rectangular Leadless Chip Carrier L53
51-80066
Document #: 38-05028 Rev. **
Page 8 of 10
CY7C128A
Package Diagrams (continued)
24-Lead (300-Mil) Molded DIP P13/P13A
51-85013-A
24-Lead (300-Mil) Molded SOJ V13
51-85030-A
Document #: 38-05028 Rev. **
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C128A
Document Title: CY7C128A 2K x 8 Static RAM
Document Number: 38-05028
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106814
09/10/01
SZV
Change from Spec number: 38-00094 to 38-05028
Document #: 38-05028 Rev. **
Page 10 of 10
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