首页 |元器件品牌

CY7C128A-15VXC [CYPRESS]

2K x 8 Static RAM; 2K ×8静态RAM
CY7C128A-15VXC
型号： CY7C128A-15VXC
厂家： CYPRESS    CYPRESS
描述：

2K x 8 Static RAM
2K ×8静态RAM
文件： 总9页 (文件大小：255K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
CY7C128A  
2K x 8 Static RAM  
Features  
Functional Description  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• High speed  
The CY7C128A is a high-performance CMOS static RAM  
organized as 2048 words by 8 bits. Easy memory expansion  
is provided by an active LOW Chip Enable (CE), and active  
LOW Output Enable (OE) and tri-state drivers. The CY7C128A  
has an automatic power-down feature, reducing the power  
consumption by 83% when deselected.  
— 15 ns  
• Low active power  
Writing to the device is accomplished when the Chip Enable  
(CE) and Write Enable (WE) inputs are both LOW.  
— 660 mW (commercial)  
• Low standby power  
Data on the eight I/O pins (I/O0 through I/O7) is written into the  
memory location specified on the address pins (A0 through  
— 110 mW (20 ns)  
A10).  
• TTL-compatible inputs and outputs  
Reading the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while Write Enable (WE)  
remains HIGH. Under these conditions, the contents of the  
memory location specified on the address pins will appear on  
the eight I/O pins.  
• Capable of withstanding greater than 2001V electro-  
static discharge  
• Available in Pb-free and non Pb-free 24-pin Molded  
SOJ, non Pb-free 24-pin (300-Mil) Molded DIP  
The I/O pins remain in high-impedance state when Chip  
Enable (CE) or Output Enable (OE) is HIGH or Write Enable  
(WE) is LOW.  
The CY7C128A utilizes a die coat to insure alpha immunity.  
Pin  
Logic Block Diagram  
Configurations  
DIP/SOJ  
Top View  
A
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
22  
7
A
A
A
A
8
A
9
6
5
4
WE  
OE  
21  
20  
19  
18  
17  
A
A
2
3
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
A
10  
INPUT BUFFER  
7C128A  
A
1
CE  
I/O  
A
0
7
A
10  
I/O  
6
I/O  
0
16  
15  
14  
13  
A
9
I/O  
I/O  
10  
11  
12  
I/O  
I/O  
5
1
A
A
8
4
2
7
128 x 16 x 8  
ARRAY  
GND  
I/O  
3
A
6
A
A
5
C128A–2  
4
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
C128A–1  
A
3
A
2
A
1
A
0
Cypress Semiconductor Corporation  
Document #: 38-05028 Rev. *A  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
CY7C128A  
Selection Guide  
-15  
15  
-20  
20  
-35  
35  
-45  
45  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
120  
40  
120  
20  
120  
20  
120  
20  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage........................................... >2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-Up Current.................................................... >200 mA  
Ambient Temperature with  
Power Applied.............................................–55°C to +125°C  
Operating Range  
Supply Voltage to Ground Potential  
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V  
Ambient  
Temperature  
Range  
VCC  
DC Voltage Applied to Outputs  
in High Z State ............................................... –0.5V to +7.0V  
Commercial  
0°C to +70°C  
5V ± 10%  
DC Input Voltage............................................ –3.0V to +7.0V  
Electrical Characteristics Over the Operating Range[2]  
-15  
-20  
-35, -45  
Parameter  
VOH  
Description  
Test Conditions  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Output HIGH  
Voltage  
VCC = Min., IOH = –4.0 mA  
2.4  
2.4  
2.4  
V
VOL  
VIH  
VIL  
IIX  
Output LOW  
Voltage  
VCC = Min., IOL = 8.0 mA  
0.4  
VCC  
0.8  
0.4  
VCC  
0.8  
0.4  
VCC  
0.8  
V
V
Input HIGH  
Voltage  
2.2  
–0.5  
–10  
–10  
2.2  
–0.5  
–10  
–10  
2.2  
–0.5  
–10  
–10  
Input LOW  
Voltage[3]  
V
Input Leakage  
Current  
GND < VI < VCC  
+10  
+10  
120  
40  
+10  
+10  
120  
40  
+10  
+10  
120  
20  
µA  
µA  
mA  
mA  
IOZ  
ICC  
ISB1  
Output Leakage GND < VI < VCC  
Current  
Output Disabled  
VCC Operating  
Supply Current  
VCC = Max. IOUT = 0 mA  
Automatic CE  
Power-Down  
Current  
Max. VCC, CE > VIH,  
Min. Duty Cycle = 100%  
ISB2  
Automatic CE  
Power-Down  
Current  
Max. VCC, CE1 >VCC–0.3V,  
40  
20  
20  
mA  
VIN > VCC–0.3V  
or VIN < 0.3V  
Notes:  
1. T is the “instant on” case temperature.  
A
2. See the last page of this specification for Group A subgroup testing information.  
3. V (min.) = –3.0V for pulse durations less than 30 ns.  
IL  
Document #: 38-05028 Rev. *A  
Page 2 of 9  
CY7C128A  
Capacitance[4]  
Parameter  
CIN  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
Max.  
10  
Unit  
pF  
COUT  
10  
pF  
AC Test Loads and Waveforms  
ALL INPUT PULSES  
90%  
R1 481Ω  
R1 481Ω  
5V  
5V  
OUTPUT  
3.0V  
GND  
90%  
10%  
OUTPUT  
10%  
≤ 5 ns  
R2  
255Ω  
R2  
255Ω  
30 pF  
5 pF  
≤ 5 ns  
C128A–5  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THÉVENIN EQUIVALENT  
C128A–4  
(a)  
(b)  
167Ω  
OUTPUT  
1.73V  
Switching Characteristics Over the Operating Range[2, 5]  
-15  
-20  
-35  
-45  
Parameter  
READ CYCLE  
tRC  
Description  
Min.  
15  
5
Max.  
Min.  
20  
Max.  
Min.  
35  
Max.  
Min.  
45  
5
Max.  
Unit  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z[6]  
CE LOW to Low Z[7]  
15  
20  
35  
45  
tOHA  
5
5
tACE  
15  
10  
20  
10  
35  
15  
45  
20  
tDOE  
tLZOE  
tHZOE  
tLZCE  
3
5
0
3
5
0
3
5
0
3
5
0
8
8
8
8
12  
15  
20  
15  
15  
25  
tHZCE  
tPU  
CE HIGH to High Z[6, 7]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
tPD  
15  
20  
WRITE CYCLE[8]  
tWC  
tSCE  
tAW  
Write Cycle Time  
15  
12  
12  
0
20  
15  
15  
0
25  
25  
25  
0
40  
30  
30  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
tHA  
tSA  
0
0
0
0
tPWE  
tSD  
12  
10  
0
15  
10  
0
20  
15  
0
20  
15  
0
Data Set-Up to Write End  
Data Hold from Write End  
WE LOW to High Z[6]  
tHD  
tHZWE  
7
7
10  
15  
tLZWE  
WE HIGH to Low Z  
5
5
5
5
Notes:  
4. Tested initially and after any design or process changes that may affect these parameters  
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
I
/I and 30-pF load capacitance.  
OL OH  
6. t  
, t  
, and t  
are specified with C = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.  
HZOE HZCE  
HZWE L  
7. At any given temperature and voltage condition, t  
is less than t  
for any given device.  
HZCE  
LZCE  
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a  
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
Document #: 38-05028 Rev. *A  
Page 3 of 9  
CY7C128A  
Switching Waveforms  
Read Cycle No. 1[9, 10]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
C128A–6  
Read Cycle No. 2[9, 11]  
t
RC  
CE  
t
ACE  
OE  
t
t
HZOE  
t
DOE  
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
t
PU  
V
ICC  
CC  
SUPPLY  
CURRENT  
50%  
50%  
ISB  
C128A–7  
Write Cycle No. 1 (WE Controlled)[8]  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA VALID  
DATA IN  
IN  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA I/O  
DATA UNDEFINED  
C128A–8  
Notes:  
9. WE is HIGH for read cycle.  
10. Device is continuously selected. OE, CE = V .  
IL  
11. Address valid prior to or coincident with CE transition LOW.  
Document #: 38-05028 Rev. *A  
Page 4 of 9  
CY7C128A  
Switching Waveforms (continued)  
Write Cycle No. 2 (CE Controlled)[8, 12, 13]  
t
WC  
ADDRESS  
t
SA  
t
SCE  
CE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA VALID  
IN  
DATA IN  
t
HZWE  
HIGH IMPEDANCE  
DATA I/O  
DATA UNDEFINED  
C128A–9  
Notes:  
12. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.  
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05028 Rev. *A  
Page 5 of 9  
CY7C128A  
Typical DC and AC Characteristics  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
OUTPUT SOURCE CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
120  
100  
80  
1.4  
1.2  
1.2  
1.0  
0.8  
I
I
CC  
CC  
1.0  
0.8  
0.6  
V
=5.0V  
CC  
0.6  
0.4  
60  
T = 2 5°C)  
A
40  
V
V
IN  
= 5.0V  
= 5.0V  
CC  
0.4  
0.2  
0.0  
20  
0
I
0.2  
0.0  
SB  
I
SB  
–55  
25  
125  
0.0  
1.0  
2.0  
3.0  
4.0  
4.0  
40  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE(°C)  
OUTPUT VOLTAGE(V)  
SUPPLY VOLTAGE(V)  
NORMALIZED ACCESS TIME  
vs. AMBIENT TEMPERATURE  
OUTPUT SINK CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED ACCESS TIME  
vs. SUPPLY VOLTAGE  
140  
120  
1.6  
1.4  
1.4  
1.3  
1.2  
100  
80  
V
A
=5.0V  
T = 25°C  
CC  
1.2  
1.0  
1.1  
1.0  
60  
T = 25°C  
A
V
= 5.0V  
CC  
40  
0.8  
20  
0
0.9  
0.8  
0.6  
–55  
0.0  
1.0  
2.0  
3.0  
25  
125  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE(°C)  
OUTPUT VOLTAGE(V)  
SUPPLY VOLTAGE(V)  
TYPICAL POWER-ON CURRENT  
vs. SUPPLY VOLTAGE  
TYPICAL ACCESS TIME CHANGE  
vs. OUTPUT LOADING  
NORMALIZED I  
CC  
vs. CYCLETIME  
3.0  
2.5  
2.0  
1.5  
30.0  
25.0  
20.0  
15.0  
1.4  
1.3  
1.2  
V
= 5.0V  
CC  
T = 25°C  
A
V
IN  
= 0.5V  
1.1  
1.0  
1.0  
0.5  
0.0  
10.0  
5.0  
V
= 4.5V  
CC  
T = 25°C  
A
0.9  
0.8  
0.0  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
0
200 400  
600 800 1000  
0
10  
20  
30  
SUPPLY VOLTAGE(V)  
CAPACITANCE (pF)  
CYCLE FREQUENCY (MHz)  
Document #: 38-05028 Rev. *A  
Page 6 of 9  
CY7C128A  
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
(ns)  
Ordering Code  
Package Type  
24-pin (300-Mil) Molded DIP  
15  
CY7C128A-15PC  
CY7C128A-15VC  
CY7C128A-15VXC  
CY7C128A-20VXC  
CY7C128A-35VC  
CY7C128A-45PC  
51-85013  
51-85030  
Commercial  
24-pin Molded SOJ  
24-pin Molded SOJ  
20  
35  
45  
51-85030  
51-85030  
51-85013  
24-pin Molded SOJ (Pb-free)  
24-pin Molded SOJ  
Commercial  
Commercial  
Commercial  
24-pin (300-Mil) Molded DIP  
Please contact local sales representative regarding availability of these parts  
Package Diagrams  
24-pin (300-Mil) Molded DIP (51-85013)  
51-85013-*B  
Document #: 38-05028 Rev. *A  
Page 7 of 9  
CY7C128A  
Package Diagrams (continued)  
24-pin (300-mil) SOJ (51-85030)  
PIN 1 ID  
12  
1
MIN.  
DIMENSIONS IN INCHES[MM]  
MAX.  
REFERENCE JEDEC MO-088  
PACKAGE WEIGHT 0.75gms  
0.291[7.39]  
0.300[7.62]  
0.330[8.38]  
0.350[8.89]  
PART #  
V24.3  
STANDARD PKG.  
LEAD FREE PKG.  
13  
24  
VZ24.3  
0.597[15.16]  
0.613[15.57]  
SEATING PLANE  
0.120[3.05]  
0.140[3.55]  
0.007[0.17]  
0.013[0.33]  
0.004[0.10]  
0.262[6.65]  
0.272[6.91]  
0.050[1.27]  
TYP.  
0.025[0.63] MIN.  
0.013[0.33]  
0.019[0.48]  
51-85030-*B  
Document #: 38-05028 Rev. *A  
Page 8 of 9  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
CY7C128A  
Document History Page  
Document Title: CY7C128A 2K x 8 Static RAM  
Document Number: 38-05028  
Issue  
Orig. of  
Change  
REV.  
**  
ECN NO. Date  
Description of Change  
106814  
493543  
09/10/01  
SZV  
Change from Spec number: 38-00094 to 38-05028  
*A  
See ECN NXR  
Removed 25 ns speed bin  
Removed Military Operating Range  
Changed the description of IIX from Input Load Current to  
Input Leakage Current in DC Electrical Characteristics table  
Removed IOS parameter from DC Electrical Characteristics table  
Updated ordering Information Table  
Document #: 38-05028 Rev. *A  
Page 9 of 9  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明