CY7C128A-20DMB [CYPRESS]
2K x 8 Static RAM; 2K ×8静态RAM
| 型号： | CY7C128A-20DMB |
| 厂家： | 
CYPRESS |
| 描述： | 2K x 8 Static RAM |
| 文件： | 总9页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C128A
CY7C128A
2K x 8 Static RAM
Features
Functional Description
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), and active LOW
output enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
— 15 ns
• Low active power
— 440 mW (commercial)
— 550 mW (military)
Writing to the device is accomplished when the chip enable
(CE) and write enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O through I/O ) is written into the
• Low standby power
— 110 mW
0
7
memory location specified on the address pins (A through
0
A
).
10
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
static discharge
Reading the device is accomplished by taking chip enable
(CE) and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory location
specified on the address pins will appear on the eight I/O pins.
• V of 2.2V
IH
The I/O pins remain in high-impedance state when chip enable
(CE) or output enable (OE) is HIGH or write enable (WE) is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Pin
Logic Block Diagram
Configurations
DIP/SOJ
Top View
A
V
CC
1
24
23
22
7
A
A
A
A
8
A
9
2
3
4
5
6
7
8
9
6
5
4
WE
OE
21
20
19
18
17
A
A
2
3
A
10
7C128A
A
1
CE
I/O
A
0
7
I/O
I/O
0
I/O
6
16
15
14
13
0
INPUT BUFFER
I/O
I/O
10
11
12
I/O
I/O
5
4
1
2
I/O
1
A
10
GND
I/O
3
A
9
I/O
2
C128A–2
A
8
LCC
Top View
A
7
I/O
3
128 x 16 x 8
ARRAY
A
6
I/O
4
A
5
A
4
3
2 1 2423
22
I/O
5
4
A
4
A
9
5
6
7
8
9
10
21
20
19
18
17
16
A
2
WE
OE
3
A
CE
WE
I/O
6
POWER
DOWN
A
A
10
7C128A
1
COLUMN
DECODER
A
0
CE
I/O
0
I/O
7
I/O
7
OE
I/O
1
I/O
6
11 12 13 14 15
A
3
A
2
A
1
A
0
C128A–3
C128A–1
Selection Guide
7C128A–15 7C128A–20 7C128A–25
7C128A–35
7C128A–45
Maximum Access Time (ns)
15
20
25
100
125
20
35
100
100
20
45
Commercial
Military
120
100
Maximum Operating
Current (mA)
125
100
20
Commercial
Military
40/40
40/20
40/20
Maximum Standby
Current (mA)
40
20
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 1988 – Revised December 1992
CY7C128A
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)........................................... –0.5V to +7.0V
Ambient
Temperature
Range
V
CC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
5V ± 10%
[1]
Military
–55°C to +125°C
DC Input Voltage............................................ –3.0V to +7.0V
[2]
Electrical Characteristics Over the Operating Range
7C128A–15 7C128A–20 7C128A–25 7C128A–35,45
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
Description
Test Conditions
V
Output HIGH
Voltage
V
= Min.,
–4.0 mA
2.4
2.4
2.4
2.4
V
OH
OL
IH
CC
I
OH =
V
V
V
Output LOW
Voltage
V
= Min., I = 8.0 mA
0.4
0.4
0.4
0.4
V
CC
OL
Input HIGH
Voltage
2.2
V
2.2
V
2.2
V
2.2
–0.5
–10
–10
V
V
CC
CC
CC
CC
Input LOW
–0.5 0.8 –0.5 0.8 –0.5 0.8
–10 +10 –10 +10 –10 +10
–10 +10 –10 +10 –10 +10
0.8
V
IL
[3]
Voltage
I
I
I
I
Input Load
Current
GND < V < V
+10
+10
µA
µA
mA
mA
IX
I
CC
CC
Output Leakage GND < V < V
Current
OZ
OS
CC
I
Output Disabled
Output Short
CircuitCurrent
V
V
= Max.,
–300
120
–300
–300
–300
CC
[4]
= GND
OUT
V
Operating
V
= Max.
= 0 mA
Com’l
Mil
100
125
40
100
125
20
100
100
20
CC
CC
Supply Current
I
OUT
I
I
Automatic CE
Power-Down
Current
Max. V
CE > V
Min. Duty Cycle
= 100%
,
CC
Com’l
Mil
40
40
mA
mA
SB1
SB2
IH,
40
40
20
Automatic CE
Power-Down
Current
Max. V
CE >V –0.3V,
,
Com’l
Mil
20
20
20
20
20
20
CC
1
CC
V
> V –0.3V
IN
CC
or V < 0.3V
IN
[ ]
Capacitance 5
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
Input Capacitance
10
pF
C
C
A
IN
V
= 5.0V
CC
Output Capacitance
10
pF
OUT
Notes:
1. A is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. IL (min.) = –3.0V for pulse durations less than 30 ns.
T
V
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C128A
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
≤ 5 ns
R2
255 Ω
R2
255 Ω
30 pF
5 pF
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
C128A–5
C128A–4
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
[2,6]
Switching Characteristics Over the Operating Range
7C128A–15 7C128A–20 7C128A–25 7C128A–35 7C128A–45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
Description
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
15
5
20
5
25
5
35
5
45
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
15
20
25
35
45
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
15
10
20
10
25
12
35
15
45
20
3
5
0
3
5
0
3
5
0
3
5
0
3
5
0
[7]
OE HIGH to High Z
8
8
8
8
10
10
20
12
15
20
15
15
25
[8]
CE LOW to Low Z
[7,8]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
15
20
PD
[9]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
0
20
15
15
0
20
20
20
0
25
25
25
0
40
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
0
0
SA
12
10
0
15
10
0
15
10
0
20
15
0
20
15
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[7]
WE LOW to High Z
7
7
7
10
15
HZWE
LZWE
WE HIGH to Low Z
5
5
5
5
5
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CY7C128A
Switching Waveforms
[10,11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C128A–6
[10,12]
Read Cycle No. 2
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
CC
SUPPLY
CURRENT
50%
50%
ISB
C128A–7
[9,13]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA VALID
DATA IN
DATA I/O
IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA UNDEFINED
C128A–8
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected. OE, CE = VIL.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.
4
CY7C128A
Switching Waveforms (continued)
[9,13,14]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA VALID
IN
DATA IN
t
HZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
C128A–9
Notes:
14. If CEgoes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.2
1.0
0.8
I
I
CC
CC
1.0
0.8
0.6
V
CC
=5.0V
0.6
0.4
60
T =25°C)
A
40
V
V
IN
=5.0V
=5.0V
CC
0.4
0.2
0.0
20
0
I
SB
0.2
0.0
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
V
CC
=5.0V
1.2
1.0
T =25°C
A
1.1
1.0
60
T =25°C
A
V
CC
=5.0V
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE(°C)
OUTPUT VOLTAGE(V)
SUPPLY VOLTAGE(V)
5
CY7C128A
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
CC
vs. CYCLETIME
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.4
1.3
1.2
V
=5.0V
CC
T =25°C
A
V
IN
=0.5V
1.1
1.0
1.0
0.5
0.0
10.0
5.0
V
=4.5V
CC
T =25°C
A
0.9
0.8
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
0
10
20
30
40
SUPPLY VOLTAGE(V)
CAPACITANCE(pF)
CYCLE FREQUENCY(MHz)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C128A–15PC
CY7C128A–15VC
CY7C128A–20PC
CY7C128A–20VC
CY7C128A–20DMB
CY7C128A–20LMB
CY7C128A–25PC
CY7C128A–25VC
CY7C128A–25DMB
CY7C128A–25LMB
CY7C128A–35PC
CY7C128A–35VC
CY7C128A–35DMB
CY7C128A–35LMB
CY7C128A–45DMB
CY7C128A–45LMB
Package Type
15
P13
V13
P13
V13
D14
L53
P13
V13
D14
L53
P13
V13
D14
L53
D14
L53
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
Commercial
Military
20
25
35
45
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
24-Lead (300-Mil) CerDIP
24-Pin Rectangular Leadless Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
Military
24-Lead (300-Mil) CerDIP
24-Pin Rectangular Leadless Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
Commercial
Military
24-Lead (300-Mil) CerDIP
24-Pin Rectangular Leadless Chip Carrier
24-Lead (300-Mil) CerDIP
Military
24-Pin Rectangular Leadless Chip Carrier
6
CY7C128A
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
1, 2, 3
V
V
V
OH
OL
IH
1, 2, 3
1, 2, 3
V Max.
1, 2, 3
IL
I
I
I
I
1, 2, 3
IX
1, 2, 3
OZ
CC
SB
1, 2, 3
1, 2, 3
Switching Characteristics
Parameter
Subgroups
READ CYCLE
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
RC
AA
OHA
ACE
DOE
WRITE CYCLE
t
t
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WC
SCE
AW
HA
SA
PWE
SD
HD
Document #: 38–00094–B
7
CY7C128A
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL–STD–1835 D–9 Config.A
24-Pin Rectangular Leadless Chip Carrier L53
24-Lead (300-Mil) Molded DIP P13/P13A
8
CY7C128A
Package Diagrams (continued)
24-Lead Molded SOJ V13
© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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