CY7C1069AV33-8ZI [CYPRESS]
2M x 8 Static RAM; 2M ×8静态RAM
| 型号： | CY7C1069AV33-8ZI |
| 厂家： | 
CYPRESS |
| 描述： | 2M x 8 Static RAM |
| 文件： | 总9页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1069AV33
2M x 8 Static RAM
device is accomplished by enabling the chip (by taking CE1
LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.
Features
• High speed
Reading from the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
— tAA = 8, 10, 12 ns
• Low active power
— 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
The input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE1 LOW, CE2 HIGH, and WE
LOW).
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
Functional Description
The CY7C1069AV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
Logic Block Diagram
Pin Configuration
TSOP II
Top View
1
54 NC
NC
CC
INPUT BUFFER
V
53
52
51
50
V
NC
I/O
2
3
4
5
6
SS
NC
A
0
A
1
I/O
6
5
V
V
CC
SS
A
2
I/O
49 I/O
7
4
A
4
3
A
4
48
47
A
5
I/O –I/O
7
2M x 8
ARRAY
0
7
A
A
A
8
3
6
A
5
6
4096 x 4096
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A
2
A
7
9
A
A
10
11
12
13
A
8
1
A
7
A
A
0
9
A
8
A
NC
NC
9
CE
OE
1
V
V
CC
14
15
16
17
18
19
20
21
22
23
SS
WE
DNU
WE
CE
COLUMN
DECODER
CE
A
20
2
2
OE
CE
A
19
A
10
1
A
18
A
11
A
12
A
13
A
17
A
16
A
15
A
14
I/O
V
I/O
V
0
3
CC
SS
24
25
26
27
I/O
I/O
2
1
30 NC
29
NC
V
V
SS
CC
28
NC
NC
Selection Guide
–8
–10
10
–12
12
Unit
ns
Maximum Access Time
8
Maximum Operating Current
Commercial
Industrial
300
300
50
275
275
50
260
260
50
mA
Maximum CMOS Standby Current
Commercial/Industrial
mA
Cypress Semiconductor Corporation
Document #: 38-05255 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 10, 2003
CY7C1069AV33
Pin Configurations
48-ball FBGA
(Top View)
1
2
4
3
5
6
A
A
A
2
NC
NC
OE
NC
0
1
CE2
NC
A
B
C
A
A
4
CE1
3
A
A
6
I/O NC
0
NC I/O
4
5
I/O
A
I/O
A17
A
D
E
F
5
7
VSS
VCC
VSS
1
A
V
CC
I/O
I/O
6
18
16
2
I/O
7
A
A
15
NC
NC
I/O
3
14
A
NC
A
G
H
NC
WE
DNU
13
12
A
A
19
A
A
A
A
8
10
9
11
20
Document #: 38-05255 Rev. *D
Page 2 of 9
CY7C1069AV33
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–8
–10
–12
Parameter
Description
Test Conditions
VCC = Min.,
OH = –4.0 mA
VCC = Min.,
OL = 8.0 mA
Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage
2.4
2.4
2.4
V
V
V
I
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
0.4
0.4
0.4
I
2.0
VCC
2.0
VCC
2.0
VCC
+ 0.3
+ 0.3
+ 0.3
VIL
IIX
Input LOW Voltage[1]
Input Load Current
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage Current GND < VOUT < VCC, Output
Disabled
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX Commercial
300
300
70
275
275
70
260
260
70
mA
mA
mA
= 1/tRC
Industrial
ISB1
Automatic CE
CE2 < VIL,
Power-down Current
—TTL Inputs
Max. VCC, SCE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
CE2 < 0.3V
Max. VCC
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Commercial/
Industrial
50
50
50
mA
,
Capacitance[2]
Parameter
Package
Z54
Description
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
6
Unit
CIN
Input Capacitance
pF
pF
pF
pF
BA48
Z54
8
COUT
I/O Capacitance
8
BA48
10
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05255 Rev. *D
Page 3 of 9
CY7C1069AV33
AC Test Loads and Waveforms[3]
50Ω
R1 317 Ω
= 1.5V
OUTPUT
VTH
3.3V
Z = 50Ω
OUTPUT
30 pF*
3.3V
0
R2
351Ω
5 pF*
(a)
*Capacitive Load consists of all
components of the test environment
All input pulses
90%
10%
*Including
jig and
scope
90%
(b)
10%
GND
Rise time > 1V/ns
Fall time:
> 1V/ns
(c)
[4]
AC Switching Characteristics Over the Operating Range
–8
–10
–12
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
tpower
tRC
VCC(typical) to the First Access[5]
Read Cycle Time
1
8
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
tAA
Address to Data Valid
10
10
12
tOHA
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[6]
OE HIGH to High-Z[6]
CE1 LOW/CE2 HIGH to Low-Z[6]
CE1 HIGH/CE2 LOW to High-Z[6]
CE1 LOW/CE2 HIGH to Power-up[7]
CE1 HIGH/CE2 LOW to Power-down[7]
3
3
3
tACE
8
5
10
5
12
6
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
1
3
0
1
3
0
1
3
0
5
5
8
5
5
6
6
tPD
10
12
Write Cycle[8, 9]
tWC
Write Cycle Time
8
6
6
0
0
6
5
0
3
10
7
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
7
8
tHA
0
0
tSA
0
0
tPWE
tSD
7
8
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[6]
5.5
0
6
tHD
0
tLZWE
3
3
tHZWE
WE LOW to High-Z[6]
5
5
6
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD , normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation
is started.
6. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV
from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE LOW / CE HIGH, and WE LOW. CE and WE must be LOW along with CE HIGH to initiate
1
2
1
2
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05255 Rev. *D
Page 4 of 9
CY7C1069AV33
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
[10, 11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2(OEControlled) [11, 12]
ADDRESS
t
RC
CE
1
CE
2
t
ASCE
OE
t
HZOE
t
DOE
t
t
HZSCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZSCE
t
PD
t
I
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
10. Device is continuously selected. CE1 = VIL, CE2 = VIH
11. WE is HIGH for Read cycle.
.
Document #: 38-05255 Rev. *D
Page 5 of 9
CY7C1069AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 Controlled)[13, 14, 15]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
t
t
SD
HD
DATAI/O
Write Cycle No.2 (WE Controlled, OE LOW)[13, 14, 15]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE1
H
CE2
X
OE
X
WE
X
I/O0–I/O7
High-Z
Mode
Power
Power-down
Power-down
Read All Bits
Write All Bits
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
L
X
X
High-Z
Data Out
Data In
High-Z
)
L
H
L
H
)
L
H
X
L
)
L
H
H
H
Selected, Outputs Disabled
)
Notes:
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high-impedance if OE = VIH
.
14. If CE1 goes HIGH / CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state.
15. CE above is defined as a combination of CE1 and CE2. It is active low.
Document #: 38-05255 Rev. *D
Page 6 of 9
CY7C1069AV33
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code[16]
Package Type
54-pin TSOP II
8
CY7C1069AV33-8ZC
CY7C1069AV33-8ZI
Z54
BA48
Z54
Commercial
Industrial
CY7C1069AV33-8BAC
CY7C1069AV33-8BAI
CY7C1069AV33-10ZC
CY7C1069AV33-10ZI
CY7C1069AV33-10BAC
CY7C1069AV33-10BAI
CY7C1069AV33-12ZC
CY7C1069AV33-12ZI
CY7C1069AV33-12BAC
CY7C1069AV33-12BAI
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
Commercial
Industrial
10
12
Commercial
Industrial
BA48
Z54
Commercial
Industrial
Commercial
Industrial
BA48
Commercial
Industrial
Package Diagrams
54-lead Thin Small Outline Package, Type II Z54-II
51-85160-**
Note:
16. Contact a Cypress Representative for availability of the 48-ball Mini BGA (BA48) package.
Document #: 38-05255 Rev. *D
Page 7 of 9
CY7C1069AV33
Package Diagrams (continued)
48-ball (8 mm x 20 mm x 1.2 mm) FBGA BA48G
51-85162-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05255 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1069AV33
Document History Page
Document Title: CY7C1069AV33 2M x 8 Static RAM
Document Number: 38-05255
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
113724
117060
117990
Description of Change
03/27/02
07/31/02
08/30/02
NSL
DFP
DFP
New Data Sheet
Removed 15-ns bin
Added 8-ns bin
*A
*B
Changing ICC for 8, 10, 12 bins
tpower changed from 1 µs to 1 ms
Load Cap Comment changed (for Tx line load)
tSD changed to 5.5 ns for the 10-ns bin
Changed some 8-ns bin #’s (tHZ, tDOE, tDBE
)
Removed hz < lz comments
*C
*D
120385
124441
11/13/02
2/25/03
DFP
Final Data Sheet
Added note 4 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd
Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin
TSOP to 6/8 pf
MEG
Changed ISB1 from 100 mA to 70 mA
Shaded the 48fBGA product offering information
Document #: 38-05255 Rev. *D
Page 9 of 9
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