CY7C1069BV33-10ZC [CYPRESS]
16-Mbit (2M x 8) Static RAM; 16兆位（ 2M ×8 ）静态RAM
| 型号： | CY7C1069BV33-10ZC |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (2M x 8) Static RAM |
| 文件： | 总7页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1069BV33
16-Mbit (2M x 8) Static RAM
Features
Functional Description
• High speed
The CY7C1069BV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
LOW) and Write Enable (WE) inputs LOW.
— tAA = 10 ns
• Low active power
— 990 mW (max.)
Reading from the device is accomplished by enabling the chip
(CE LOW) as well as forcing the Output Enable (OE) LOW
while forcing the Write Enable (WE) HIGH. See the truth table
at the back of this data sheet for a complete description of
Read and Write modes.
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
The input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW and WE LOW).
• Available in Pb-free and non Pb-free 54-pin TSOP II
package
The CY7C1069BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Pin Configurations[1, 2]
Logic Block Diagram
54-pin TSOP II (Top View)
INPUT BUFFER
NC
1
54
53
NC
CC
V
V
2
3
4
5
6
SS
A
A
A
0
1
2
NC
52
51
50
NC
I/O
I/O
6
5
V
A
V
SS
3
4
CC
I/O –I/O
2M x 8
0
7
A
I/O
49 I/O
7
4
ARRAY
A
A
5
6
48
47
A
5
A
6
A
A
3
7
4
8
A
A
A
7
8
9
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A
A
7
9
2
A
10
11
12
13
A
8
1
A
A
9
0
NC
NC
CE
CC
WE
OE
COLUMN
DECODER
V
V
SS
14
15
16
17
18
19
20
21
22
23
OE
CE
DNU/V
WE
CC
SS
A
20
DNU/V
A
19
A
10
A
18
A
11
A
17
A
13
12
A
A
15
16
A
A
14
I/O
V
I/O
V
0
3
CC
SS
24
25
26
27
I/O
I/O
2
1
NC
NC
V
V
CC
SS
NC
NC
Notes:
1. DNU/V Pin (#16) has to be left floating or connected to V and DNU/V Pin (#40) has to be left floating or connected to V to ensure proper application.
CC
CC
SS
SS
2. NC - No Connect Pins are not connected to the die.
Cypress Semiconductor Corporation
Document #: 38-05694 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
CY7C1069BV33
Selection Guide
–10
10
–12
12
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
275
275
50
260
260
50
mA
Industrial
Maximum CMOS Standby Current
Commercial/Industrial
mA
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
3.3V ± 0.3V
–40°C to +85°C
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–10
–12
Parameter
VOH
VOL
VIH
Description
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min.
Max.
Unit
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[3]
2.4
2.4
V
V
0.4
VCC + 0.3
0.8
0.4
2.0
–0.3
–1
2.0
–0.3
–1
VCC + 0.3
0.8
V
VIL
V
IIX
Input Leakage Current GND < VI < VCC
Output Leakage Current GND < VOUT < VCC, Output Disabled
+1
+1
µA
µA
mA
mA
mA
IOZ
–1
+1
–1
+1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Comm’l
Ind’l
275
260
260
70
275
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
70
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC
,
Comm’l/
Ind’l
50
50
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Capacitance[4]
Parameter
CIN
Description
Input Capacitance
I/O Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
pF
pF
COUT
Thermal Resistance[4]
Parameter
Description
Test Conditions
TSOP-II
49.95
3.34
Unit
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
°C/W
°C/W
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
Thermal Resistance (Junction to Case)
Notes:
3. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL
IH
CC
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05694 Rev. *B
Page 2 of 7
CY7C1069BV33
AC Test Loads and Waveforms[5]
50Ω
R1 317 Ω
= 1.5V
3.3V
OUTPUT
VTH
OUTPUT
Z = 50Ω
0
30 pF*
*Capacitive Load consists of all
R2
351Ω
5 pF*
components of the test environment
*Including
jig and
scope
(a)
All input pulses
3.3V
GND
(b)
90%
10%
90%
10%
Fall time: > 1V/ns
Rise time > 1V/ns
(c)
[6]
AC Switching Characteristics Over the Operating Range
–10
–12
Parameter
Read Cycle
Description
Min.
Max.
Min.
Max.
Unit
tpower
VCC(typical) to the First Access[7]
Read Cycle Time
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
10
12
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8]
CE LOW to Low-Z[8]
CE to High-Z[8]
10
12
tOHA
3
3
tACE
10
5
12
6
tDOE
tLZOE
1
3
0
1
3
0
tHZOE
5
5
6
6
tLZCE
tHZCE
tPU
CE to Power-up[9]
CE to Power-down[9]
tPD
10
12
Write Cycle[10, 11]
tWC
tSCE
tAW
tHA
Write Cycle Time
10
7
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
7
8
0
0
tSA
0
0
tPWE
tSD
7
8
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[8]
WE LOW to High-Z[8]
5.5
0
6
tHD
0
tLZWE
3
3
tHZWE
5
6
Notes:
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). As soon as 1ms (T
) after reaching the
DD
power
minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
DD
DD
CCDR
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
7. t
8. t
/I and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
OL OH
gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
POWER
, t
, t
and t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV
HZOE HZSCE HZWE
LZOE LZCE
LZWE
from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05694 Rev. *B
Page 3 of 7
CY7C1069BV33
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ASCE
OE
t
HZOE
t
DOE
t
t
HZSCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZSCE
t
PD
t
ICC
PU
50%
50%
ISB
Notes:
12. Device is continuously selected. CE = V .
IL
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05694 Rev. *B
Page 4 of 7
CY7C1069BV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
t
t
SD
HD
DATAI/O
Write Cycle No. 2 (WE Controlled, OE LOW)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE
H
L
OE
X
WE
X
I/O0–I/O7
High-Z
Mode
Power
Standby (ISB
Power-down
Read
)
L
H
Data Out
Data In
High-Z
Active (ICC
)
)
)
L
X
L
Write
Active (ICC
Active (ICC
L
H
H
Selected, Outputs Disabled
Notes:
15. Data I/O is high-impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05694 Rev. *B
Page 5 of 7
CY7C1069BV33
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
Package Type
54-pin TSOP II
10
CY7C1069BV33-10ZC
CY7C1069BV33-10ZXC
CY7C1069BV33-10ZI
CY7C1069BV33-10ZXI
CY7C1069BV33-12ZC
CY7C1069BV33-12ZXC
CY7C1069BV33-12ZI
CY7C1069BV33-12ZXI
51-85160
Commercial
54-pin TSOP II (Pb-free)
54-pin TSOP II
Industrial
54-pin TSOP II (Pb-free)
54-pin TSOP II
12
Commercial
Industrial
54-pin TSOP II (Pb-free)
54-pin TSOP II
54-pin TSOP II (Pb-free)
Package Diagram
54-pin TSOP II (51-85160)
51-85160-**
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05694 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1069BV33
Document History Page
Document Title: CY7C1069BV33 16-Mbit (2M x 8) Static RAM
Document Number: 38-05694
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
283950
314014
492137
See ECN
See ECN
See ECN
RKF
RKF
NXR
New data sheet
*A
Final data sheet
*B
Removed 8 ns speed bin
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information Table
Document #: 38-05694 Rev. *B
Page 7 of 7
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