CY7C1069AV33_06 [CYPRESS]
2M x 8 Static RAM; 2M ×8静态RAM
| 型号： | CY7C1069AV33_06 |
| 厂家： | 
CYPRESS |
| 描述： | 2M x 8 Static RAM |
| 文件： | 总9页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1069AV33
2M x 8 Static RAM
Features
Functional Description
• High speed
The CY7C1069AV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE1
LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.
— tAA = 10, 12 ns
• Low active power
— 990 mW (max.)
Reading from the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) as well as forcing the Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
The input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE1 LOW, CE2 HIGH, and WE
LOW).
• Available in Pb-free and non Pb-free 54-pin TSOP II ,
non Pb-free 60-ball fine-pitch ball grid array (FBGA)
package
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
60-ball fine-pitch ball grid array (FBGA) package.
Pin Configurations[1, 2]
Logic Block Diagram
TSOP II
Top View
NC
1
2
3
4
5
6
54
53
NC
CC
V
V
SS
NC
52
51
50
NC
I/O
I/O
6
5
V
V
SS
CC
I/O
49 I/O
7
4
A
A
3
48
47
A
5
A
6
7
4
8
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A
A
7
9
2
A
10
11
12
I/O
A
8
0
1
A
Data in Drivers
A
9
0
NC
A
NC
CE1 13
CC
14
WE
CE2
0
I/O
1
A
OE
1
V
V
A
SS
2
A
DNU
15
3
I/O
2
A
A
20
16
4
A
A
19
A
10
17
18
19
20
21
22
23
24
25
26
27
5
A
I/O
A
18
A
11
6
3
2048K x 8
ARRAY
A
A
A
7
8
A
17
A
13
12
A
A
15
16
I/O
9
4
A
A
14
A
10
A
I/O
I/O
11
12
0
3
A
I/O
V
V
5
CC
SS
I/O
I/O
2
1
NC
NC
I/O
6
V
V
POWER
DOWN
CC
SS
COLUMN
DECODER
CE
CE
1
2
NC
NC
I/O
WE
OE
7
Cypress Semiconductor Corporation
Document #: 38-05255 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C1069AV33
Selection Guide
–10
10
–12
12
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
275
50
260
50
mA
mA
Pin Configurations[1, 2](continued)
60-ball FBGA
(Top View)
3
5
1
2
4
6
NC
NC
NC
NC
NC
NC
A
A
A
NC
NC
I/O
CE2
NC
OE
NC
NC
I/O
A
B
0
3
5
2
1
A
A
A
A
CE1
4
C
A
NC I/O
6
4
0
I/O
A
D
E
5
7
V
V
V
CC
1
17
SS
A
18
A
16
V
I/O
I/O
6
CC
SS
2
I/O
A
A
15
NC
NC
I/O
7
F
G
H
14
3
A
NC
A
13
NC
DNU
WE
12
A
10
A
20
A
19
A
9
A
11
A
8
NC
NC
NC
NC
NC
NC
Notes:
1. NC pins are not connected on the die.
2. DNU pins have to be left floating or tied to VSS to ensure proper application.
Document #: 38-05255 Rev. *F
Page 2 of 9
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CY7C1069AV33
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–10
–12
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[3]
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min.
Max.
0.4
Unit
V
2.4
2.4
0.4
V
VIH
2.0
–0.3
–1
VCC + 0.3
0.8
2.0
–0.3
–1
VCC + 0.3
0.8
V
VIL
V
IIX
Input Leakage Current GND < VI < VCC
Output Leakage Current GND < VOUT < VCC, Output Disabled
+1
+1
µA
µA
mA
IOZ
–1
+1
–1
+1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
275
260
ISB1
Automatic CE
Power-down Current
—TTL Inputs
CE2 < VIL,
Max. VCC, CE1 > VIH
VIN > VIH or VIN < VIL, f = fMAX
70
50
70
50
mA
mA
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
CE2 < 0.3V, Max. VCC
CE1> VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
,
Capacitance[4]
Parameter
CIN
Description
Input Capacitance
I/O Capacitance
Test Conditions
TSOP II
FBGA
Unit
pF
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
8
COUT
10
pF
AC Test Loads and Waveforms[5]
50Ω
R1 317 Ω
= 1.5V
VTH
OUTPUT
3.3V
Z = 50Ω
30 pF*
0
*Capacitive Load consists of all
components of the test environment
OUTPUT
R2
351Ω
5 pF*
(a)
*Including
jig and
scope
(b)
All input pulses
3.3V
GND
90%
10%
90%
10%
Fall time: > 1V/ns
Rise time > 1V/ns
(c)
Notes:
3. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). As soon as 1ms (T
) after reaching the
power
DD
minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
CCDR
DD
DD
Document #: 38-05255 Rev. *F
Page 3 of 9
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CY7C1069AV33
[7]
AC Switching Characteristics Over the Operating Range
–10
–12
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[8]
Read Cycle Time
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
tAA
Address to Data Valid
10
12
tOHA
tACE
Data Hold from Address Change
3
3
LOW/CE2 HIGH to Data Valid
10
5
12
6
CE1
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Data Valid
LOW to Low-Z[9]
1
3
0
1
3
0
OE
9
OE HIGH to High-Z[ ]
5
5
6
6
LOW/CE2 HIGH to Low-Z[9]
CE1 HIGH/CE2 LOW to High-Z[
CE1 LOW/CE2 HIGH to Power-up[10]
CE1
9]
tPD
HIGH/CE2 LOW to Power-down[10]
10
12
CE1
Write Cycle[10, 11]
tWC
Write Cycle Time
10
7
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
7
8
tHA
0
0
tSA
0
0
tPWE
tSD
7
8
Data Set-up to Write End
5.5
0
6
tHD
Data Hold from Write End
HIGH to Low-Z[9]
WE
WE LOW to High-Z[ ]
0
tLZWE
tHZWE
3
3
9
5
6
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Notes:
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). As soon as 1ms (T
) after reaching the
power
DD
minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
DD
DD
CCDR
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
OL OH
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
started.
time has to be provided initially before a Read/Write operation is
power
9. t
, t
, t
and t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
HZOE HZSCE HZWE
LZOE LZCE
LZWE
steady-state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal Write time of the memory is defined by the overlap of CE LOW/CE HIGH, and WE LOW. CE and WE must be LOW along with CE HIGH to initiate
1
2
1
2
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the Write.
12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05255 Rev. *F
Page 4 of 9
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CY7C1069AV33
Switching Waveforms
Read Cycle No. 1[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
CE1
t
RC
CE2
t
ASCE
OE
t
HZOE
t
DOE
t
t
HZSCE
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZSCE
t
PD
t
ICC
PU
50%
50%
ISB
Notes:
13. Device is continuously selected. CE = V , CE = V .
IH
1
IL
2
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
Document #: 38-05255 Rev. *F
Page 5 of 9
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CY7C1069AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 Controlled)[16, 17, 18]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
t
t
SD
HD
DATAI/O
Write Cycle No. 2 (WE Controlled, OE LOW)[16, 17, 18]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE2
X
I/O0–I/O7
High-Z
Mode
Power
CE1
H
OE
X
WE
X
Power-down
Power-down
Read All Bits
Write All Bits
Standby (ISB
)
)
X
L
X
X
High-Z
Standby (ISB
L
H
L
H
Data Out
Data In
High-Z
Active (ICC
)
)
)
L
H
X
L
Active (ICC
Active (ICC
L
H
H
H
Selected, Outputs Disabled
Notes:
16. Data I/O is high-impedance if OE = V
.
IH
17. If CE goes HIGH/CE LOW simultaneously with WE going HIGH, the output remains in a high–impedance state.
1
2
18. CE above is defined as a combination of CE and CE . It is active low.
1
2
Document #: 38-05255 Rev. *F
Page 6 of 9
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CY7C1069AV33
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
Package Type
54-pin TSOP II
10
CY7C1069AV33-10ZC
CY7C1069AV33-10ZXC
CY7C1069AV33-10BAC
CY7C1069AV33-10ZI
CY7C1069AV33-10ZXI
CY7C1069AV33-10BAI
CY7C1069AV33-12ZC
CY7C1069AV33-12ZXC
CY7C1069AV33-12BAC
CY7C1069AV33-12ZI
CY7C1069AV33-12ZXI
CY7C1069AV33-12BAI
51-85160
Commercial
54-pin TSOP II (Pb-free)
51-85162
51-85160
60-ball (8 mm x 20 mm x 1.2 mm) FBGA
54-pin TSOP II
Industrial
54-pin TSOP II (Pb-free)
51-85162
51-85160
60-ball (8 mm x 20 mm x 1.2 mm) FBGA
54-pin TSOP II
12
Commercial
Industrial
54-pin TSOP II (Pb-free)
51-85162
51-85160
60-ball (8 mm x 20 mm x 1.2 mm) FBGA
54-pin TSOP II
54-pin TSOP II (Pb-free)
51-85162
60-ball (8 mm x 20 mm x 1.2 mm) FBGA
Package Diagrams
54-pin TSOP II (51-85160)
51-85160-**
Document #: 38-05255 Rev. *F
Page 7 of 9
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CY7C1069AV33
Package Diagrams (continued)
60-ball FBGA (8 mm x 20 mm x 1.2 mm) (51-85162)
TOP VIEW
A1 CORNER
BOTTOM VIEW
1
2
3
(
5
6
A1 CORNER
6
5
(
3
2
1
DUMMY BALL ꢀ0.3X 812
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A
B
C
D
E
A
B
C
D
E
F
G
H
F
G
H
DIMENSIONS IN MM
PART #
STANDARD PKG.
LEAD FREE PKG.
BA60A
BK60A
A
1.475
B
4.00 0.10
A
0.75
0.75
1.00
PKG WEIGHT: 0.30 gms
3.75
6.00
B
4.00 0.10
0.15ꢀ(8X
51-85162-*D
SEATING PLANE
C
All product and company names mentioned in this document may be the trademarks of their respective holders
Document #: 38-05255 Rev. *F
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1069AV33
Document History Page
Document Title: CY7C1069AV33 2M x 8 Static RAM
Document Number: 38-05255
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
113724
117060
117990
Description of Change
03/27/02
07/31/02
08/30/02
NSL
DFP
DFP
New Data Sheet
Removed 15-ns bin
Added 8-ns bin
*A
*B
Changing ICC for 8, 10, 12 bins
t
power changed from 1 µs to 1 ms
Load Cap Comment changed (for Tx line load)
tSD changed to 5.5 ns for the 10-ns bin
Changed some 8-ns bin #'s (tHZ, tDOE, tDBE
Removed hz < lz comments
)
*C
120385
11/13/02
DFP
Final Data Sheet
Added note 4 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd
Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin
TSOP to 6/8 pf
*D
*E
124441
403984
2/25/03
MEG
NXR
Changed ISB1 from 100 mA to 70 mA
Shaded the 48fBGA product offering information
See ECN
Changed the Logic Block Diagram On page # 1
Added notes under Pin Configuration
Changed the Package diagram of 51-85162 from Rev *A to Rev *D
Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration
Updated the Ordering Information
*F
492137
See ECN
NXR
Removed 8 ns speed bin from product offering
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information
Document #: 38-05255 Rev. *F
Page 9 of 9
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