CY7C006A-20AXC [CYPRESS]
32 K/16 K Ã 8, 16 K Ã 9 Dual-Port Static RAM; 32 K / 16 K A ？ 8 ， 16 K A ？ 9双端口静态RAM
| 型号： | CY7C006A-20AXC |
| 厂家： | 
CYPRESS |
| 描述： | 32 K/16 K Ã 8, 16 K Ã 9 Dual-Port Static RAM |
| 文件： | 总22页 (文件大小：703K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C007A32 K/16 K × 8, 16 K × 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32 K/16 K × 8, 16 K × 9
Dual-Port Static RAM
32 K/16
K × 8, 16 K × 9 Dual-Port Static RAM
■ Automatic power-down
Features
■ Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 16 K × 8 organization (CY7C006A)
■ 32 K × 8 organization (CY7C007A)
■ 16 K × 9 organization (CY7C016A)
■ 32 K × 9 organization (CY7C017A)
■ 0.35-micron CMOS for optimum speed/power
■ High-speed access: 12[1]/15/20 ns
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Pin select for Master or Slave
■ Commercial temperature range
■ Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pinTQFP(CY7C006A), andin80-pinTQFP
(CY7C007A and CY7C016A)
■ Low operating power
❐ Active: ICC = 180 mA (typical)
❐ Standby: ISB3 = 0.05 mA (typical)
■ Pb-Free packages available
■ Fully asynchronous operation
Logic Block Diagram
R/WL
R/WR
CER
CEL
OEL
OER
8/9
[2]
8/9
[2]
I/O0L–I/O7/8L
I/O0R–I/O7/8R
I/O
Control
I/O
Control
14/15
14/15
Address
Decode
Address
Decode
True Dual-Ported
[4]
[4]
A0L–A13/14L
A0R–A13/14R
RAM Array
14/15
14/15
[4]
[4]
A
0L–A13/14L
A0R–A13/14R
CER
CEL
Interrupt
Semaphore
Arbitration
OEL
OER
R/WL
SEML
R/WR
SEMR
[3] BUSYR
INTR
[3]
BUSYL
INTL
Notes
M/S
1. See page 7 for Load Conditions.
2. I/O –I/O for x8 devices; I/O –I/O for x9 devices.
0
7
0
8
3. BUSY is an output in master mode and an input in slave mode.
4. A –A for 16K; A –A for 32K devices.
0
13
0
14
Cypress Semiconductor Corporation
Document Number: 38-06045 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 17, 2010
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Contents
Pin Configurations ...........................................................3
Selection Guide ................................................................4
Pin Definitions ..................................................................5
Architecture ......................................................................5
Functional Description .....................................................5
Write Operation ...........................................................5
Read Operation ...........................................................5
Interrupts .....................................................................5
Busy ............................................................................6
Master/Slave ...............................................................6
Semaphore Operation .................................................6
Maximum Ratings .............................................................7
Operating Range ...............................................................7
Electrical Characteristics .................................................7
Capacitance Table ............................................................8
AC Test Loads and Waveforms .......................................8
AC Test Loads (Applicable to –12 only) .........................8
Switching Characteristics ................................................9
Data Retention Mode ......................................................10
Timing ..............................................................................10
Switching Waveforms ....................................................11
Read Cycle No. 1 (Either Port Address Access) ....... 11
Read Cycle No. 2 (Either Port CE/OE Access) ......... 11
Read Cycle No. 3 (Either Port) .................................. 11
Write Cycle No. 1: R/W Controlled Timing ................12
Write Cycle No. 2: CE Controlled Timing ..................12
Semaphore Read After Write Timing, Either Side .....13
Timing Diagram of Semaphore Contention ...............13
Timing Diagram of Read with BUSY (M/S=HIGH) ....14
Write Timing with Busy Input (M/S=LOW) .................14
CELValid First: ...........................................................15
Left Address Valid First: ............................................15
Busy Timing Diagram No. 1 (CE Arbitration) .............15
Busy Timing Diagram No. 2 (Address Arbitration) ....15
Interrupt Timing Diagrams .........................................16
Ordering Information ......................................................18
16K x 8 Asynchronous Dual-Port SRAM ...................18
Ordering Code Definitions .........................................18
Package Diagrams ..........................................................19
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support .......................22
Products ....................................................................22
PSoC Solutions .........................................................22
Document Number: 38-06045 Rev. *F
Page 2 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations
68-pin PLCC
Top View
60
59
A
A
10
11
12
13
I/O
I/O
5L
2L
3L
4L
4L
58
57
I/O
A
A
A
3L
I/O
5L
2L
56
55
GND
1L
14
15
A
0L
I/O
6L
54
53
52
INT
I/O
7L
L
16
17
CY7C006A (16K x 8)
CY7C007A (32K x 8)
CY7C017A (32K x 9)
BUSY
V
CC
L
GND
M/S
GND
18
19
20
21
I/O
0R
51
50
I/O
1R
BUSY
R
I/O
2R
INT
R
49
48
V
CC
A
A
0R
22
23
I/O
3R
1R
47
I/O
4R
24
25
26
A
A
A
46
45
2R
3R
4R
I/O
5R
I/O6
R
44
80-pin TQFP
Top View
NC
1
2
NC
60
I/O
A
5L
2L
59
I/O
I/O
I/O
A
4L
3
4
3L
4L
5L
58
57
A
A
3L
2L
5
6
7
8
56
55
54
53
A
A
GND
I/O
1L
0L
6L
I/O
7L
INT
L
BUSY
V
L
9
10
CC
52
51
GND
M/S
NC
CY7C007A (32K x 8)
CY7C016A (16K X 9)
GND
I/O
11
12
13
14
50
49
48
47
BUSY
0R
R
I/O
1R
INT
R
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
15
16
46
45
I/O
3R
I/O
4R
17
44
I/O
5R
A
18
19
20
4R
43
42
41
I/O
6R
NC
NC
NC
Notes
5. This pin is I/O for CY7C017A only.
6.
A
is a no connect pin for 16K devices.
14
Document Number: 38-06045 Rev. *F
Page 3 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations (continued)
64-pin TQFP
Top View
I/O
2L
A
48
47
1
2
4L
A
A
I/O
3L
3L
I/O
4L
2L
46
45
3
4
A
A
I/O
5L
1L
GND
44
43
42
41
5
6
0L
I/O
6L
INT
L
I/O
7L
BUSY
7
L
GND
M/S
V
CC
8
CY7C006A (16K x 8)
GND
40
39
9
BUSY
I/O
0R
10
11
12
R
I/O
1R
38
37
INT
R
I/O
2R
A
A
A
A
A
0R
1R
2R
3R
V
CC
36
35
34
13
I/O
3R
14
15
I/O
4R
I/O
5R
33
16
4R
Selection Guide
CY7C006A
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–15
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–20
CY7C007A
CY7C016A
CY7C017A
–12[7]
Maximum Access Time (ns)
12
195
55
15
190
50
20
180
45
Typical Operating Current (mA)
Typical Standby Current for ISB1 (mA) (Both Ports TTL Level)
Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level)
0.05
0.05
0.05
Note
7. See page 7 for Load Conditions.
Document Number: 38-06045 Rev. *F
Page 4 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Definitions
Left Port
CEL
Right Port
Description
CER
Chip Enable
Read/Write Enable
Output Enable
Address
R/WL
R/WR
OER
OEL
A0L–A14L
I/O0L–I/O8L
SEML
A0R–A14R
I/O0R–I/O8R
SEMR
Data Bus Input/Output (I/O0–I/O7 for ×8 devices and I/O0–I/O8 for ×9)
Semaphore Enable
Interrupt Flag
Busy Flag
INTL
INTR
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
Ground
NC
No Connect
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
Architecture
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
consist of an array of 32K/16K words of 8 bits and 32K words
of 9 bits each of dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in
memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two Interrupt
(INT) pins can be utilized for port-to-port communication. Two
Semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power-down
feature controlled by CE. Each port is provided with its own
Output Enable control (OE), which allows data to be read from
the device.
The CY7C006A, CY7C007A and CY7C017A are available in
68-pin PLCC packages, the CY7C006A is also available in
64-pin TQFP, and the CY7C007A and CY7C016A are also
available in 80-pin TQFP packages.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in Table 1.
Functional Description
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
low-power CMOS 32K × 8/9 and 16K × 8/9 dual-port static
RAMs. Various arbitration schemes are included on the
devices to handle situations when multiple processors access
the same piece of data. Two ports are provided, permitting
independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
standalone 8/9-bit dual-port static RAMs or multiple devices
can be combined in order to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and
dual-port video/graphics memory.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
The upper two memory locations may be used for message
passing. The highest memory location (7FFF) is the mailbox
for the right port and the second-highest memory location
Document Number: 38-06045 Rev. *F
Page 5 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
(7FFE) is the mailbox for the left port. When one port writes to
the other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
dual-port memory locations. Semaphores are used to reserve
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For example,
if the left port wants to request a given resource, it sets a latch
by writing a zero to a semaphore location. The left port then
verifies its success in setting the latch by reading it. After writing
to the semaphore, SEM or OE must be deasserted for tSOP
before attempting to read the semaphore. The semaphore value
will be available tSWRD + tDOE after the rising edge of the
semaphore write. If the left port was successful (reads a zero), it
assumes control of the shared resource, otherwise (reads a one)
it assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side will succeed in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. The operation of the interrupts and their interaction with
Busy are summarized in Table 2.
Busy
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide on-chip arbitration to resolve simultaneous memory
location access (contention). If both ports’ CEs are asserted and
an address match occurs within tPS of each other, the busy logic
will determine which port has access. If tPS is violated, one port
will definitely gain permission to the location, but it is not
predictable which port will get that permission. BUSY will be
asserted tBLA after an address match or tBLC after CE is taken
LOW.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set to
one for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 3 shows sample semaphore opera-
tions.
Master/Slave
A M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output
of the master is connected to the BUSY input of the slave. This
will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (tBLC or tBLA), otherwise,
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
When reading a semaphore, all data lines output the semaphore
value. The read value is latched in an output register to prevent
the semaphore from changing state during a write from the other
port. If both ports attempt to access the semaphore within tSPS
of each other, the semaphore will definitely be obtained by one
side or the other, but there is no guarantee which side will control
the semaphore.
Semaphore Operation
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide eight semaphore latches, which are separate from the
Document Number: 38-06045 Rev. *F
Page 6 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
DC Input Voltage[10]........................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................>2001V
Latch-Up Current.....................................................>200 mA
Maximum Ratings[8]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .................................–65C to +150C
Ambient Temperature with
Power Applied ............................................–55C to +125C
Operating Range
Ambient
Temperature
Supply Voltage to Ground Potential................–0.3V to +7.0V
Range
VCC
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
Commercial
0C to +70C
5V 10%
Electrical Characteristics
Over the Operating Range
CY7C006A
CY7C007A
CY7C016A
CY7C017A
Parameter
Description
Unit
–12[9]
–15
–20
Typ Max
Min
Typ
Max Min
Typ Max Min
VOH
Output HIGH Voltage
(VCC = Min, IOH = –4.0 mA)
2.4
–
–
2.4
–
–
2.4
–
–
V
V
VOL
Output LOW Voltage
–
0.4
–
0.4
–
0.4
(VCC = Min, IOH = +4.0 mA)
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.2
–
–
2.2
–
–
2.2
–
–
V
V
0.8
10
0.8
10
0.8
10
Output Leakage Current
–10
–
–10
–
–10
–
A
Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Commercial
Industrial
195
55
325
190
215
280
305
180
45
275 mA
mA
–
–
–
–
–
–
–
–
ISB1
ISB2
ISB3
Standby Current
(Both Ports TTL Level)
CEL & CER VIH, f = fMAX
Commercial
Industrial
75
205
0.5
50
65
70
95
65
mA
mA
Standby Current
(One Port TTL Level)
CEL | CER VIH, f = fMAX
Commercial
Industrial
125
0.05
120
135
180
205
110
0.05
160 mA
mA
Standby Current
Commercial
Industrial
0.05
0.05
0.5
0.5
0.5
mA
mA
(Both Ports CMOS Level)
CEL & CER VCC 0.2 V,
f = 0
ISB4
Standby Current
(One Port CMOS Level) CEL
| CER VIH, f = fMAX
Commercial
Industrial
115
185
110
125
160
175
100
140 mA
mA
–
–
[10, 11]
Notes
8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
9. See page 7 for Load Conditions.
10. Pulse width < 20 ns.
11. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
MAX
RC RC
I
.
SB3
Document Number: 38-06045 Rev. *F
Page 7 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Capacitance Table[12]
Parameter
Description
Test Conditions
Max
10
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25 C, f = 1 MHz, VCC = 5.0 V
COUT
10
pF
AC Test Loads and Waveforms
5 V
5 V
R
TH
= 250
R1 = 893
OUTPUT
C = 30 pF
OUTPUT
R1 = 893
R2 = 347
OUTPUT
C = 5 pF
C = 30 pF
R2 = 347
V
TH
= 1.4 V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
AC Test Loads (Applicable to –12 only)[13]
ALL INPUTPULSES
90%
Z0 = 50
R = 50
OUTPUT
3.0 V
GND
90%
10%
10%
3 ns
C
3 ns
V
TH
= 1.4 V
(a) Load 1 (-12 only)
1 .00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Test Conditions: C = 10 pF.
Document Number: 38-06045 Rev. *F
Page 8 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics
Over the Operating Range[14]
CY7C006A
CY7C007A
CY7C016A
CY7C017A
Parameter
Description
Unit
–12[15]
–15
–20
Min
Max
Min
Max
Min
Max
READ CYCLE
tRC
Read Cycle Time
12
–
3
–
–
3
–
3
–
0
–
–
12
–
15
–
3
–
–
3
–
3
–
0
–
–
15
–
20
–
3
–
–
3
–
3
–
0
–
–
20
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
tOHA
[16]
tACE
tDOE
tLZOE
12
8
15
10
–
20
12
–
[17, 18, 19]
[17, 18, 19]
–
tHZOE
OE HIGH to High Z
10
–
10
–
12
–
[17, 18, 19]
tLZCE
CE LOW to Low Z
[17, 18, 19]
tHZCE
CE HIGH to High Z
10
–
10
–
12
–
[19]
tPU
tPD
CE LOW to Power-Up
CE HIGH to Power-Down
[19]
12
15
20
WRITE CYCLE
tWC
Write Cycle Time
12
10
10
0
–
–
15
12
12
0
–
–
20
15
15
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[16]
tSCE
tAW
tHA
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
–
–
–
–
–
–
[16]
tSA
tPWE
tSD
0
–
0
–
0
–
10
10
0
–
12
10
0
–
15
15
0
–
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
–
–
–
[22]
tHD
–
–
–
[18, 19]
tHZWE
–
10
–
–
10
–
–
12
–
[18, 19]
tLZWE
R/W HIGH to Low Z
3
3
3
[20]
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
–
25
20
–
30
25
–
45
30
[20]
tDDD
BUSY TIMING[21]
–
–
–
tBLA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
–
–
12
12
–
–
15
15
–
–
20
20
ns
ns
tBHA
Notes:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
I
/I and 30-pF load capacitance.
OI OH
15. See page 7 for Load Conditions.
16. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
17. At any given temperature and voltage condition for any given device, t
18. Test conditions used are Load 3.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
19. This parameter is guaranteed but not tested.
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
22. For 15 ns industrial parts t Min. is 0.5 ns.
HD
Document Number: 38-06045 Rev. *F
Page 9 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics
Over the Operating Range[14] (continued)
CY7C006A
CY7C007A
CY7C016A
CY7C017A
Parameter
Description
Unit
–12[15]
–15
–20
Min
Max
Min
Max
15
Min
Max
20
tBLC
tBHC
tPS
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
12
12
ns
ns
ns
ns
ns
ns
15
17
5
0
5
0
5
0
tWB
tWH
tBDD
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
11
13
15
[23]
12
15
20
INTERRUPT TIMING[24]
tINS
INT Set Time
12
12
15
15
20
20
ns
ns
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
10
5
ns
ns
ns
ns
5
5
5
tSAA
12
15
20
Timing
Data Retention Mode
Data Retention Mode
4.5V
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
designed with battery backup in mind. Data retention voltage and
supply current are guaranteed over temperature. The following
rules ensure data retention:
V
CC
4.5V
V
CC
2.0V
t
RC
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2 V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VCC – 0.2 V and 70% of VCC during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 V).
Parameter
ICCDR1
Test Conditions[25]
Max
1.5
Unit
mA
@ VCCDR = 2 V
Notes:
23. t
is a calculated parameter and is the greater of t
–t
(actual) or t
–t (actual).
BDD
WDD PWE
DDD SD
24. Test conditions used are Load 2.
25. CE = V , V = GND to V , T = 25 C. This parameter is guaranteed but not tested.
CC
in
CC
A
Document Number: 38-06045 Rev. *F
Page 10 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[26, 27, 28]
t
RC
ADDRESS
t
AA
t
t
OHA
OHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[26, 29, 30]
t
ACE
CE
OE
t
HZCE
t
DOE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Read Cycle No. 3 (Either Port)[26, 28, 29, 30]
t
RC
ADDRESS
t
AA
t
OHA
t
t
LZCE
t
ABE
CE
t
HZCE
t
ACE
LZCE
DATA OUT
Notes
26. R/W is HIGH for read cycles.
27. Device is continuously selected CE = V . This waveform cannot be used for semaphore reads.
IL
28. OE = V .
IL
29. Address valid prior to or coincident with CE transition LOW.
30. To access RAM, CE = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IH
IH
IL
Document Number: 38-06045 Rev. *F
Page 11 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing [31, 32, 33, 34]
t
WC
ADDRESS
OE
[36]
t
HZOE
t
AW
[35]
CE
[34]
PWE
t
t
t
HA
SA
R/W
DATAOUT
DATA IN
[36]
HZWE
t
t
LZWE
NOTE 37
NOTE 37
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing [31, 32, 33, 38]
t
WC
ADDRESS
t
AW
[35]
CE
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes
31. R/W or CE must be HIGH during all address transitions.
32. A write occurs during the overlap (t or t ) of a LOW CE or SEM.
SCE
PWE
33. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
34. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data
PWE
HZWE SD
to be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
SD
as short as the specified t
.
PWE
35. To access RAM, CE = V , SEM = V
.
IH
IL
36. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
37. During this period, the I/O pins are in the output state, and input signals must not be applied.
38. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document Number: 38-06045 Rev. *F
Page 12 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[39]
t
AA
t
OHA
A –A
0
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[40, 41, 42]
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
Notes
39. CE = HIGH for the duration of the above timing (both write and read cycle).
40. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
41. Semaphores are reset (available to both ports) at cycle start.
42. If t is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SPS
Document Number: 38-06045 Rev. *F
Page 13 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[43]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note
43. CE = CE = LOW.
L
R
Document Number: 38-06045 Rev. *F
Page 14 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[44]
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
ADDRESS MATCH
L,R
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
Busy Timing Diagram No. 2 (Address Arbitration)[44]
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note
44. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document Number: 38-06045 Rev. *F
Page 15 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
t
WC
ADDRESS
WRITE 7FFF
L
[45]
t
HA
CE
L
R/W
INT
L
R
[46]
t
INS
Right Side Clears INTR:
t
RC
READ 7FFF
ADDRESS
R
CE
R
[46]
INR
t
R/W
R
OE
R
INT
R
Right Side Sets INTL:
t
WC
ADDRESS
WRITE 7FFE
R
[45]
HA
t
CE
R
R
R/W
INT
L
[46]
INS
t
Left Side Clears INTL:
t
RC
READ 7FFE
R
ADDRESS
CE
L
L
[46]
INR
t
R/W
OE
L
L
INT
Notes
45. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
46. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INS
INR L L
Document Number: 38-06045 Rev. *F
Page 16 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
H
X
R/W
X
OE
X
SEM
H
I/O0–I/O8
Operation
High Z
Deselected: Power-Down
Read Data in Semaphore Flag
I/O Lines Disabled
Write into Semaphore Flag
Read
H
L
L
Data Out
High Z
X
H
X
X
H
L
L
Data In
Data Out
Data In
H
L
L
H
L
X
H
Write
L
X
X
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Left Port
Right Port
OER A0R–14R
X
Function
R/WL CEL
OEL
X
A0L–14L
7FFF
X
INTL R/WR CER
INTR
L[48]
H[47]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
L
X
X
7FFF
7FFE
X
X
X
L[47]
H[48]
X
X
L
7FFE
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O8 Left I/O0–I/O8Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Notes
47. If BUSY = L, then no change.
R
48. If BUSY = L, then no change.
L
Document Number: 38-06045 Rev. *F
Page 17 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Ordering Information
16K x 8 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C006A-20AC
Package Type
20
A65
A65
A65
J81
64-Pin Thin Quad Flat Pack
Commercial
CY7C006A-20AXC
CY7C006A-20AXI
CY7C006A-20JXC
64-Pin Pb-Free Thin Quad Flat Pack
64-Pin Pb-Free Thin Quad Flat Pack
68-Pin Pb-Free Plastic Leaded Chip Carrier
Commercial
Industrial
Commercial
Ordering Code Definitions
CY 7C 06A - 20
0
X
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type: X = A or J
A = 64-pin TQFP
J = 68-pin PLCC
Speed Grade: 20 ns
06A = Depth: 16K
0 = Width: × 8
7C = Dual Port SRAM
CY = Cypress Device
Document Number: 38-06045 Rev. *F
Page 18 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
64-Lead Pb-Free Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046 *D
Document Number: 38-06045 Rev. *F
Page 19 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Package Diagrams (continued)
80-Pin Thin Plastic Quad Flat Pack A80
80-Pin Pb-Free Thin Plastic Quad Flat Pack A80
51-85065 *C
68-Lead Plastic Leaded Chip Carrier J81
68-Lead Pb-Free Plastic Leaded Chip Carrier J81
51-85005 *B
Document Number: 38-06045 Rev. *F
Page 20 of 22
[+] Feedback
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Document History Page
Document Title: CY7C006A/CY7C007A/CY7C016A/CY7C017A 32K/16K x 8, 16K x 9 Dual-Port Static RAM
Document Number: 38-06045
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
110197
122295
237620
345376
09/29/01
12/27/02
See ECN
See ECN
SZV
Change from Spec number: 38-00831 to 38-06045
Power up requirements added to Maximum Ratings Information
Removed cross information from features section
*A
*B
*C
RBI
YDT
AEQ
Removed I-Temp versions for both packages, since they are not valid part
numbers.
*D
387333
See ECN
PCX
Included Pb-Free Logo
Included package: CY7C006A-20AI
Included Pb-Free packages:
CY7C006A-15AXC, CY7C006A-20AXC, CY7C006A-20AXI,
CY7C006A-20JXC, CY7C007A-20JXC, CY7C016A-15AXC
*E
*F
2896210
3110296
03/22/2010 RAME
12/14/2010 EYB
Updated Ordering Information
Updated Package Diagram
Updated Ordering Information.
Added Ordering Code Definitions.
Minor edits and updated in new template.
Document Number: 38-06045 Rev. *F
Page 21 of 22
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06045 Rev. *F
Revised December 17, 2010
Page 22 of 22
All products and company names mentioned in this document may be the trademarks of their respective holders.
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相关型号：
CY7C006A-20AXCT
Multi-Port SRAM, 16KX8, 20ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MS-026, TQFP-64
CYPRESS
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