CY7C006AV-20AC [CYPRESS]
3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM; 3.3V 4K / 8K / 16K / 32K X 8/9双口静态RAM
| 型号： | CY7C006AV-20AC |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM |
| 文件： | 总20页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
25/0251
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
• Fully asynchronous operation
• Automatic power-down
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
• 4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20/25 ns
• Low operating power
• Expandabledatabusto16/18bitsormoreusingMaster/
Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Pin-compatible and functionally equivalent to
IDT70V05, 70V06, and 70V07.
Logic Block Diagram
R/WL
CEL
R/WR
CER
OEL
OER
[1]
[1]
8/9
8/9
I/O0L–I/O7/8L
I/O0R–I/O7/8R
I/O
Control
I/O
Control
[2]
12–15
12–15
[2]
Address
Decode
Address
Decode
True Dual-Ported
A0L–A11–14L
A0R–A11–14R
RAM Array
12–15
12–15
[2]
[2]
A0L–A11–14L
A0R–A11–14R
CEL
CER
OER
Interrupt
Semaphore
Arbitration
OEL
R/WL
SEML
R/WR
SEMR
[3]
BUSYL
INTL
[3] BUSYR
INTR
M/S
Notes:
1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices;
3. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06051 Rev. *A
Revised December 27, 2002
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
cessor/multiprocessor designs, communications status buffer-
ing, and dual-port video/graphics memory.
Functional Description
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and
32K x8/9 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are pro-
vided, permitting independent, asynchronous access for reads
and writes to any location in memory. The devices can be uti-
lized as standalone 8/9-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16/18-bit or
wider master/slave dual-port static RAM. An M/S pin is provid-
ed for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Select (CE) pin.
Pin Configurations
68-Pin PLCC
Top View
9
8
7
6
5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
I/O
I/O
2L
3L
4L
A
A
A
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
5L
4L
3L
I/O
5L
A
2L
A
1L
A
0L
GND
I/O
6L
I/O
7L
INT
L
V
CC
BUSY
L
CY7C138AV (4K x 8)
CY7C139AV (4K x 9)
GND
GND
M/S
I/O
I/O
I/O
V
0R
1R
2R
BUSY
R
INT
21
22
23
24
25
26
R
A
0R
CC
I/O
3R
4R
5R
6R
A
A
47
46
45
44
1R
I/O
I/O
I/O
2R
A
3R
A
4R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
Notes:
4. I/O8L on the CY7C139AV.
5. I/O8R on the CY7C139AV.
Document #: 38-06051 Rev. *A
Page 2 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Configurations (continued)
PLCC
68-Pin
Top View
9
8
7
6
5 4 3 2 1 68 6766 65 64 63 62 61
I/O
2L
3L
4L
A
A
A
A
A
A
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
5L
4L
3L
I/O
I/O
I/O
5L
2L
1L
0L
GND
I/O
6L
I/O
7L
INT
L
V
CC
BUSY
L
CY7C144AV (8K x 8)
CY7C145AV (8K x 9)
GND
GND
M/S
I/O
I/O
0R
1R
2R
BUSY
R
I/O
V
INT
21
22
23
24
25
26
R
A
0R
CC
I/O
3R
4R
5R
A
A
47
46
45
44
1R
I/O
I/O
I/O
2R
A
3R
A
4R
6R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
64-Pin TQFP
Top View
I/O
I/O
A
48
47
2L
1
2
4L
A
A
3L
3L
4L
I/O
I/O
2L
46
45
3
4
A
A
1L
5L
GND
44
43
42
41
5
6
7
8
9
0L
I/O
6L
INT
L
I/O
7L
BUSY
L
GND
M/S
V
CC
CY7C144AV (8K x 8)
GND
40
39
BUSY
I/O
0R
10
R
I/O
1R
38
37
36
INT
R
11
12
13
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
I/O
3R
35
34
14
15
I/O
4R
I/O
5R
33
A
4R
16
Notes:
6. I/O8L on the CY7C145AV.
7. I/O8R on the CY7C145AV.
Document #: 38-06051 Rev. *A
Page 3 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Configurations (continued)
68-Pin PLCC
Top View
60
A
A
10
11
12
13
I/O
I/O
5L
2L
59
58
57
3L
4L
4L
I/O
A
A
A
3L
I/O
5L
2L
56
55
GND
1L
14
15
A
0L
I/O
6L
54
53
52
INT
I/O
7L
L
16
17
CY7C006AV (16K x 8)
CY7C007AV (32K x 8)
CY7C016AV (16K x 9)
CY7C017AV (32K x 9)
BUSY
V
CC
L
GND
M/S
GND
18
19
20
21
I/O
0R
51
50
I/O
1R
BUSY
R
I/O
2R
INT
R
49
48
V
CC
A
A
0R
22
23
I/O
3R
1R
47
I/O
4R
24
25
26
A
A
A
46
45
2R
3R
4R
I/O
5R
I/O6
R
44
64-Pin TQFP
Top View
I/O
I/O
A
48
47
2L
1
2
4L
A
A
3L
3L
4L
I/O
I/O
2L
46
45
3
4
A
A
1L
5L
GND
44
43
42
41
5
6
0L
I/O
6L
INT
L
I/O
7L
BUSY
7
L
GND
M/S
V
CC
8
CY7C006AV (16K x 8)
GND
40
39
9
BUSY
I/O
0R
10
11
12
R
I/O
1R
38
37
36
INT
R
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
13
I/O
3R
35
34
14
15
I/O
4R
I/O
5R
33
A
4R
16
Notes:
8. I/O for CY7C016AV and CY7C017AV only. NC for other parts.
9. Address line for CY7C007AV and CY7C017AV only. NC for other parts.
Document #: 38-06051 Rev. *A
Page 4 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Selection Guide
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-25
Maximum Access Time (ns)
20
120
35
25
115
30
Typical Operating Current (mA)
Typical Standby Current for ISB1 (mA)
(Both Ports TTL level)
Typical Standby Current for ISB3 (µA)
10 µA
10 µA
(Both Ports CMOS level)
Pin Definitions
Left Port
CEL
Right Port
CER
Description
Chip Enable
R/WL
OEL
R/WR
Read/Write Enable
Output Enable
OER
A0L–A14L
I/O0L–I/O8L
SEML
INTL
A0R–A14R
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K)
I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9)
SEMR
INTR
Semaphore Enable
Interrupt Flag
Busy Flag
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
Ground
NC
No Connect
Maximum Ratings [10]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current.................................................... >200 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial[12]
Temperature
0°C to +70°C
–40°C to +85°C
VCC
Supply Voltage to Ground Potential............... –0.5V to +4.6V
3.3V ± 300 mV
3.3V ± 300 mV
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to VCC+0.5V
DC Input Voltage[11] .................................–0.5V to VCC+0.5V
Notes:
10. The Voltage on any input or I/O pin can not exceed the power pin during power-up.
11. Pulse width < 20 ns.
12. Industrial parts are available in CY7C007AV and CY7C017AV only.
Document #: 38-06051 Rev. *A
Page 5 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Electrical Characteristics Over the Operating Range
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
-25
Parameter
VOH
Description
Output HIGH Voltage (VCC = 3.3V)
Output LOW Voltage
Min.
Typ. Max. Min.
Typ. Max.
Unit
V
2.4
2.4
VOL
0.4
2.0
0.8
0.4
V
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
0.8
10
V
IOZ
Output Leakage Current
–10
10
175
195
45
–10
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
Com’l.
Ind.[12]
Com’l.
Ind.[12]
Com’l.
Ind.[12]
Com’l.
Ind.[12]
Com’l.
Ind.[12]
120
140
35
115
30
65
10
60
165
ISB1
ISB2
ISB3
ISB4
Standby Current (Both Ports TTL Level)
40
[13]
CEL & CER ≥ VIH, f = fMAX
45
55
Standby Current (One Port TTL Level)
75
110
130
500
500
95
95
[13]
CEL | CER ≥ VIH, f = fMAX
85
Standby Current(BothPortsCMOS Level)
10
500
80
CEL & CER ≥ VCC – 0.2V, f = 0[13]
10
Standby Current (One Port CMOS Level)
70
[13]
CEL | CER ≥ VIH, f = fMAX
80
105
Capacitance[14]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
CIN
10
10
pF
pF
COUT
AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
30 pF
OUTPUT
R1 = 590Ω
R2 = 435Ω
OUTPUT
C
=
C = 30 pF
R2 = 435Ω
C = 5 pF
V
= 1.4V
TH
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(b) ThéveninEquivalent (Load 1)
(Used for tLZ, tHZ, tHZWE & tLZWE
including scope and jig)
ALL INPUTPULSES
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
Notes:
13. fMAX = 1/tRC. All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3
.
14. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06051 Rev. *A
Page 6 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Characteristics Over the Operating Range[15]
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
-25
Parameter
Description
Min.
20
Max.
Min.
25
3
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
20
25
tOHA
3
[16]
tACE
20
12
25
13
tDOE
[17, 18, 19]
tLZOE
3
3
0
3
3
0
[17, 18, 19]
tHZOE
OE HIGH to High Z
12
12
20
15
15
25
[17, 18, 19]
tLZCE
CE LOW to Low Z
[17, 18, 19]
tHZCE
CE HIGH to High Z
[19]
tPU
CE LOW to Power-Up
CE HIGH to Power-Down
[19]
tPD
WRITE CYCLE
tWC
Write Cycle Time
20
16
16
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[16]
tSCE
CE LOW to Write End
tAW
tHA
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
[16]
tSA
0
0
tPWE
tSD
16
12
0
20
15
0
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
tHD
[18, 19]
tHZWE
12
15
[18, 19]
tLZWE
R/W HIGH to Low Z
3
3
[20]
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
40
30
50
35
[20]
tDDD
BUSY TIMING[21]
tBLA
tBHA
tBLC
tBHC
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
20
20
20
16
20
20
20
17
ns
ns
ns
ns
ns
BUSY HIGH from CE HIGH
Port Set-Up for Priority
tPS
5
5
Note:
15. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
16. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
18. Test conditions used are Load 3.
19. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
Document #: 38-06051 Rev. *A
Page 7 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Characteristics Over the Operating Range[15] (continued)
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
-25
Parameter
Description
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
Min.
0
Max.
Min.
0
Max.
Unit
ns
tWB
tWH
15
17
ns
[22]
tBDD
20
25
ns
INTERRUPT TIMING[21]
tINS INT Set Time
tINR INT Reset Time
SEMAPHORE TIMING
20
20
20
20
ns
ns
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
10
5
12
5
ns
ns
ns
ns
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
5
5
tSAA
20
25
Data Retention Mode
Timing
The CY7C0138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data reten-
tion:
Data Retention Mode
3.0V
V
CC
3.0V
V
CC
> 2.0V
t
RC
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
Parameter
ICCDR1
Test Conditions[23]
Max.
Unit
µA
@ VCCDR = 2V
50
Notes:
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06051 Rev. *A
Page 8 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[24, 25, 26]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[24, 27, 28]
t
ACE
CE
OE
t
HZCE
t
DOE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Read Cycle No. 3 (Either Port)[24, 26, 27, 28]
t
RC
ADDRESS
t
AA
t
OHA
t
LZCE
LZCE
t
ABE
CE
t
HZCE
t
ACE
t
DATA OUT
Notes:
24. R/W is HIGH for read cycles.
25. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
26. OE = VIL
.
27. Address valid prior to or coincident with CE transition LOW.
28. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06051 Rev. *A
Page 9 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[29, 30, 31, 32]
t
WC
ADDRESS
OE
[33]
t
HZOE
t
AW
[34]
CE
[32]
PWE
t
SA
t
t
HA
R/W
DATAOUT
DATA IN
[33]
HZWE
t
t
LZWE
[35]
[35]
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing[29, 30, 31, 36]
t
WC
ADDRESS
t
AW
[34]
CE
t
SA
t
t
HA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
29. R/W must be HIGH during all address transitions.
30. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
31. HA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
t
32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tPWE
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. To access RAM, CE = VIL, SEM = VIH
.
.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06051 Rev. *A
Page 10 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[37]
t
t
OHA
SAA
A
–A
0 2
VALID ADRESS
VALID ADRESS
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[38, 39, 40]
A
–A
2L
0L
MATCH
R/W
L
SEM
L
t
SPS
A
–A
2R
0R
MATCH
R/W
R
SEM
R
Notes:
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
39. Semaphores are reset (available to both ports) at cycle start.
40. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06051 Rev. *A
Page 11 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[41]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
41. CEL = CER = LOW.
Document #: 38-06051 Rev. *A
Page 12 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[42]
CELValid First:
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
Busy Timing Diagram No. 2 (Address Arbitration)[42]
Left Address Valid First
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
42. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 38-06051 Rev. *A
Page 13 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
t
WC
ADDRESS
WRITE FFF (See Functional Description)
[43]
L
t
HA
CE
L
R/W
INT
L
R
[44]
t
INS
Right Side Clears INTR:
t
RC
READ FFF
(See Functional Description)
ADDRESS
R
CE
R
[44]
t
INR
R/W
R
OE
R
INT
R
:
Right SideSets INTL
t
WC
ADDRESS
R
WRITE FFE (See Functional Description)
[43]
t
HA
CE
R
R
R/W
INT
L
[44]
INS
t
Left Side Clears INTL:
t
RC
READ FFE
(See Functional Description)
ADDRESS
R
CE
L
[44]
t
INR
R/W
L
OE
INT
L
L
Notes:
43. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
44. INS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
t
Document #: 38-06051 Rev. *A
Page 14 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
neous memory location access (contention). If both ports’ CEs are
asserted and an address match occurs within tPS of each other, the
busy logic will determine which port has access. If tPS is violated, one
port will definitely gain permission to the location, but it is not predict-
able which port will get that permission. BUSY will be asserted tBLA
after an address match or tBLC after CE is taken LOW.
Architecture
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV consist of an array of 4K, 8K, 16K, and 32K
words of 8 and 9 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin
is provided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communication. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the device
can function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The device also has an automatic power-
down feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read from the
device.
Master/Slave
An M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external compo-
nents. Writing to slave devices must be delayed until after the BUSY
input has settled (tBLC or tBLA), otherwise, the slave chip may begin
a write cycle during a contention situation. When tied HIGH, the M/S
pin allows the device to be used as a master and, therefore, the
BUSY line is an output. BUSY can then be used to send the arbitra-
tion outcome to a slave.
Functional Description
Read and Write Operations
Semaphore Operation
When writing data must be set up for a duration of tSD before
the rising edge of R/W in order to guarantee a valid write. A write
operation is controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CEpin (see Write Cycle No. 2 waveform). Required
inputs for non-contention operations are summarized in Table 1.
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide eight semaphore latches, which
are separate from the dual-port memory locations. Sema-
phores are used to reserve resources that are shared between
the two ports. The state of the semaphore indicates that a
resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a sema-
phore location. The left port then verifies its success in setting
the latch by reading it. After writing to the semaphore, SEMor
OE must be deasserted for tSOP before attempting to read the sema-
phore. The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource, otherwise
(reads a one) it assumes the right port has control and continues to
poll the semaphore. When the right side has relinquished control of
the semaphore (by writing a one), the left side will succeed in gaining
control of the semaphore. If the left side no longer requires the sema-
phore, a one is written to cancel its request.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port tDDD after the data is presented on the other port.
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin and OE must also
be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C138AV/9AV, 1FFF for the CY7C144AV/5AV, 3FFF for the
CY7C006AV/16AV, 7FFF for the CY7C007AV/17AV) is the
mailbox for the right port and the second-highest memory lo-
cation (FFE for the CY7C138AV/9AV, 1FFE for the
CY7C144AV/5AV, 3FFE for the CY7C006AV/16AV, 7FFE for
the CY7C007AV/17AV) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is gen-
erated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user de-
fined.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
remain HIGH during SEM LOW). A0–2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. Howev-
er, if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soonas the left port released it. Table 3 shows sample
semaphore operations.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it. If an
application does not require message passing, do not connect
the interrupt pin to the processor’s interrupt request input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
When reading a semaphore, all data lines output the sema-
phore value. The read value is latched in an output register to
prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the sema-
phore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
Busy
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide on-chip arbitration to resolve simulta-
Document #: 38-06051 Rev. *A
Page 15 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
R/W
X
OE
X
SEM
I/O0–I/O8
Operation
H
L
High Z
Deselected: Power-Down
H
H
L
Data Out
High Z
Read Data in Semaphore Flag
I/O Lines Disabled
X
X
H
X
L
H
X
Data In
Write into Semaphore Flag
L
L
L
H
L
L
X
X
H
H
L
Data Out
Data In
Read
Write
X
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Left Port
Right Port
OER A0R–14R
X
Function
R/WL CEL
OEL
X
A0L–14L
FFF[45]
X
INTL R/WR CER
INTR
L[46]
H[47]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
L
X
X
FFF[45]
1FFE[45]
X
X
X
L[47]
H[46]
X
X
L
1FFE[45]
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O8 Left I/O0–I/O8 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Left port writes 1 to semaphore
Note:
45. See Functional Description for specific addresses by device part number.
46. If BUSYL = L, then no change.
47. If BUSYR = L, then no change.
Document #: 38-06051 Rev. *A
Page 16 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Ordering Information
Package Availability Guide
Device
Organization
4K x 8
68-Pin PLCC
64-Pin TQFP
CY7C138AV
CY7C139AV
CY7C144AV
CY7C145AV
CY7C006AV
CY7C016AV
CY7C007AV
CY7C017AV
X
X
X
X
X
X
X
X
4K x 9
8K x 8
X
X
8K x 9
16K x 8
16K x 9
32K x 8
32K x 9
4K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C138AV–20JC
CY7C138AV–25JC
Package Type
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
Range
Commercial
Commercial
20
J81
J81
25
4K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C139AV–20JC
CY7C139AV–25JC
Package Type
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
20
J81
J81
Commercial
Commercial
25
8K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C144AV–20AC
CY7C144AV–20JC
CY7C144AV–25AC
CY7C144AV–25JC
Package Type
64-Pin Thin Quad Flat Pack
20
A65
J81
A65
J81
Commercial
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
25
Commercial
68-Pin Plastic Leaded Chip Carrier
8K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C145AV–20JC
CY7C145AV–25JC
Package Type
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
20
J81
J81
Commercial
Commercial
25
16K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C006AV–20AC
CY7C006AV–20JC
CY7C006AV–25AC
CY7C006AV–25JC
Package Type
64-Pin Thin Quad Flat Pack
20
A65
J81
A65
J81
Commercial
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
25
Commercial
68-Pin Plastic Leaded Chip Carrier
Document #: 38-06051 Rev. *A
Page 17 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Ordering Information (continued)
16K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C016AV–20JC
CY7C016AV–25JC
Package Type
Range
Commercial
Commercial
20
J81
J81
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
25
32K x8 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C007AV–20JC
CY7C007AV–20JI
CY7C007AV–25JC
Package Type
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
20
J81
J81
J81
Commercial
Industrial
25
Commercial
32K x9 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C017AV–20JC
CY7C017AV–20JI
CY7C017AV–25JC
Package Type
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
20
J81
J81
J81
Commercial
Industrial
25
Commercial
Document #: 38-06051 Rev. *A
Page 18 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
Document #: 38-06051 Rev. *A
Page 19 of 20
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document Title: CY7C138AV/144AV/006AV/CY7C139AV/145AV/016AV/CY7C007AV/017AV 3.3V 4K/8K/16K/32K x 8/9
Dual Port SRAM
Document Number: 38-06051
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
110203
Description of Change
Change from Spec number: 38-00837 to 38-06051
Power up requirements added to Maximum Ratings Information
12/02/01
12/27/02
SZV
RBI
*A
122301
Document #: 38-06051 Rev. *A
Page 20 of 20
相关型号：
©2020 ICPDF网 联系我们和版权申明