CY7C006A-20JCT [CYPRESS]
Dual-Port SRAM, 16KX8, 20ns, CMOS, PQCC68, PLASTIC, LCC-68;
| 型号： | CY7C006A-20JCT |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 16KX8, 20ns, CMOS, PQCC68, PLASTIC, LCC-68 |
| 文件： | 总20页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C006A
CY7C007A
CY7C017A32K/16K
x 8, 32K x 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32K/16K x8, 32K/16K x9
Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
Logic Block Diagram
R/WL
R/WR
CER
CEL
OEL
OER
8/9
[2]
I/O0L–I/O7/8L
8/9
[2]
I/O0R–I/O7/8R
I/O
I/O
Control
Control
14/15
14/15
Address
Decode
Address
Decode
True Dual-Ported
[4]
[4]
A0L–A13/14L
A0R–A13/14R
RAM Array
14/15
14/15
[4]
[4]
A0L–A13/14L
CEL
OEL
R/WL
A0R–A13/14R
CER
Interrupt
Semaphore
Arbitration
OER
R/WR
SEML
BUSYL
INTL
SEMR
[3]
[3] BUSYR
INTR
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. See page 7 for Load Conditions.
2. I/O –I/O for x8 devices; I/O –I/O for x9 devices.
0
7
0
8
3. BUSY is an output in master mode and an input in slave mode.
4. A –A for 16K; A –A for 32K devices.
0
13
0
14
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06045 Rev. *C
Revised April 11, 2005
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations
68-Pin PLCC
Top View
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
A
A
10
11
12
13
14
15
I/O
I/O
5L
2L
3L
4L
I/O
4L
A
A
A
3L
2L
1L
I/O
GND
5L
A
0L
I/O
6L
INT
BUSY
GND
M/S
BUSY
I/O
7L
L
16
CY7C006A (16K x 8)
CY7C007A (32K x 8)
CY7C017A (32K x 9)
V
17
L
CC
GND
18
19
20
21
22
23
24
25
26
I/O
0R
I/O
1R
R
I/O
2R
INT
R
V
A
1R
CC
0R
A
I/O
3R
I/O
4R
A
2R
3R
4R
I/O
5R
A
A
I/O6
R
44
80-Pin TQFP
Top View
NC
2L
1
2
3
4
5
6
7
8
NC
60
59
I/O
A
4L
5L
I/O
I/O
I/O
A
3L
4L
5L
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
A
3L
A
2L
A
1L
A
0L
GND
I/O
6L
I/O
7L
INT
L
BUSY
GND
M/S
BUSY
INT
V
L
9
10
CC
NC
CY7C007A (32K x 8)
CY7C016A (16K X 9)
GND
11
12
13
14
15
16
I/O
0R
R
I/O
1R
R
I/O
V
I/O
I/O
I/O
I/O
2R
A
0R
A
1R
A
2R
A
3R
CC
3R
4R
5R
6R
17
A
4R
18
19
20
NC
NC
NC
Notes:
5. This pin is I/O for CY7C017A only.
6. A is a no connect pin for 16K devices.
14
Document #: 38-06045 Rev. *C
Page 2 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Configurations (continued)
64-Pin TQFP
Top View
I/O
2L
A
4L
48
1
A
I/O
3L
47
46
45
2
3
4
3L
A
2L
I/O
4L
A
1L
I/O
5L
A
INT
L
BUSY
GND
M/S
BUSY
R
INT
R
GND
44
43
42
41
40
39
38
37
36
35
34
5
6
7
8
9
10
11
12
13
14
15
0L
I/O
6L
I/O
7L
L
V
CC
CY7C006A (16K x 8)
GND
I/O
0R
I/O
1R
I/O
2R
A
0R
A
1R
V
CC
A
2R
I/O
3R
A
3R
I/O
4R
I/O
5R
33
A
4R
16
Selection Guide
CY7C006A
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-15
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-20
CY7C007A
CY7C016A
CY7C017A
-12[1]
Maximum Access Time (ns)
Typical Operating Current (mA)
Typical Standby Current for ISB1 (mA) (Both Ports TTL Level)
Typical Standby Current for ISB3 (mA) (Both Ports CMOS Level)
12
195
55
15
190
50
20
180
45
0.05
0.05
0.05
Document #: 38-06045 Rev. *C
Page 3 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Pin Definitions
Left Port
CEL
Right Port
Description
CER
Chip Enable
Read/Write Enable
Output Enable
Address
R/WL
R/WR
OER
OEL
A0L–A14L
I/O0L–I/O8L
SEML
A0R–A14R
I/O0R–I/O8R
SEMR
Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9)
Semaphore Enable
Interrupt Flag
Busy Flag
INTL
INTR
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
Ground
NC
No Connect
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
Architecture
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
consist of an array of 32K/16K words of 8 bits and 32K words
of 9 bits each of dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin
is provided on each port. Two Interrupt (INT) pins can be utilized for
port-to-port communication. Two Semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the devices
can function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The devices also have an automatic
power-down feature controlled by CE. Each port is provided with its
own Output Enable control (OE), which allows data to be read from
the device.
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
The CY7C006A, CY7C007A, and CY7C017A are available in
68-pin PLCC packages, the CY7C006A is also available in
64-pin TQFP, and the CY7C007A and CY7C016A are also
available in 80-pin TQFP packages.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa-
rized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Functional Description
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
low-power CMOS 32K x 8/9 and 16K x 8/9 dual-port static
RAMs. Various arbitration schemes are included on the
devices to handle situations when multiple processors access
the same piece of data. Two ports are provided, permitting
independent, asynchronous access for reads and writes to
any location in memory. The devices can be utilized as
standalone 8/9-bit dual-port static RAMs or multiple devices
can be combined in order to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and
dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (7FFF) is the mailbox
for the right port and the second-highest memory location
(7FFE) is the mailbox for the left port. When one port writes to
Document #: 38-06045 Rev. *C
Page 4 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
the other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. The operation of the interrupts and their interaction
with Busy are summarized in Table 2.
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For
example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be
deasserted for tSOP before attempting to read the semaphore.
The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was
successful (reads a zero), it assumes control of the shared
resource, otherwise (reads a one) it assumes the right port has
control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a
one), the left side will succeed in gaining control of the
semaphore. If the left side no longer requires the semaphore,
a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
Busy
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide on-chip arbitration to resolve simultaneous memory
location access (contention). If both ports’ CEs are asserted
and an address match occurs within tPS of each other, the busy
logic will determine which port has access. If tPS is violated,
one port will definitely gain permission to the location, but it is
not predictable which port will get that permission. BUSY will
be asserted tBLA after an address match or tBLC after CE is
taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
When reading a semaphore, all data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Semaphore Operation
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
provide eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
Document #: 38-06045 Rev. *C
Page 5 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
DC Input Voltage[8] .........................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
Latch-Up Current..................................................... >200 mA
Maximum Ratings[7]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage to Ground Potential............... –0.3V to +7.0V
Range
Temperature
VCC
DC Voltage Applied to Outputs
Commercial
0°C to +70°C
5V ± 10%
in High Z State ............................................... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-12[1]
-15
-20
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
Output HIGH Voltage
2.4
2.4
2.4
V
(VCC = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage
0.4
0.4
0.4
V
(VCC = Min., IOH = +4.0 mA)
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
2.2
2.2
2.2
V
V
µA
mA
mA
0.8
10
325
0.8
10
280
305
0.8
10
275
–10
–10
–10
Operating Current
Com’l.
Ind.
195
55
190
215
180
45
(VCC = Max., IOUT = 0 mA)
Outputs Disabled
ISB1
ISB2
ISB3
Standby Current
Com’l.
Ind.
75
205
0.5
50
65
70
95
65
160
0.5
mA
mA
(Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX
Standby Current
Com’l.
Ind.
125
0.05
120
135
180
205
110
0.05
mA
mA
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Standby Current
(Both Ports CMOS Level)
CEL & CER ≥ VCC − 0.2V,
f = 0
Com’l.
Ind.
0.05
0.05
0.5
0.5
mA
mA
ISB4
Standby Current
Com’l.
Ind.
115
185
110
125
160
175
100
140
mA
mA
(One Port CMOS Level)
[8, 9]
CEL | CER ≥ VIH, f = fMAX
Capacitance Table[10]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
10
10
pF
pF
V
CC = 5.0V
COUT
Notes:
7. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
8. Pulse width < 20 ns.
9. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
.
MAX
RC
RC
SB3
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06045 Rev. *C
Page 6 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
AC Test Loads and Waveforms
5V
5V
R
TH
= 250Ω
R1 = 893Ω
OUTPUT
C = 30 pF
OUTPUT
R1 = 893Ω
OUTPUT
C = 5 pF
C = 30 pF
R2 = 347Ω
R2 = 347Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay(Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
(b) Thévenin Equivalent (Load 1)
AC Test Loads (Applicable to -12 only)[11]
ALL INPUTPULSES
90%
Z0 = 50Ω
R = 50Ω
OUTPUT
3.0V
GND
90%
10%
3 ns
10%
C
3 ns
≤
V
TH
= 1.4V
≤
(a) Load 1 (-12 only)
1 .00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
11. Test Conditions: C = 10 pF.
Document #: 38-06045 Rev. *C
Page 7 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics Over the Operating Range[12]
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–12[1]
–15
–20
Parameter
READ CYCLE
tRC
tAA
Description
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Min.
Max.
Min.
Max.
Min.
20
Max.
Unit
12
3
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
20
tOHA
3
[13]
tACE
tDOE
tLZOE
12
8
15
10
20
12
[14, 15, 16]
[14, 15, 16]
3
3
0
3
3
0
3
3
0
tHZOE
10
10
12
10
10
15
12
12
20
[14, 15, 16]
tLZCE
[14, 15, 16]
tHZCE
[16]
[16]
tPU
tPD
WRITE CYCLE
tWC
Write Cycle Time
CE LOW to Write End
12
10
10
0
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[13]
tSCE
tAW
tHA
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
[13]
tSA
tPWE
tSD
0
0
0
10
10
0
12
10
0
15
15
0
[19]
tHD
[15, 16]
tHZWE
tLZWE
tWDD
10
10
12
[15, 16]
3
3
3
[17]
25
20
30
25
45
30
[17]
tDDD
BUSY TIMING[18]
tBLA
BUSY LOW from Address Match
12
12
12
12
15
15
15
15
20
20
20
17
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
tPS
5
5
5
Notes:
12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OI OH
13. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
LZOE
14. At any given temperature and voltage condition for any given device, t
15. Test conditions used are Load 3.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
16. This parameter is guaranteed but not tested.
17. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
18. Test conditions used are Load 2.
19. For 15 ns industrial parts t Min. is 0.5 ns.
HD
Document #: 38-06045 Rev. *C
Page 8 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics Over the Operating Range[12] (continued)
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–12[1]
–15
–20
Parameter
tWB
Description
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
Min.
0
11
Max.
Min.
0
13
Max.
Min.
0
15
Max.
Unit
ns
ns
tWH
tBDD
[20]
12
15
20
ns
INTERRUPT TIMING[18]
tINS
tINR
INT Set Time
INT Reset Time
12
12
15
15
20
20
ns
ns
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
5
10
5
5
10
5
5
ns
ns
ns
ns
tSAA
12
15
20
Timing
Data Retention Mode
Data Retention Mode
4.5V
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The
following rules ensure data retention:
V
CC
4.5V
V
CC
> 2.0V
t
RC
1. Chip Enable (CE) must be held HIGH during data retention,
V
CC
to V – 0.2V
CC
V
within VCC to VCC – 0.2V.
IH
CE
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
Parameter
Test Conditions[21]
Max.
Unit
minimum operating voltage (4.5 volts).
ICCDR1
@ VCCDR = 2V
1.5
mA
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[22, 23, 24]
t
RC
ADDRESS
t
AA
t
t
OHA
OHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Notes:
20. t
is a calculated parameter and is the greater of t
–t
(actual) or t
–t (actual).
BDD
WDD PWE
DDD SD
21. CE = V , V = GND to V , T = 25°C. This parameter is guaranteed but not tested.
CC
in
CC
A
22. R/W is HIGH for read cycles.
23. Device is continuously selected CE = V . This waveform cannot be used for semaphore reads.
IL
24. OE = V .
IL
Document #: 38-06045 Rev. *C
Page 9 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Read Cycle No. 2 (Either Port CE/OE Access)[22, 25, 26]
t
ACE
CE
OE
t
HZCE
t
DOE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
Read Cycle No. 3 (Either Port)[22, 24, 25, 26]
t
RC
ADDRESS
t
AA
t
OHA
t
LZCE
t
ABE
CE
t
HZCE
t
ACE
t
LZCE
DATA OUT
Notes:
25. Address valid prior to or coincident with CE transition LOW.
26. To access RAM, CE = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IH
IH
IL
Document #: 38-06045 Rev. *C
Page 10 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing [27, 28, 29, 30]
t
WC
ADDRESS
OE
[32]
t
HZOE
t
AW
[31]
CE
[30]
PWE
t
SA
t
t
HA
R/W
DATAOUT
DATA IN
[32]
HZWE
t
t
LZWE
NOTE 33
NOTE 33
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing [27, 28, 29, 34]
t
WC
ADDRESS
t
AW
[31]
CE
t
SA
t
t
HA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
27. R/W or CE must be HIGH during all address transitions.
28. A write occurs during the overlap (t
or t
) of a LOW CE or SEM.
PWE
SCE
29. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data
PWE
HZWE SD
to be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
SD
as short as the specified t
.
PWE
31. To access RAM, CE = V , SEM = V
.
IL
IH
32. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
33. During this period, the I/O pins are in the output state, and input signals must not be applied.
34. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06045 Rev. *C
Page 11 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[35]
t
AA
t
OHA
A –A
0
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[36, 37, 38]
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
Notes:
35. CE = HIGH for the duration of the above timing (both write and read cycle).
36. I/O = I/O = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
37. Semaphores are reset (available to both ports) at cycle start.
38. If t is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SPS
Document #: 38-06045 Rev. *C
Page 12 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[39]
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
39. CE = CE = LOW.
L
R
Document #: 38-06045 Rev. *C
Page 13 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[40]
CELValid First:
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
ADDRESS MATCH
L,R
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
Busy Timing Diagram No. 2 (Address Arbitration)[40]
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
40. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document #: 38-06045 Rev. *C
Page 14 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
t
WC
ADDRESS
WRITE 7FFF
L
[41]
t
HA
CE
L
R/W
INT
L
R
[42]
t
INS
Right Side Clears INTR:
t
RC
READ 7FFF
ADDRESS
R
CE
R
[42]
INR
t
R/W
R
OE
R
INT
R
Right Side Sets INTL:
t
WC
ADDRESS
WRITE 7FFE
R
[41]
HA
t
CE
R
R
R/W
INT
L
[42]
INS
t
Left Side Clears INTL:
t
RC
ADDRESS
READ 7FFE
R
CE
L
L
[42]
t
INR
R/W
OE
L
L
INT
Notes:
41. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
42. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INS
INR L L
Document #: 38-06045 Rev. *C
Page 15 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
H
X
R/W
X
OE
X
SEM
H
I/O0–I/O8
Operation
High Z
Deselected: Power-Down
H
L
L
Data Out
High Z
Read Data in Semaphore Flag
I/O Lines Disabled
Write into Semaphore Flag
Read
X
H
X
X
H
L
L
Data In
Data Out
Data In
H
L
L
H
L
X
H
Write
L
X
X
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–14L
7FFF
X
INTL R/WR CER
OER
X
A0R–14R
X
INTR
L[44]
H[43]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
L
7FFF
7FFE
X
X
X
L[43]
H[44]
X
L
7FFE
X
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O8 Left I/O0–I/O8Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Notes:
43. If BUSY = L, then no change.
R
44. If BUSY = L, then no change.
L
Document #: 38-06045 Rev. *C
Page 16 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Ordering Information
16K x8 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
Package Type
Range
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
12[1]
CY7C006A-12AC
A65
J81
A65
J81
A65
J81
64-Pin Thin Quad Flat Pack
CY7C006A-12JC
CY7C006A-15AC
CY7C006A-15JC
CY7C006A-20AC
CY7C006A-20JC
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
15
20
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
68-Pin Plastic Leaded Chip CarrieR
32K x8 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
80-Pin Thin Quad Flat Pack
12[1]
CY7C007A-12AC
A80
J81
A80
J81
A80
J81
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C007A-12JC
CY7C007A-15AC
CY7C007A-15JC
CY7C007A-20AC
CY7C007A-20JC
68-Pin Plastic Leaded Chip Carrier
80-Pin Thin Quad Flat Pack
15
20
68-Pin Plastic Leaded Chip Carrier
80-Pin Thin Quad Flat Pack
68-Pin Plastic Leaded Chip CarrieR
16K x9 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
12[1]
15
Ordering Code
Package Type
80-Pin Plastic Leaded Chip Carrier
80-Pin Plastic Leaded Chip Carrier
80-Pin Plastic Leaded Chip Carrier
CY7C016A-12AC
A80
A80
A80
Commercial
Commercial
Commercial
CY7C016A-15AC
CY7C016A-20AC
20
32K x9 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
12[1]
15
Ordering Code
Package Type
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
CY7C017A-12JC
J81
J81
J81
Commercial
Commercial
Commercial
CY7C017A-15JC
CY7C017A-20JC
20
Document #: 38-06045 Rev. *C
Page 17 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-*B
Document #: 38-06045 Rev. *C
Page 18 of 20
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Package Diagrams (continued)
80-Pin Thin Plastic Quad Flat Pack A80
51-85065-*B
68-Lead Plastic Leaded Chip Carrier J81
51-85005-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06045 Rev. *C
Page 19 of 20
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Document History Page
Document Title: CY7C006A/CY7C007A/CY7C016A/CY7C017A 32K/16K x 8, 32K/16K x 9 Dual Port Static RAM
Document Number: 38-06045
Issue
Orig. of
Change
SZV
REV.
**
*A
*B
*C
ECN NO. Date
Description of Change
110197
122295
237620
345376
09/29/01
12/27/02
See ECN YDT
See ECN AEQ
Change from Spec number: 38-00831 to 38-06045
Power up requirements added to Maximum Ratings Information
Removed cross information from features section
RBI
Removed I-Temp versions for both packages, since they are not valid part
numbers.
Document #: 38-06045 Rev. *C
Page 20 of 20
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