CY7B9910-7SI [CYPRESS]
Low Skew Clock Buffer; 低偏移的时钟缓冲器
| 型号： | CY7B9910-7SI |
| 厂家： | 
CYPRESS |
| 描述： | Low Skew Clock Buffer |
| 文件： | 总7页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7B9920
fax id: 3516
CY7B9910
CY7B9920
Low Skew
Clock Buffer
Features
Block Diagram Description
• All outputs skew <100 ps typical (250 max.)
• 15- to 80-MHz output operation
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive 50Ω terminated lines
• Low operating current
Phase Frequency Detector and Filter
These two blocks accept inputs from the reference frequency
(REF) input and the feedback (FB) input and generate correc-
tion information to control the frequency of the Voltage-Con-
trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.
• 24-pin SOIC package
VCO
• Jitter: <200 ps peak to peak, <25 ps RMS
• Compatible with Pentium™-based processors
The VCO accepts analog control inputs from the PLL filter
block and generates a frequency. The operational range of the
VCO is determined by the FS control pin.
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low-skew system clock distribution. These multiple-output
clock drivers optimize the timing of high-performance comput-
er systems. Eight individual drivers can each drive terminated
transmission lines with impedances as low as 50Ω while deliv-
ering minimal and specified output skews and full-swing logic
levels (CY7B9910 TTL or CY7B9920 CMOS).
Test Mode
The TEST input is a three-level input. In normal system oper-
ation, this pin is connected to ground, allowing the
CY7B9910/CY7B9920 to operate as explained above. (For
testing purposes, any of the three-level inputs can have a re-
movable jumper to ground, or be tied LOW through a 100Ω
resistor. This will allow an external tester to change the state of
these pins.)
The completely integrated PLL allows “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low-frequency clock that can be multiplied by virtu-
ally any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock speed
and flexibility.
If the TEST input is forced to its MID or HIGH state, the device
will operate with its internal phase-locked loop disconnected,
and input levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal
mode.
Logic Block Diagram
Pin Configuration
TEST
Voltage
Controlled
Oscillator
PHASE
FREQ
DET
FB
FILTER
REF
SOIC
Top View
FS
REF
1
24
23
22
21
GND
TEST
NC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
V
CCQ
FS
2
3
NC
4
GND
V
CCQ
20
19
18
17
16
15
5
V
CCN
6
V
CCN
Q0
7B9910
7B9920
Q7
Q6
GND
Q5
Q4
7
Q1
GND
Q2
8
9
10
11
12
14
13
Q3
V
CCN
V
CCN
FB
7B9910–1
7B9910–2
Pentium is a trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 1994 – Revised July 7, 1997
CY7B9910
CY7B9920
Pin Definitions
Signal
Name
I/O
Description
REF
I
Reference frequency input. This input supplies thefrequencyand timing against which allfunctional
variation is measured.
FB
I
I
PLL feedback input (typically connected to one of the eight outputs).
Three-level frequency range select.
Three-level select. See Test Mode section.
Clock outputs.
[9,10,11]
FS
TEST
I
Q[0..7]
O
V
V
PWR
PWR
PWR
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
CCN
CCQ
GND
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW) .............................64 mA
5V ± 10%
5V ± 10%
Electrical Characteristics Over the Operating Range
CY7B9910
CY7B9920
Min. Max.
Parameter
Description
Test Conditions
= Min., I = –16 mA
Min.
Max.
Unit
V
Output HIGH Voltage
V
V
V
V
2.4
V
OH
CC
CC
CC
CC
OH
= Min., I =–40 mA
V
–0.75
CC
OH
V
Output LOW Voltage
= Min., I = 46 mA
0.45
V
OL
OL
= Min., I = 46 mA
0.45
OL
V
V
V
V
V
Input HIGH Voltage
(REF and FB inputs only)
2.0
V
V
1.35
–
V
CC
V
V
IH
CC
CC
Input LOW Voltage
(REF and FB inputs only)
–0.5
0.8
–0.5
1.35
IL
Three-Level Input HIGH
Min. ≤ V ≤ Max.
V
– 1V
V
V
– 1V
V
CC
V
IHH
IMM
ILL
CC
CC
CC
CC
[1]
Voltage (Test, FS)
Three-Level Input MID
Min. ≤ V ≤ Max.
V
/2 –
V
/2 +
V
/2 –
V /2 +
CC
500 mV
V
CC
CC
CC
500 mV
CC
[1]
Voltage (Test, FS)
500 mV
500 mV
Three-Level Input LOW
Min. ≤ V ≤ Max.
0.0
1.0
0.0
1.0
V
CC
[1]
Voltage (Test, FS)
I
I
I
I
I
Input HIGH Leakage Current
(REF and FB inputs only)
V
V
V
V
V
= Max., V = Max.
10
10
µA
µA
µA
µA
µA
IH
CC
CC
IN
Input LOW Leakage Current
(REF and FB inputs only)
= Max., V = 0.4V
–500
–50
–500
–50
IL
IN
Input HIGH Current
(Test, FS)
= V
CC
200
50
200
50
IHH
IMM
ILL
IN
IN
IN
Input MID Current
(Test, FS)
= V /2
CC
Input LOW Current
(Test, FS)
= GND
–200
–200
2
CY7B9910
CY7B9920
Electrical Characteristics Over the Operating Range (continued)
CY7B9910
Min. Max.
CY7B9920
Min. Max.
Parameter
Description
Test Conditions
= Max., V
= GND (25°C only)
Unit
I
Output Short Circuit
V
–250
N/A
mA
OS
CC
OUT
[2]
Current
I
I
Operating Current Used by
Internal Circuitry
V
=V
CCQ
=Max., Com’l
Mil/Ind
85
90
85
90
mA
mA
mW
CCQ
CCN
All Input
Selects Open
Output Buffer Current per
V
= V = Max.,
CCQ
= 0 mA
14
19
CCN
CCN
[3]
Output Pair
I
OUT
Input Selects Open, f
MAX
[5]
PD
Power Dissipation per
V
= V
= Max.,
78
104
CCN
CCQ
[4]
Output Pair
I
= 0 mA
OUT
Input Selects Open, f
MAX
Capacitance[6]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz, V = 5.0V
Max.
10
Unit
C
Input Capacitance
pF
IN
A
CC
Notes:
1. These inputs are normally wired to VCC, GND, orleft unconnected (actual threshold voltages varyas a percentage of VCC). Internal termination resistors hold unconnected
inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are
achieved.
2. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short
circuit protected.
3. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B9910:
I
CCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
CCN = [(3.5+ .17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
I
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
4. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 3 for variable definition.
5. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.
6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
5V
3.0V
2.0V
=1.5V
0.8V
0.0V
2.0V
=1.5V
0.8V
R1=130
R2=91
R1
R2
V
th
V
th
C = 50 pF (C = 30pF for –5 and – 2 devices)
L
L
C
(Includes fixture and probe capacitance)
L
≤1ns
≤1ns
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (Cy7B9910)
V
CC
V
CC
R1=100
R2=100
80%
80%
R1
R2
C = 50 pF (C =30 pF for –5 and – 2devices)
V
th
= V /2
V
th
= V /2
L
L
CC
CC
(Includes fixture and probe capacitance)
20%
0.0V
20%
C
L
≤ 3ns
≤ 3ns
7B9910–5
7B9910–6
CMOS Input Test Waveform (CY7B9920)
CMOS AC Test Load (CY7B9920)
3
CY7B9910
CY7B9920
[7]
Switching Characteristics Over the Operating Range
[8]
[8]
CY7B9910–2
CY7B9920–2
Parameter
Description
FS = LOW
Min.
Typ.
Max.
Min.
15
Typ.
Max.
30
Unit
[9, 10]
[9, 10]
f
Operating Clock
15
25
30
50
80
MHz
NOM
Frequency in MHz
FS = MID
25
50
[9, 10, 11]
[12]
FS = HIGH
40
40
80
t
t
t
t
t
t
t
t
t
t
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
RPWH
RPWL
SKEW
DEV
[13, 14]
Zero Output Skew (All Outputs)
0.1
0.25
0.75
+0.25
+0.65
1.2
0.1
0.25
0.75
+0.25
+0.65
2.5
[14, 15]
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
–0.25
–0.65
0.15
0.0
0.0
1.0
1.0
–0.25
–0.65
0.5
0.0
0.0
2.0
2.0
PD
[16]
Output Duty Cycle Variation
ODCV
ORISE
OFALL
LOCK
JR
[17, 18]
Output Rise Time
[17, 18]
Output Fall Time
0.15
1.2
0.5
2.5
[19]
PLL Lock Time
0.5
0.5
Cycle-to-Cycle Output Jitter Peak to Peak
RMS
200
25
200
25
CY7B9910–5
Typ.
CY7B9920–5
Typ.
Parameter
Description
Min.
15
Max.
30
Min.
15
Max.
30
Unit
[9, 10]
f
Operating Clock
FS = LOW
MHz
NOM
Frequency in MHz
[9, 10]
FS = MID
25
50
25
50
[9, 10, 11]
[12]
FS = HIGH
40
80
40
80
t
t
t
t
t
t
t
t
t
t
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
RPWH
RPWL
SKEW
DEV
[13, 14]
Zero Output Skew (All Outputs)
0.25
0.5
1.0
0.25
0.5
1.0
[8, 15]
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
–0.5
–1.0
0.15
0.15
0.0
0.0
1.0
1.0
+0.5
+1.0
1.5
–0.5
–1.0
0.5
0.0
0.0
2.0
2.0
+0.5
+1.0
3.0
PD
[16]
Output Duty Cycle Variation
ODCV
ORISE
OFALL
LOCK
JR
[17, 18]
Output Rise Time
[17, 18]
Output Fall Time
1.5
0.5
3.0
[19]
PLL Lock Time
0.5
0.5
[8]
Cycle-to-Cycle Output Jitter Peak to Peak
200
25
200
25
[8]
RMS
Notes:
7. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unlessotherwise specified.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
10. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO(see Logic Block Diagram). The frequency appearing at the REF and
FB inputs will be fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/X when the device is configured for a frequency
multiplication by using external division in the feedback path of value X.
11. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 4.3V.
12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80-MHz with a 30-pF load.
13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
14.
15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, etc.).
16. ODCV is the deviation of the output from a 50% duty cycle.
tSKEW is defined as the skew between outputs.
t
17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50Ω
to 2.06V (CY7B9910) or VCC/2 (CY7B9920).
18.
tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920.
19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
4
CY7B9910
CY7B9920
[7]
Switching Characteristics Over the Operating Range (continued)
CY7B9910–7
CY7B9920–7
Parameter
Description
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
[9, 10]
f
Operating Clock
FS = LOW
15
30
15
30
MHz
NOM
Frequency in MHz
[9, 10]
FS = MID
25
40
50
80
25
40
50
[9, 10, 11]
[12]
FS = HIGH
80
t
t
t
t
t
t
t
t
t
t
t
REF Pulse Width HIGH
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
RPWH
RPWL
SKEW
DEV
REF Pulse Width LOW
[13, 14]
Zero Output Skew (All Outputs)
0.3
0.75
1.5
0.3
0.75
1.5
[8, 15]
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
–0.7
–1.2
0.15
0.15
0.0
0.0
1.5
1.5
+0.7
+1.2
2.5
–0.7
–1.2
0.5
0.0
0.0
3.0
3.0
+0.7
+1.2
5.0
PD
[16]
Output Duty Cycle Variation
ODCV
ORISE
OFALL
LOCK
JR
[17, 18]
Output Rise Time
[17, 18]
Output Fall Time
2.5
0.5
5.0
[19]
PLL Lock Time
0.5
0.5
[8]
Cycle-to-Cycle Output Peak to Peak
Jitter
200
25
200
25
[8]
RMS
JR
AC Timing Diagrams
t
t
RPWL
REF
t
RPWH
REF
t
PD
t
ODCV
t
ODCV
FB
Q
t
JR
t
SKEW
t
SKEW
OTHERQ
7B9910–8
5
CY7B9910
CY7B9920
REF
LOAD
Z
Z
0
FB
SYSTEM
CLOCK
REF
FS
LOAD
LOAD
Q0
Q1
0
Q2
Q3
Q4
Q5
Z
0
Q6
Q7
LOAD
TEST
Z
0
7B9910–9
Figure 1. Zero-Skew and/or Zero-Delay Clock Driver
nated transmission lines (with impedances as low as 50
ohms), allows efficient printed circuit board design.
Operational Mode Descriptions
Figure 1 shows the device configured as a zero-skew clock
buffer. In this mode the 7B9910/9920 can be used as the basis
for a low-skew clock distribution tree. The outputs are aligned
and may each drive a terminated transmission line to an inde-
pendent load. The FB input can be tied to any output and the
operating frequency range is selected with the FS pin. The
low-skew specification, coupled with the ability to drive termi-
Figure 2 shows the CY7B9910/9920 connected in series to
construct a zero-skew clock distribution tree between boards.
Cascaded clock buffers will accumulate low-frequency jitter
because of the non-ideal filtering characteristics of the PLL
filter. It is not recommended that more than two clock buffers
be connected in series.
LOAD
REF
Z
0
FB
LOAD
LOAD
SYSTEM
CLOCK
REF
FS
Z
0
Q0
Q1
Q2
Q3
Q4
Q5
Z
0
Q6
Q7
FB
REF
FS
TEST
LOAD
Q0
Q1
Z
0
Q2
Q3
Q4
Q5
LOAD
Q6
Q7
TEST
7B9910–10
Figure 2. Board-to-Board Clock Distribution
6
CY7B9910
CY7B9920
Ordering Information
Accuracy
Package
Name
Operating
(ps)
Ordering Code
Package Type
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
24-Lead Small Outline IC
Range
250
CY7B9910–2SC
CY7B9920–2SC
CY7B9910–5SC
CY7B9910–5SI
CY7B9920–5SC
CY7B9920–5SI
CY7B9910–7SC
CY7B9910–7SI
CY7B9920–7SC
CY7B9920–7SI
S13
S13
S13
S13
S13
S13
S13
S13
S13
S13
Commercial
500
750
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38–00437–B
Package Diagram
24-Lead (300-Mil) Molded SOIC S13
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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