CY62168DV30LL-70BVXI [CYPRESS]
16-Mbit (2048K x 8) Static RAM; 16兆位（ 2048K ×8 ）静态RAM
| 型号： | CY62168DV30LL-70BVXI |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (2048K x 8) Static RAM |
| 文件： | 总9页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62168DV30
MoBL
16-Mbit (2048K x 8) Static RAM
addresses are not toggling. The device can be put into standby
mode reducing power consumption by more than 99% when
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)
LOW. The input/output pins (I/O0 through I/O7) are placed in
a high-impedance state when: deselected Chip Enable 1
(CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled
(OE HIGH), or during a write operation (Chip Enable 1 (CE1)
LOW and Chip Enable 2 (CE2) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address
pins(A0 through A20).
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip
Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
Features
• Very high speed: 55 ns and 70 ns
— Wide voltage range: 2.20V – 3.60V
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = fmax
• Ultra-low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Functional Description[1]
The CY62168DV30 is a high-performance CMOS static RAMs
organized as 2048Kbit words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 90% when
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
Data in Drivers
A0
A1
A2
A3
A4
1
2
A
A5
A6
3
4
5
2048K x 8
A7
ARRAY
A98
A10
A11
A12
6
7
POWER
DOWN
COLUMN
CE
CE
1
2
DECODER
I/O
WE
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05329 Rev. *D
Revised September 14, 2004
CY62168DV30
MoBL
Pin Configuration[2]
FBGA
Top View
1
2
4
3
5
6
DNU
DNU
A
2
A
A
OE
CE2
0
1
A
B
C
A
DNU
DNU
DNU
A
CE1
4
3
A
A
I/O
I/O
DNU
5
6
0
4
V
A
V
CC
I/O
A17
SS
D
E
F
I/O1
7
5
V
DNU
A
16
I/O
V
CC
SS
I/O
2
6
A
A
15
I/O
I/O
DNU
DNU
WE
14
3
7
A
A
G
H
DNU
A18
DNU
A19
13
12
A
A
A
A
10
9
11
8
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = fmax
VCC Range (V)
Typ.[3]
f = 1 MHz
Standby ISB2(µA)
Speed
Product
Min.
Max.
3.6
(ns)
55
Typ.[3]
Max.
4
Typ.[3]
Max.
30
Typ.[3]
Max.
CY62168DV30L
2.2
3.0
2
15
12
15
12
2.5
30
70
55
70
25
CY62168DV30LL
2.2
3.0
3.6
2
4
30
2.5
22
25
Notes:
2. DNU pins have to be left floating or tied to V to ensure proper application.
SS
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
CC
, T = 25°C.
A
CC(typ.)
Document #: 38-05329 Rev. *D
Page 2 of 9
CY62168DV30
MoBL
DC Input Voltage[4, 5]......................–0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
Static Discharge Voltage...........................................> 2001V
lines, not tested.)
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential........................................ –0.3V to VCC(max) + 0.3V
[7]
Range
Temperature (TA) [6]
VCC
DC Voltage Applied to Outputs
Industrial
–40°C to +85°C
2.2V – 3.6V
in High-Z State[4, 5]......................... –0.3V to VCC(max) + 0.3V
DC Electrical Characteristics (Over the Operating Range)
CY62168DV30-55
CY62168DV30-70
Parameter
Description
Test Conditions
Min. Typ.[3] Max. Min. Typ.[3] Max. Unit
2.2 < VCC < 2.7 IOH = −0.1 mA 2.0
2.7 < VCC < 3.6 IOH = −1.0 mA 2.4
2.2 < VCC < 2.7 IOL = 0.1 mA
2.0
2.4
V
V
VOH
Output HIGH Voltage
0.4
0.4
0.4
0.4
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
2.7 < VCC < 3.6 IOH = 2.1 mA
2.2 < VCC < 2.7
1.8
2.2
VCC
+
+
1.8
2.2
VCC
+
+
0.3
0.3
V
V
2.7 < VCC < 3.6
VCC
0.3
VCC
0.3
2.2 < VCC < 2.7
2.7 < VCC < 3.6
Input Leakage Current GND < VI < VCC
–0.3
–0.3
–1
0.6
0.8
+1
+1
30
4
–0.3
–0.3
–1
0.6
0.8
+1
+1
25
4
IIX
IOZ
µA
µA
mA
Output Leakage Current GND < VO < VCC, Output disabled –1
–1
VCC Operating Supply
f = fMAX = 1/tRC Vcc = 3.6V,
OUT = 0mA,
CMOS level
15
2
12
2
ICC
Current
I
f = 1 MHz
CE1 > VCC − 0.2V, CE2 <
Automatic CE
L
2.5
2.5
30
22
2.5
2.5
30
22
µA
µA
Power-down Current − 0.2V, VIN > VCC − 0.2V, VIN
ISB1
CMOS Inputs
< 0.2V, f = fMAX (Address
and Data Only), f = 0 (OE,
WE, )
LL
Automatic CE
CE1 > VCC − 0.2V, CE2 <
L
LL
2.5
2.5
30
22
2.5
2.5
30
22
ISB2
Power-down Current − 0.2V, VIN > VCC − 0.2V or
CMOS Inputs
VIN < 0.2V, f = 0, VCC=3.6V
Thermal Resistance
Parameter
ΘJA
Description
Test Conditions
Still Air, soldered on a 3 x 4.5 inch, four-layer printed
BGA
55
Unit
°C/W
Thermal Resistance[8]
(Junction to Ambient)
circuit board
ΘJC
Thermal Resistance[8]
(Junction to Case)
16
°C/W
Notes:
4.V
= –0.2V for pulse durations less than 20 ns.
IL(min)
IH(max)
5.V
= V + 0.75V for pulse durations less than 20 ns.
CC
6.T is the “Instant-On” case temperature.
A
7.Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 100 µs wait time after V stabilization..
cc
cc
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05329 Rev. *D
Page 3 of 9
CY62168DV30
MoBL
e
Capacitance[8]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
8
10
Unit
pF
pF
CIN
COUT
TA = 25°C, f = 1 MHz,
V
CC = VCC(typ.)
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
OUTPUT
VCC
GND
90%
10%
10%
50 pF
R2
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50V
3.0V
1103
1554
645
Unit
Ω
R1
R2
RTH
VTH
16600
15400
8000
1.2
Ω
Ω
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current VCC = 1.5V
Conditions
Min.
1.5
Typ.[3]
Max.
3.6
15
Unit
V
µA
µA
L
CE1 > VCC − 0.2V or CE2 <0.2V
10
LL
V
IN > VCC − 0.2V or VIN < 0.2V
[8]
tCDR
Chip Deselect to Data
Retention Time
Operation Recovery
0
ns
ns
[9]
tR
tRC
Time
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
VCC(min)
V
V
CC
VCC(min)
DR
t
t
R
CDR
CE1
or
CE
2
Note:
9. Full Device AC operation requires linear V ramp from V to V
> 100 µs or stable at V > 100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05329 Rev. *D
Page 4 of 9
CY62168DV30
MoBL
Switching Characteristics Over the Operating Range [10]
55 ns
70 ns
Parameter
Read Cycle
tRC
Description
Min.
55
Max.
Min.
70
Max.
Unit
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
10
10
55
25
70
35
OE LOW to Low Z[11]
5
10
0
5
10
0
OE HIGH to High Z[11, 12]
20
20
55
25
25
70
CE1 LOW and CE2 HIGH to Low Z[11]
CE1 HIGH or CE2 LOW to High Z[11, 12]
CE1 LOW and CE2 HIGH to Power-Up
CE1 HIGH or CE2 LOW to Power-Down
tPD
Write Cycle[13]
tWC
Write Cycle Time
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[11, 12]
WE HIGH to Low Z[11]
0
0
40
25
0
45
30
0
20
25
10
10
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of V
/2, input
CC(typ.)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
OL OH
CC(typ.)
11. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
12. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
13. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05329 Rev. *D
Page 5 of 9
CY62168DV30
MoBL
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
50%
50%
SUPPLY
ISB
CURRENT
Write Cycle No. 1(WE Controlled) [13, 17, 18]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
See Note [19]
VALID DATA
DATA I/O
t
HZOE
Notes:
14. Device is continuously selected. OE, CE = V , CE = V .
IH
1
IL
2
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
17. Data I/O is high impedance if OE = V
.
IH
18. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.
1
2
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05329 Rev. *D
Page 6 of 9
CY62168DV30
MoBL
Switching Waveforms (continued)
Write Cycle No. 2(CE1 or CE2 Controlled)[13, 17, 18]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
t
HA
AW
t
PWE
WE
OE
t
t
HD
SD
DATA I/O
VALID DATA
Write Cycle No. 3 (WE Controlled, OE LOW) [19]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
See Note [19]
DATAI/O
VALID DATA
t
t
LZWE
HZWE
Truth Table
CE1
H
X
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
OE
X
X
L
H
X
Inputs/Outputs
High Z
High Z
Data Out (I/O0-I/O7)
High Z
Mode
Power
Standby (ISB)
Deselect/Power-down
Deselect/Power-down
Read
Output Disabled
Write
Standby (ISB
)
Active (ICC)
Active (Icc)
Active (Icc)
L
L
Data in (I/O0-I/O7)
Document #: 38-05329 Rev. *D
Page 7 of 9
CY62168DV30
MoBL
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
55
CY62168DV30L-55BVXI
CY62168DV30LL-55BVXI
CY62168DV30L-70BVXI
CY62168DV30LL-70BVXI
CY62168DV30L-55BVXI
CY62168DV30LL-55BVXI
CY62168DV30L-70BVXI
CY62168DV30LL-70BVXI
BV48B
BV48B
BV48B
BV48B
BV48B
BV48B
BV48B
BV48B
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm)
Industrial
Industrial
Industrial
Industrial
70
55
70
Package Diagrams
48-Lead VFBGA (8 x 9.5 x 1 mm) BV48B
51-85178-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are trademarks of their respective holders.
Document #: 38-05329 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62168DV30
MoBL
Document History Page
Document Title: CY62168DV30 MoBL® 16-Mbit (2048K x 8) Static RAM
Document Number: 38-05329
Issue
Date
09/30/02
Orig. of
Change
GUG
REV.
**
ECN NO.
118409
Description of Change
New Data Sheet
*A
123693
02/05/03
DPM
Changed Advance Information to Preliminary
Added package diagram
*B
*C
*D
126556
132869
272589
04/24/03
01/15/04
See ECN
DPM
XRJ
PCI
Minor change: Change sunset owner from DPM to HRT
Changed Preliminary to Final
Updated Final data sheet and added Pb-free package.
Document #: 38-05329 Rev. *D
Page 9 of 9
相关型号：
CY62168G18-55BVXI
Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
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