CY62168EV30 [CYPRESS]
16-Mbit (2M x 8) Static RAM; 16兆位（ 2M ×8 ）静态RAM
| 型号： | CY62168EV30 |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (2M x 8) Static RAM |
| 文件： | 总10页 (文件大小：930K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62168EV30 MoBL®
16-Mbit (2M x 8) Static RAM
toggling. Placing the device into standby mode reduces power
consumption by more than 99% when deselected (Chip
Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW). The input
and output pins (IO0 through IO7) are placed in a high
impedance state when: the device is deselected (Chip Enable
1 (CE1) HIGH or Chip Enable 2 (CE2) LOW), outputs are
disabled (OE HIGH), or a write operation is in progress (Chip
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE
LOW).
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V – 3.60V
• Ultra low standby power
— Typical standby current: 1.5 µA
— Maximum standby current: 12 µA
• Ultra low active power
Write to the device by taking Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input
LOW. Data on the eight IO pins (IO0 through IO7) is then
written into the location specified on the address pins (A0
through A20).
— Typical active current: 2.2 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power down when deselected
• CMOS for optimum speed/power
Read from the device by taking Chip Enable 1 (CE1) and
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the IO pins.
• Offered in Pb-free 48-ball FBGA package. For Pb-free
48-pin TSOP I package, refer to CY62167EV30 data sheet.
Functional Description[1]
The CY62168EV30 is a high performance CMOS static RAM
organized as 2M words by 8 bits. This device features
advanced circuit design to provide an ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 90% when addresses are not
The eight input and output pins (IO0 through IO7) are placed
in a high impedance state when the device is deselected (CE1
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or
a write operation is in progress (CE1 LOW and CE2 HIGH and
WE LOW). See the “Truth Table” on page 8 for a complete
description of read and write modes.
Logic Block Diagram
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO
0
DATA IN DRIVERS
IO
1
IO
2
2M x 8
IO
3
IO
IO
IO
IO
ARRAY
4
5
6
7
A
A
A
A
9
10
11
12
CE
CE
1
2
POWER
DOWN
COLUMN DECODER
WE
OE
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 001-07721 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 07, 2007
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CY62168EV30 MoBL®
Pin Configuration [2]
48-Ball FBGA Top View
1
2
4
A1
A4
A6
A7
3
A0
5
6
A2
CE2
NC
IO4
NC
NC
IO0
OE
NC
NC
IO1
IO2
A
B
C
A3
CE1
NC
IO5
A5
V
CC
V
A17
NC
SS
D
E
F
V
SS
A16 IO6
V
CC
A14 A15
A12 A13
IO3
NC
A18
NC
IO7
NC
NC
A20
A8
G
H
WE
A9
A10
A11 A19
Product Portfolio
Power Dissipation
f = fmax
VCC Range (V)
Operating ICC (mA)
Speed
(ns)
Product
Standby ISB2 (µA)
f = 1 MHz
Min
2.2
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
CY62168EV30LL
3.0
3.6
45
2.2
4.0
25
30
1.5
12
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V (typ), T = 25°C.
CC
CC
A
Document #: 001-07721 Rev. *B
Page 2 of 10
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CY62168EV30 MoBL®
DC Input Voltage[4, 5]....................–0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Static Discharge Voltage...........................................> 2001V
(MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to +150°C
Latch up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground
Potential....................................... –0.3V to VCC(max) + 0.3V
Ambient
[7]
Range
VCC
Temperature (TA)[6]
DC Voltage Applied to Outputs
Industrial
–40°C to +85°C
2.2V – 3.6V
in High-Z State[4, 5]....................... –0.3V to VCC(max) + 0.3V
DC Electrical Characteristics
Over the Operating Range
CY62168EV30-45
Parameter
Description
Test Conditions
Unit
Min
2.0
2.4
Typ[3]
Max
VOH
Output HIGH Voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
GND < VI < VCC
IOH = −0.1 mA
IOH = −1.0 mA
IOL = 0.1 mA
IOH = 2.1 mA
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
0.4
V
V
V
1.8
2.2
–0.3
–0.3
–1
VCC + 0.3
VCC + 0.3
0.6
0.8
IIX
Input Leakage Current
Output Leakage Current
+1
µA
µA
IOZ
ICC
GND < VO < VCC, Output disabled
–1
+1
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.6V,
OUT = 0 mA,
CMOS level
25
30
mA
I
2.2
4.0
ISB1
Automatic CE Power Down CE1 > VCC − 0.2V, CE2 < 0.2V,
1.5
12
12
µA
µA
Current — CMOS Inputs
VIN > VCC − 0.2V, VIN < 0.2V,
f = fMAX (Address and Data Only),
f = 0 (OE, WE)
[8]
ISB2
Automatic CE Power Down CE1 > VCC − 0.2V, CE2 < 0.2V,
1.5
Current— CMOS Inputs
VIN > VCC − 0.2V or VIN < 0.2V, f = 0,
CC = 3.6V
V
Capacitance[9]
Parameter
Description
Test Conditions
Max
8
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
CC = VCC(typ)
pF
pF
V
COUT
10
Notes
4. V (min) = –0.2V for pulse durations less than 20 ns.
IL
5.
6.
V (max) = V + 0.75V for pulse durations less than 20 ns.
IH CC
T
is the “Instant-On” case temperature.
A
7. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 100 µs wait time after V stabilization.
CC
CC
8. Only chip enables (CE and CE ) must be at CMOS level to meet the I / I spec. Other inputs can be left floating.
1
2
SB2 CCDR
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-07721 Rev. *B
Page 3 of 10
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CY62168EV30 MoBL®
Thermal Resistance[9]
Parameter
Description
Test Conditions
BGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit
board
55
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
16
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC
90%
10%
OUTPUT
90%
10%
GND
30 pF
R2
Rise Time: 1 V/ns
Fall time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5V (2.2V to 2.7V)
3.0V (2.7V to 3.6V)
Unit
Ω
R1
R2
16600
15400
8000
1.2
1103
1554
645
Ω
RTH
VTH
Ω
1.75
V
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
Conditions
Min
Typ[3]
Max
3.6
10
Unit
V
VCC for Data Retention
Data Retention Current
1.5
[8]
ICCDR
VCC = 1.5V
CE1 > VCC − 0.2V or CE2 < 0.2V
µA
VIN > VCC − 0.2V or VIN < 0.2V
[9]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[10]
tR
Operation Recovery Time
tRC
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
VCC(min)
V
V
CC
VCC(min)
DR
t
t
R
CDR
CE1
or
CE
2
Note
10. Full Device AC operation requires linear V ramp from V to V (min) > 100 µs or stable at V (min) > 100 µs.
CC
DR
CC
CC
Document #: 001-07721 Rev. *B
Page 4 of 10
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CY62168EV30 MoBL®
Switching Characteristics
Over the Operating Range [11]
45 ns
Unit
Parameter
Description
Min
45
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
10
45
22
OE LOW to Low Z[12]
OE HIGH to High Z[12, 13]
5
10
0
18
18
45
CE1 LOW and CE2 HIGH to Low Z[12]
CE1 HIGH or CE2 LOW to High Z[12, 13]
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH or CE2 LOW to Power Down
tPD
Write Cycle[14]
tWC
Write Cycle Time
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
35
25
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High Z[12, 13]
WE HIGH to Low Z[12]
tHD
tHZWE
tLZWE
18
10
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V (typ)/2, input
CC
pulse levels of 0 to V (typ), and output loading of the specified I /I as shown in “AC Test Loads and Waveforms” on page 4.
CC
OL OH
12. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
13. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
14. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 001-07721 Rev. *B
Page 5 of 10
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CY62168EV30 MoBL®
Switching Waveforms
Figure 1 shows address transition controlled read cycle waveforms.[15, 16]
Figure 1. Read Cycle No. 1
t
RC
ADDRESS
DATA OUT
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
Figure 2 shows OE controlled read cycle waveforms.[16, 17]
Figure 2. Read Cycle No. 2
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
OE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
15. The device is continuously selected. OE, CE = V , and CE = V .
IH
1
IL
2
16. WE is HIGH for read cycle.
17. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
Document #: 001-07721 Rev. *B
Page 6 of 10
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CY62168EV30 MoBL®
Switching Waveforms (continued)
Figure 3 shows WE controlled write cycle waveforms.[14, 18, 19]
Figure 3. Write Cycle No. 1
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
OE
tHD
tSD
NOTE 20
DATA IO
VALID DATA
tHZOE
Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[14, 18, 19]
Figure 4. Write Cycle No. 2
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
OE
tHD
tSD
VALID DATA
DATA IO
NOTE 20
tHZOE
Notes
18. Data IO is high impedance if OE = V
.
IH
19. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
20. During this period the IOs are in output state. Do not apply input signals.
Document #: 001-07721 Rev. *B
Page 7 of 10
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CY62168EV30 MoBL®
Switching Waveforms (continued)
Figure 5 shows WE controlled, OE LOW write cycle waveforms.[19]
Figure 5. Write Cycle No. 3
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tSD
tHD
NOTE 20
DATA IO
VALID DATA
tLZWE
tHZWE
Truth Table
CE1
H
CE2
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Power
X
L
Deselect/Power Down
Deselect/Power Down
Read
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
X
X
High Z
)
L
H
H
H
H
L
Data Out (IO0-IO7)
High Z
)
L
H
H
X
Output Disabled
Write
)
L
L
Data in (IO0-IO7)
)
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
CY62168EV30LL-45BVXI
Package Type
(ns)
45
51-85150 48-ball Fine Pitch BGA (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of these parts.
Document #: 001-07721 Rev. *B
Page 8 of 10
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CY62168EV30 MoBL®
Package Diagrams
Figure 6. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85150-*D
Document #: 001-07721 Rev. *B
Page 9 of 10
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their
respective holders.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and
foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only
in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except
as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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CY62168EV30 MoBL®
Document History Page
Document Title: CY62168EV30 MoBL® 16-Mbit (2M x 8) Static RAM
Document Number: 001-07721
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
457686
464509
See ECN
See ECN
NXR
New Data Sheet
*A
NXR
Removed TSOP I package; Added reference to CY62167EV30 TSOP I
package which can be used as a 2M x 8 SRAM
Changed the ISB2(Typ) value from 1.3 µA to 1.5 µA
Changed the ICC(Typ) value from 2 mA to 2.2 mA for f=1MHz Test condition
Changed the ICC(Typ) value from 15 mA to 22 mA and ICC(Max) value from
40 mA to 25 mA for f=1MHz Test condition
Changed the ICCDR(Max) value from 8.5 µA to 8 µA
*B
1138883
See ECN
VKN
Converted from preliminary to final
Changed ICC(max) spec from 2.8 mA to 4.0 mA for f=1MHz
Changed ICC(typ) spec from 22 mA to 25 mA for f=fmax
Changed ICC(max) spec from 25 mA to 30 mA for f=fmax
Added footnote# 8 related to ISB2 and ICCDR
Changed ISB1 and ISB2 spec from 8.5 µA to 12 µA
Changed ICCDR spec from 8 µA to 10 µA
Document #: 001-07721 Rev. *B
Page 10 of 10
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