CY62168G18-55BVXI [CYPRESS]
Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48;
| 型号： | CY62168G18-55BVXI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62168G/CY62168GE MoBL®
16-Mbit (2M words × 8 bits) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (2M words
× 8 bits) Static RAM with Error-Correcting Code (ECC)
Devices with a single chip enable input are accessed by
asserting the chip enable input (CE) LOW. Dual chip enable
devices are accessed by asserting both chip enable inputs – CE1
as LOW and CE2 as HIGH.
Features
■ Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 16 A
Write to the device by taking Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written
■ High speed: 45 ns/55 ns
into the location specified on the address pins (A0 through A20).
■ Embedded error-correcting code (ECC) for single-bit error
correction
Read from the device by taking Chip Enable 1 (CE1) and
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while
forcing Write Enable (WE) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
■ Widevoltage range: 1.65 V to2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■ 1.0 V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Available in Pb-free 48-ball VFBGA package
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table – CY62168G/CY62168GE on page
14 for a complete description of read and write modes.
Functional Description
CY62168G and CY62168GE are high-performance CMOS
low-power (MoBL) SRAM devices with embedded ECC. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62168GE device includes an
error indication pin that signals a single-bit error-detection and
correction event during a read cycle.
On CY62168GE devices, the detection and correction of a single
bit error in the accessed location is indicated by the assertion of
the ERR output (ERR = HIGH) [1]
.
The CY62168G and CY62168GE devices are available in a
Pb-free 48-pin VFBGA package. The logic block diagrams are
on page 2.
For a complete list of related resources, click here.
Product Portfolio
Power Dissipation
Features and Options
(see Pin
Operating ICC, (mA)
Speed
Product
Range
VCC Range (V)
Standby, ISB2 (µA)
(ns)
Configurations
section)
f = fmax
Typ[2]
Max
32
Typ[2]
7
Max
26
CY62168G(E)18 Single or dual Chip
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
55
45
29
29
Enables
CY62168G(E)30
36
5.5
16
Optional ERR pin
CY62168G(E)
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V
CC
CC
CC
(for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.
CC
CC
CC
A
Cypress Semiconductor Corporation
Document Number: 001-84771 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 22, 2017
CY62168G/CY62168GE MoBL®
Logic Block Diagram – CY62168G
DATAIN
DRIVERS
ECC ENCODER
A0
A1
A2
A3
I/O0‐I/O7
2M x 8
RAM ARRAY
A4
A5
A6
A7
A8
A9
COLUMN
DECODER
WE
OE
CE2
CE1
Logic Block Diagram – CY62168GE
DATAIN
DRIVERS
ECC ENCODER
A0
A1
A2
A3
I/O0‐I/O7
2M x 8
RAM ARRAY
A4
A5
A6
A7
A8
A9
ERR
COLUMN
DECODER
WE
OE
CE2
CE1
Document Number: 001-84771 Rev. *I
Page 2 of 19
CY62168G/CY62168GE MoBL®
Contents
Pin Configurations ...........................................................4
Maximum Ratings .............................................................5
Operating Range ...............................................................5
DC Electrical Characteristics ..........................................5
Capacitance ...................................................................... 7
Thermal Resistance ..........................................................7
AC Test Loads and Waveforms .......................................7
Data Retention Characteristics .......................................8
Data Retention Waveform ................................................8
Switching Characteristics ................................................9
Switching Waveforms ....................................................10
Truth Table – CY62168G/CY62168GE ...........................14
ERR Output – CY62168GE .............................................14
Ordering Information ......................................................15
Ordering Code Definitions .........................................15
Package Diagrams ..........................................................16
Acronyms ........................................................................17
Document Conventions .................................................17
Units of Measure .......................................................17
Document History Page .................................................18
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC® Solutions ......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 001-84771 Rev. *I
Page 3 of 19
CY62168G/CY62168GE MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) pinout[3]
CY62168G
1
2
3
4
5
6
A0
A2
A1
CE2
A
B
C
NC
NC
OE
NC
A3
A5
A4
A6
NC
I/O4
VCC
CE1
NC
I/O0 NC
I/O1
VSS
A7 I/O5
D
E
F
A17
A18
VCC
I/O3 NC
A16 I/O6 VSS
I/O2
A14
A15
NC
I/O7
NC
A12 A13
A9
NC
A8
NC
A19
WE
G
H
A10 A11
A20
Figure 2. 48-ball VFBGA (6 × 8 × 1 mm) pinout[3, 4]
CY62168GE
Note
3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
4. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-84771 Rev. *I
Page 4 of 19
CY62168G/CY62168GE MoBL®
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch up current ......................................................>140 mA
Storage temperature ............................... –65 °C to + 150 °C
Operating Range
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
[6]
Grade
Ambient Temperature
VCC
Supply voltage to ground potential ...................–0.5 V to 6 V
Industrial
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC voltage applied to outputs
in High Z state[5] .................................. –0.5 V to VCC + 0.5 V
DC input voltage[5] .............................. –0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
45 ns/55 ns
Parameter
Description
Test Conditions
Unit
Min
1.4
Typ [7]
Max
VOH
Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V
V
2.0
–
2.4
–
–
V
2.4
V
VCC – 0.4 [8]
–
V
VOL
VIH
VIL
Output LOW
voltage
–
0.2
V
–
0.4
V
–
0.4
V
–
0.4
V
Input HIGH
voltage
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
–
1.4
VCC + 0.2
VCC + 0.3
VCC + 0.3
VCC + 0.5
0.4
V
–
1.8
V
–
2.0
V
–
2.2
V
Input LOW
voltage[9]
–
–0.2
–0.3
–0.3
–0.5
–1.0
–1.0
V
–
0.6
V
–
0.8
V
–
0.8
V
IIX
Input leakage current
Output leakage current
GND < VIN < VCC
+1.0
+1.0
A
A
IOZ
GND < VOUT < VCC, Output disabled
Notes
5.
V
= –2.0 V and V
= V + 2 V for pulse durations of less than 20 ns.
IH(max) CC
IL(min)
6. Full Device AC operation assumes a 100 µs ramp time from 0 to V
and 200 µs wait time after V stabilization.
CC(min)
CC
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V
CC
CC
CC
(for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.
CC
CC
CC
A
8. This parameter is guaranteed by design and is not tested.
9. = –2.0 V and V = V + 2 V for pulse durations of less than 20 ns.
V
IL(min)
IH(max)
CC
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Page 5 of 19
CY62168G/CY62168GE MoBL®
DC Electrical Characteristics (continued)
Over the operating range of –40 C to 85 C
45 ns/55 ns
Unit
Parameter
Description
Test Conditions
Min
–
Typ [7]
Max
36.0
32.0
ICC
VCC operating supply current
VCC = Max,
IOUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
29.0
mA
mA
mA
f = 18.18 MHz
(55 ns)
–
29.0
f = 1 MHz
–
–
7.0
5.5
9.0
mA
[10]
[10]
ISB1
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V,
16.0
A
CMOS inputs;
VIN > VCC – 0.2 V, VIN < 0.2 V,
VCC = 2.2 to 3.6 V and 4.5 to 5.5 V f = fmax (address and data only),
Automatic power down current –
–
7
26.0
A
f = 0 (OE, and WE), VCC = VCC(max)
CMOS inputs; VCC = 1.65 to 2.2 V
ISB2
Automatic power down current – CE1 > VCC – 0.2 V or 25 °C [11]
CMOS inputs;
VCC = 2.2 to 3.6 V and 4.5 to 5.5 V
–
–
–
–
5.5
6.3
6.5
8.0
A
A
A
A
CE2 < 0.2 V,
40 °C [11]
70 °C [11]
85 °C
VIN > VCC – 0.2 V or
VIN < 0.2 V,
8.4
12.0 [11]
12.0
16.0
f = 0, VCC = VCC(max)
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V,
CMOS inputs;
–
7.0
26.0
A
VCC = 1.65 to 2.2 V
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
10. Chip enables (CE and CE ) must be tied to CMOS levels to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
11. The I
limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
SB2
Document Number: 001-84771 Rev. *I
Page 6 of 19
CY62168G/CY62168GE MoBL®
Capacitance
Parameter [12]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [12]
Description
Test Conditions
48-ball VFBGA Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
31.50
°C/W
JC
Thermal resistance
(junction to case)
15.75
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
V
10%
R1
V
CC
OUTPUT
HIGH
90%
10%
90%
GND
Fall Time = 1 V/ns
R2
30 pF
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
1.8 V
13500
10800
6000
0.8
2.5 V
3.0 V
1103
1554
645
5.0 V
1800
990
Unit
R1
R2
16667
15385
8000
1.2
RTH
VTH
VHIGH
639
1.75
3.0
1.77
5.0
V
1.8
2.5
V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-84771 Rev. *I
Page 7 of 19
CY62168G/CY62168GE MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.0
–
Typ[13]
–
Max
–
Unit
V
[14, 15]
ICCDR
1.2 V < VCC < 2.2 V,
7.0
26.0
A
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
2.2 V < VCC < 3.6 V or 4.5 V < VCC < 5.5 V,
–
5.5
16.0
A
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
[16]
tCDR
Chip deselect to data retention
time
0
–
–
–
–
–
[16, 17]
tR
Operation recovery time
45/55
ns
Data Retention Waveform
Figure 4. Data Retention Waveform
D A T A R E T E N T IO N M O D E
V C C
V D R = 1 .0 V
V C C (m in )
tC D R
V C C (m in )
t R
C E 1
(o r )
C E 2
Notes
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V
CC
CC
CC
(for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.
CC
CC
CC
A
14. Chip enables (CE and CE ) must be tied to CMOS levels to meet the I / I / I spec. Other inputs can be left floating.
SB1 SB2 CCDR
1
2
15. I
is guaranteed only after device is first powered up to V
and brought down to V
.
CCDR
CC(min)
DR
16. These parameters are guaranteed by design.
17. Full device operation requires linear V ramp from V to V
> 100 s or stable at V
> 100 s.
CC
DR
CC(min)
CC(min)
Document Number: 001-84771 Rev. *I
Page 8 of 19
CY62168G/CY62168GE MoBL®
Switching Characteristics
45 ns
55 ns
Parameter [18, 19]
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
45.0
–
–
45.0
–
55.0
–
–
55.0
–
ns
ns
ns
tAA
Address to data valid / Address to ERR valid
tOHA
Data hold from address change / ERR hold from
address change
10.0
10.0
tACE
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR
valid
–
45.0
–
55.0
ns
tDOE
OE LOW to data valid / OE LOW to ERR valid
OE LOW to Low Z [19, 20]
OE HIGH to High Z [19, 20, 21]
CE1 LOW and CE2 HIGH to Low Z [19, 20]
CE1 HIGH and CE2 LOW to High Z [19, 20, 21]
CE1 LOW and CE2 HIGH to power-up
CE1 HIGH and CE2 LOW to power-down
–
5.0
–
22.0
–
–
5.0
–
25.0
–
ns
ns
ns
ns
ns
ns
ns
tLZOE
tHZOE
tLZCE
tHZCE
18.0
–
18.0
–
10.0
–
10.0
–
18.0
–
18.0
–
[22]
tPU
0
0
[22]
tPD
–
45.0
–
55.0
Write Cycle[23, 24]
tWC
tSCE
tAW
Write cycle time
45.0
35.0
35.0
0
–
–
55.0
40.0
40.0
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW and CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
–
tHA
–
–
tSA
0
–
0
–
tPWE
tSD
35.0
25.0
0
–
40.0
25.0
0
–
Data setup to write end
Data hold from write end
WE LOW to High Z [19, 21, 20]
WE HIGH to Low Z [19, 20]
–
–
tHD
–
–
tHZWE
tLZWE
–
18.0
–
–
20.0
–
10.0
10.0
Notes
18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V > 3 V) and V /2 (for V < 3 V), and input pulse levels
CC
CC
CC
of 0 to 3 V (for V > 3 V) and 0 to V (for V < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified
CC
CC
CC
otherwise.
19. At any temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
20. Tested initially and after any design or process changes that may affect these parameters.
21. t , t , and t transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
22. These parameters are guaranteed by design and are not tested.
23. The internal write time of the memory is defined by the overlap of WE = V , CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
IL
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
24. The minimum write cycle pulse width for write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of t
and t
SD.
HZWE
Document Number: 001-84771 Rev. *I
Page 9 of 19
CY62168G/CY62168GE MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY62168G (Address Transition Controlled)[25, 26]
tRC
ADDRESS
DATA I/O
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 6. Read Cycle No. 1 of CY62168GE (Address Transition Controlled)[25, 26]
tRC
ADDRESS
tAA
tOHA
DATA I/O
ERR
PREVIOUS DATAOUT VALID
DATAOUT VALID
ERR VALID
tAA
tOHA
PREVIOUS ERR VALID
Notes
25. The device is continuously selected. OE = V , CE = V .
IL
IL
26. WE is HIGH for read cycle.
Document Number: 001-84771 Rev. *I
Page 10 of 19
CY62168G/CY62168GE MoBL®
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled)[27, 28, 29]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
tLZCE
tPU
DATA I/O
DATAOUT VALID
VCC
SUPPLY
CURRENT
ISB
Notes
27. WE is HIGH for read cycle.
28. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
29. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-84771 Rev. *I
Page 11 of 19
CY62168G/CY62168GE MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled)[30, 31, 32]
tW
C
A D D R E S S
tS C E
C E
tA W
tS A
tH A
tP W
E
W E
O E
tH Z O
tH D
E
tS D
Note 33
D A T A I/O
D A T A IN V A L ID
Notes
30. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
31. The internal write time of the memory is defined by the overlap of WE = V , CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
IL
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
32. Data I/O is in the high-impedance state if CE = V , or OE = V
.
IH
IH
33. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-84771 Rev. *I
Page 12 of 19
CY62168G/CY62168GE MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (WE Controlled, OE Low)[34, 35, 36, 37]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tLZWE
tSD
t
HZWE
tHD
Note 38
DATA I/O
DATA VALID
IN
Figure 10. Write Cycle No. 3 (CE Controlled)[34, 35, 36]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
OE
tHZOE
tHD
tSD
Note 38
DATA I/O
DATA VALID
IN
Notes
34. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
35. The internal write time of the memory is defined by the overlap of WE = V , CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
IL
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
36. Data I/O is in high impedance state if CE = V , or OE = V
.
IH
IH
37. The minimum write cycle pulse width should be equal to the sum of the t
38. During this period I/O are in the output state. Do not apply input signals.
and t
.
HZWE
SD
Document Number: 001-84771 Rev. *I
Page 13 of 19
CY62168G/CY62168GE MoBL®
Truth Table – CY62168G/CY62168GE
CE1
CE2
X[39]
L
WE
X[39]
X[39]
H
OE
I/Os
Mode
Deselect / Power down
Deselect / Power down
Read
Power
H
X[39] High Z
X[39] High Z
Standby (ISB2
Standby (ISB2
)
)
X[39]
L
H
L
H
X
Data Out (I/O0–I/O7)
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
H
Output disabled
Write
L
H
L
Data In (I/O0–I/O7)
ERR Output – CY62168GE
Output[40]
Mode
0
1
Read Operation, no single-bit error in the stored data.
Read Operation, single-bit error detected and corrected.
Device deselected / Outputs disabled / Write Operation.
High Z
Note
39. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
40. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-84771 Rev. *I
Page 14 of 19
CY62168G/CY62168GE MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type (all Pb-free)
Ordering Code
45
CY62168GE30-45BVXI
CY62168GE30-45BVXIT
CY62168G30-45BVXI
CY62168G30-45BVXIT
CY62168G18-55BVXI
CY62168G18-55BVXIT
51-85150 48-ball VFBGA
Industrial
48-ball VFBGA, Tape and Reel
51-85150 48-ball VFBGA
48-ball VFBGA, Tape and Reel
51-85150 48-ball VFBGA
48-ball VFBGA, Tape and Reel
Industrial
Industrial
55
Ordering Code Definitions
G
X
X
XX BV
XX -
X
I
6
621
CY
8
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
BV = 48-ball VFBGA
Speed Grade: XX = 45 or 55
45 = 45 ns; 55 = 55 ns
Voltage Range: XX = 30 or 18
30 = 3 V typ; 18 = 1.8 V typ
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: G = 65 nm
Bus Width: 8 = × 8
Density: 6 = 16-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-84771 Rev. *I
Page 15 of 19
CY62168G/CY62168GE MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-84771 Rev. *I
Page 16 of 19
CY62168G/CY62168GE MoBL®
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CE
Chip Enable
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
°C
MHz
A
s
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
OE
Output Enable
SRAM
VFBGA
WE
Static Random Access Memory
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-84771 Rev. *I
Page 17 of 19
CY62168G/CY62168GE MoBL®
Document History Page
Document Title: CY62168G/CY62168GE MoBL®, 16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-84771
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*G
*H
4800984
5449003
VINI
VINI
07/31/2015 Changed status from Preliminary to Final.
11/03/2016 Updated Maximum Ratings:
Updated Note 5 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding
to Operating Range “2.7 V to 3.6 V”.
Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding
to Operating Range “2.2 V to 2.7 V”.
Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
*I
6003639 AESATP12 12/22/2017 Updated logo and copyright.
Document Number: 001-84771 Rev. *I
Page 18 of 19
CY62168G/CY62168GE MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-84771 Rev. *I
Revised December 22, 2017
Page 19 of 19
相关型号：
CY62168GE30-45BVXI
Standard SRAM, 2MX8, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
CY62168GE30-45BVXIT
16-Mbit (2M words à 8 bits) Static RAM with Error-Correcting Code (ECC)
CYPRESS
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