CY62177DV20_08 [CYPRESS]
32-Mbit (2M x 16) Static RAM; 32兆位（ 2M ×16 ）静态RAM
| 型号： | CY62177DV20_08 |
| 厂家： | 
CYPRESS |
| 描述： | 32-Mbit (2M x 16) Static RAM |
| 文件： | 总11页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62177DV20 MoBL2™
32-Mbit (2M x 16) Static RAM
by 99% when addresses are not toggling. The device can also
be put into standby mode when deselected (CE1 HIGH or CE2
LOW or both BHE and BLE are HIGH). The input and output pins
(IO0 through IO15) are placed in a high impedance state when:
the device is deselected (CE1HIGH or CE2 LOW); outputs are
disabled (OE HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH); when a write operation
is in progress (CE1 LOW, CE2 HIGH and WE LOW).
Features
■ Very high speed: 70 ns
■ Wide voltage range: 1.7V – 2.2V
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
❐ Typical active current: 12 mA at f = fMAX
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written
into the location specified on the address pins (A0 through A20).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the address
pins (A0 through A20).
■ Ultra low standby power
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in 48-ball VFBGA package
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO8 to IO15. See the Truth Table on page 9
for a complete description of read and write modes.
Functional Description
The CY62177DV20 is a high performance CMOS static RAM
organized as 2M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A10
A 9
A 8
A 7
A 6
A 5
A 4
2M × 16
RAM ARRAY
IO0–IO7
IO8–IO15
A 3
A 2
A 1
A 0
COLUMN DECODER
BHE
WE
CE2
CE2
CE
1
PowerDown
Circuit
CE
1
OE
BHE
BLE
BLE
Cypress Semiconductor Corporation
Document #: 001-44018 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 08, 2008
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CY62177DV20 MoBL2™
Pin Configuration
Figure 1. 48-Ball VFBGA (8 x 9.5 x 1.2 mm) Top View [1]
1
4
2
5
3
6
A
A
2
A
CE2
OE
BLE
0
1
A
B
C
A
A
4
IO
BHE
CE1 IO
3
0
2
8
A
A
6
IO
IO
1
IO
IO
5
9
10
Vcc
A
V
IO
IO
3
A17
D
E
F
SS
7
11
A
V
CC
Vss
IO
DNU
IO
IO
16
12
4
5
A
A
15
IO
IO
IO
14
13
14
6
A
A
G
H
IO
A19
WE
IO
13
12
15
7
A
A
A
A
A20
A18
10
9
11
8
Product Portfolio
Power Dissipation
Speed
(ns)
Product
VCC Range (V)
Operating ICC (mA)
f = 1 MHz f = fmax
Standby ISB2 (μA)
Min
Typ[2]
Max
2.2
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
CY62177DV20LL
1.7
1.8
70
2
4
12
25
5
50
Notes
1. DNU pins must be connected to V or left open.
SS
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
Document #: 001-44018 Rev. **
Page 2 of 11
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CY62177DV20 MoBL2™
DC Input Voltage[3, 4].......................–0.2V toVCC(max) + 0.2V
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................ –65°C to + 150°C
Latch up Current...................................................... >200 mA
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Operating Range
Supply Voltage to Ground
Potential .........................................–0.2V to VCC(max) + 0.2V
Ambient
Temperature
[5]
Device
Range
VCC
DC Voltage Applied to Outputs
CY62177DV20LL Industrial –40°C to +85°C 1.7V to 2.2V
in High Z State[3, 4]..........................–0.2V to VCC(max) + 0.2V
Electrical Characteristics
Over the Operating Range
70 ns
Min Typ[2]
Parameter
Description
Test Conditions
Unit
Max
VOH
VOL
VIH
VIL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOH = –0.1 mA
1.4
V
V
IOL = 0.1 mA
0.2
VCC = 1.7V to 2.2V
VCC = 1.7V to 2.2V
GND < VI < VCC
1.4
–0.2
–1
VCC + 0.2V
V
0.4
+1
+1
25
4
V
IIX
Input Leakage Current
Output Leakage Current
μA
μA
mA
mA
IOZ
ICC
GND < VO < VCC, Output Disabled
–1
VCC Operating Supply
Current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCC(max)
12
IOUT = 0 mA
CMOS levels
2
ISB1
Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V
5
100
μA
Current – CMOS Inputs
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax(Address and Data Only),
f = 0 (OE, WE, BHE and BLE), VCC = VCC(max)
ISB2
Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V,
5
50
μA
Current – CMOS Inputs
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
12
Unit
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
pF
pF
COUT
12
Notes
3. V (min) = –2.0V for pulse durations less than 20 ns.
IL
4.
V (max) = V + 0.75V for pulse durations less than 20 ns.
IH CC
5. Full Device AC operation is based on a 100 μs ramp time from 0 to V (min) and 100 μs wait time after V stabilization.
CC
CC
Document #: 001-44018 Rev. **
Page 3 of 11
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CY62177DV20 MoBL2™
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
VFBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
55
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
16
°C/W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
VCC
OUTPUT
VCC(typ)
GND
90%
10%
10%
R2
30 pF
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
1.8V
13500
10800
6000
0.80
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
V
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min
Typ[2]
Max
Unit
V
1.0
ICCDR
VCC = 1.0V, CE1 > VCC – 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
25
μA
[6]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[7]
tR
Operation Recovery Time
tRC
Data Retention Waveform
DATA RETENTION MODE
VCC(min)
tR
> 1.0 V
VDR
VCC(min)
tCDR
VCC
CE or
1
[8]
BHE.BLE
or
CE
2
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear V ramp from V to V (min) > 100 μs or stable at V (min) > 100 μs.
CC
DR
CC
CC
8. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 001-44018 Rev. **
Page 4 of 11
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CY62177DV20 MoBL2™
Switching Characteristics
Over the Operating Range [9]
70 ns
Parameter
Description
Unit
Min
70
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[10]
OE HIGH to High-Z[10, 11]
CE1 LOW and CE2 HIGH to Low-Z[10]
CE1 HIGH and CE2 LOW to High-Z[10, 11]
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH and CE2 LOW to Power Down
BLE/BHE LOW to Data Valid
10
70
35
5
10
0
25
25
tPD
70
70
tDBE
tLZBE
tHZBE
Write Cycle[12]
tWC
BLE/BHE LOW to Low-Z[10]
BLE/BHE HIGH to High-Z[10, 11]
5
25
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tBW
45
60
30
0
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z[10, 11]
WE HIGH to Low-Z[10]
tSD
tHD
tHZWE
tLZWE
25
10
Notes
9. Test conditions are based on signal transition time of 2 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ)
CC(typ)
specified I
.
OL
10. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
11. t
, t
, t
, and t
transitions are measured when the output enters a high impedance state.
HZOE HZCE HZBE
HZWE
12. The internal memory write time is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate a write and
1
IL
IL
2
IH
any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-44018 Rev. **
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CY62177DV20 MoBL2™
Switching Waveforms
Figure 2 shows address transition controlled read cycle waveforms.[13, 14]
Figure 2. Read Cycle No. 1
t
RC
ADDRESS
DATA OUT
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
Figure 3 shows OE controlled read cycle waveforms.[14, 15]
Figure 3. Read Cycle No. 2
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
OE
tDBE
tHZBE
tLZBE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
13. The device is continuously selected. OE, CE = V , BHE, BLE or both = V , and CE = V .
IH
1
IL
IL
2
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 001-44018 Rev. **
Page 6 of 11
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CY62177DV20 MoBL2™
Switching Waveforms (continued)
Figure 4 shows WE controlled write cycle waveforms.[12, 16, 17]
Figure 4. Write Cycle No. 1
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
NOTE 18
DATA IO
VALID DATA
tHZOE
Notes
16. Data IO is high impedance if OE = V
.
IH
17. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
18. During this period the IOs are in output state. Do not apply input signals.
Document #: 001-44018 Rev. **
Page 7 of 11
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CY62177DV20 MoBL2™
Switching Waveforms (continued)
Figure 5 shows CE1 or CE2 controlled write cycle waveforms.[12, 16, 17]
Figure 5. Write Cycle No. 2
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
VALID DATA
DATA IO
NOTE 18
tHZOE
Figure 6 shows WE controlled, OE LOW write cycle waveforms.[17]
Figure 6. Write Cycle No. 3
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
NOTE 18
DATA IO
VALID DATA
tLZWE
tHZWE
Document #: 001-44018 Rev. **
Page 8 of 11
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CY62177DV20 MoBL2™
Switching Waveforms (continued)
Figure 7 shows BHE/BLE controlled, OE LOW write cycle waveforms.[17]
Figure 7. Write Cycle No. 4
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
tHD
NOTE 18
DATA IO
VALID DATA
Truth Table
CE1 CE2 WE OE BHE BLE
Inputs/Outputs
Mode
Power
H
X
X
L
X
L
X
X
X
H
H
X
X
X
L
X
X
H
L
X
X
H
L
High Z
High Z
High Z
Deselect / Power Down
Deselect / Power Down
Deselect / Power Down
Read
Standby (ISB
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
)
)
X
H
H
)
Data Out (IO0–IO15
Data Out (IO0–IO7);
High Z (IO8–IO15
)
)
L
L
H
L
Read
)
)
L
H
H
L
L
H
High Z (IO0–IO7);
Data Out (IO8–IO15
Read
Active (ICC)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data In (IO0–IO15
Data In (IO0–IO7);
High Z (IO8–IO15
)
)
L
H
Write
)
)
L
H
L
X
L
H
High Z (IO0–IO7);
Data In (IO8–IO15
Write
Active (ICC)
)
Document #: 001-44018 Rev. **
Page 9 of 11
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CY62177DV20 MoBL2™
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
70
CY62177DV20LL-70BAI
51-85191 48-ball VFBGA (8.0 x 9.5 x 1.2 mm)
Industrial
Package Diagram
Figure 8. 48-Ball VFBGA (8.0 x 9.5 x 1.2 mm)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
3.75
B
4.00 0.10
B
4.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85191-**
-
.888
Document #: 001-44018 Rev. **
Page 10 of 11
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CY62177DV20 MoBL2™
Document History Page
Document Title: CY62177DV20 MoBL2™ 32-Mbit (2M x 16) Static RAM
Document Number: 001-44018
Orig. of
REV.
ECN NO. Issue Date
1910928
Change
Description of Change
**
See ECN VKN/AESA New Data Sheet
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-44018 Rev. **
Revised January 08, 2008
Page 11 of 11
MoBL is aregisteredtrademark andMore Battery Lifeis atrademark of Cypress Semiconductor. All product andcompany names mentioned in this document are the trademarks of their respective holders.
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