CY62168DV30LL-55BVI [CYPRESS]
16-Mbit (2M x 8) MoBL㈢ Static RAM; 16兆位（ 2M ×8 ）的MoBL ？静态RAM
| 型号： | CY62168DV30LL-55BVI |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (2M x 8) MoBL㈢ Static RAM |
| 文件： | 总9页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62168DV30 MoBL®
16-Mbit (2M x 8) MoBL® Static RAM
reduces power consumption. The device can be put into
standby mode reducing power consumption by 90% when
addresses are not toggling. The device can be put into standby
mode reducing power consumption by more than 99% when
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)
LOW. The input/output pins (I/O0 through I/O7) are placed in
a high-impedance state when: deselected Chip Enable 1
(CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled
(OE HIGH), or during a write operation (Chip Enable 1 (CE1)
LOW and Chip Enable 2 (CE2) HIGH and WE LOW).
Features
• Very high speed
— 55 ns
• Wide voltage range
— 2.2V – 3.6V
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = fMax (55 ns Speed)
• Ultra-low standby power
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address
pins(A0 through A20).
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip
Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
• Available in Pb-free and non Pb-free 48-ball VFBGA
package
Functional Description[1]
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
LOW and CE2 HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
The CY62168DV30 is a high-performance CMOS static RAMs
organized as 2048Kbit words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
Data in Drivers
A0
A1
A2
A3
A4
A
1
2
A56
3
4
5
2048K x 8
ARRAY
A
A7
A98
A10
A11
A12
6
7
POWER
DOWN
COLUMN
DECODER
CE
CE
1
2
I/O
WE
OE
Note:
1. For best-practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05329 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 27, 2006
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CY62168DV30 MoBL®
Pin Configuration[2]
48-ball VFBGA
Top View
1
2
4
3
5
6
DNU
DNU
A
2
A
A
OE
CE2
0
1
A
B
C
A
DNU
DNU
DNU
A
CE1
4
3
A
A
I/O
I/O
DNU
5
6
0
4
V
A
V
CC
I/O
A17
SS
D
E
F
I/O1
7
5
V
DNU
A
16
I/O
V
CC
SS
I/O
2
6
A
A
15
I/O
I/O
DNU
DNU
WE
14
3
7
A
A
A
G
H
DNU
A18
DNU
A19
13
20
12
A
A
A
A
10
9
11
8
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = fMax Standby ISB2(µA)
V
CC Range (V)
Speed
Product
Min.
2.2
Typ.[3]
Max.
3.6
(ns)
Typ.[3]
Max.
Typ.[3]
Max.
Typ.[3]
Max.
CY62168DV30LL
3.0
55
2
4
15
30
2.5
22
Notes:
2. DNU pins have to be left floating or tied to V to ensure proper operation.
SS
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
Document #: 38-05329 Rev. *F
Page 2 of 9
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CY62168DV30 MoBL®
DC Input Voltage[4, 5]......................–0.3V to VCC(max) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential........................................ –0.3V to VCC(max) + 0.3V
Range
Temperature (TA)[6]
VCC
[7]
DC Voltage Applied to Outputs
Industrial
–40°C to +85°C
2.2V – 3.6V
in High-Z State[4, 5]......................... –0.3V to VCC(max) + 0.3V
DC Electrical Characteristics (Over the Operating Range)
CY62168DV30-55
Parameter
VOH
Description
Test Conditions
Min. Typ.[3]
Max.
Unit
Output HIGH Voltage
2.2V < VCC < 2.7V
2.7V < VCC < 3.6V
2.2V < VCC < 2.7V
2.7V < VCC < 3.6V
2.2V < VCC < 2.7V
2.7V < VCC < 3.6V
2.2V < VCC < 2.7V
2.7V < VCC < 3.6V
GND < VI < VCC
IOH = −0.1 mA
IOH = −1.0 mA
IOL = 0.1 mA
IOL = 2.1 mA
2.0
2.4
V
V
V
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
0.4
1.8
2.2
–0.3
–0.3
–1
VCC + 0.3
VCC + 0.3
0.6
0.8
+1
+1
30
4
IIX
Input Leakage Current
Output Leakage Current
µA
µA
IOZ
ICC
GND < VO < VCC, Output disabled
–1
VCC Operating Supply Current f = fMax = 1/tRC
f = 1 MHz
VCC = 3.6V,
OUT = 0 mA,
CMOS level
15
mA
I
2
ISB1
Automatic CE Power-down
Current — CMOS Inputs
2.5
22
µA
µA
CE1 > VCC − 0.2V, CE2 < 0.2V,
VIN > VCC − 0.2V, VIN < 0.2V,
f = fMax (Address and Data Only),
f = 0 (OE, WE)
ISB2
Automatic CE Power-down
Current— CMOS Inputs
2.5
22
CE1 > VCC − 0.2V, CE2 < 0.2V,
V
IN > VCC − 0.2V or VIN < 0.2V,
f = 0, VCC = 3.6V
Capacitance[8]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
Max.
8
Unit
pF
pF
COUT
10
Notes:
4. V
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
6. T is the “Instant-On” case temperature.
A
7. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 100 µs wait time after V stabilization.
CC
CC
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05329 Rev. *F
Page 3 of 9
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CY62168DV30 MoBL®
Thermal Resistance[8]
Parameter
ΘJA
Description
Test Conditions
VFBGA
Unit
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch,
2-layer printed circuit board
55
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
16
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC
OUTPUT
90%
10%
90%
10%
50 pF
R2
GND
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5V
16600
15400
8000
1.2
3.0V
1103
1554
645
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
Conditions
Min.
Typ.[3]
Max.
Unit
VCC for Data Retention
1.5
3.6
10
V
Data Retention Current VCC = 1.5V
µA
CE1 > VCC − 0.2V or CE2 <0.2V
VIN > VCC − 0.2V or VIN < 0.2V
[8]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[9]
tR
Operation Recovery
Time
tRC
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
VCC(min)
V
V
CC
VCC(min)
DR
t
t
R
CDR
CE1
or
CE2
Note:
9. Full Device AC operation requires linear V ramp from V to V
> 100 µs or stable at V > 100 µs.
CC(min.)
CC
DR
CC(min.)
Document #: 38-05329 Rev. *F
Page 4 of 9
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CY62168DV30 MoBL®
Switching Characteristics Over the Operating Range [10]
55 ns
Parameter
Read Cycle
Description
Min.
55
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
10
55
25
OE LOW to Low Z[11]
5
10
0
OE HIGH to High Z[11, 12]
20
20
55
CE1 LOW and CE2 HIGH to Low Z[11]
CE1 HIGH or CE2 LOW to High Z[11, 12]
CE1 LOW and CE2 HIGH to Power-Up
CE1 HIGH or CE2 LOW to Power-Down
tPD
Write Cycle[13]
tWC
Write Cycle Time
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
40
25
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[11, 12]
WE HIGH to Low Z[11]
tHD
tHZWE
tLZWE
20
10
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of V
/2, input
CC(typ.)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ.)
OL OH
11. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
12. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
13. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05329 Rev. *F
Page 5 of 9
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CY62168DV30 MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
t
RC
CE1
CE2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
VCC
SUPPLY
CURRENT
t
LZCE
t
PD
ICC
t
PU
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[13, 17, 18]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
See Note 19
VALID DATA
DATA I/O
t
HZOE
Notes:
14. Device is continuously selected. OE, CE = V , CE = V .
IH
1
IL
2
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
17. Data I/O is high impedance if OE = V
.
IH
18. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.
1
2
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05329 Rev. *F
Page 6 of 9
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CY62168DV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled)[13, 17, 18]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
t
HA
AW
t
PWE
WE
OE
t
t
HD
SD
DATA I/O
VALID DATA
Write Cycle No. 3 (WE Controlled, OE LOW)[19]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA I/O
See Note 19
VALID DATA
t
t
LZWE
HZWE
Truth Table
CE1
H
CE2
WE
X
OE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
X
L
High Z
Deselect/Power-down
Deselect/Power-down
Read
)
X
X
X
High Z
)
L
H
H
H
H
L
Data Out (I/O0-I/O7)
Data in (I/O0-I/O7)
High Z
)
L
L
X
Write
)
L
H
H
Output Disabled
)
Document #: 38-05329 Rev. *F
Page 7 of 9
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CY62168DV30 MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
55
CY62168DV30LL-55BVI
CY62168DV30LL-55BVXI
51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm)
48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of these parts
Package Diagram
48-ball VFBGA (8 x 9.5 x 1 mm) (51-85178)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
4.00 0.10
3.75
B
4.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85178-**
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are trademarks of their respective holders.
Document #: 38-05329 Rev. *F
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62168DV30 MoBL®
Document History Page
Document Title: CY62168DV30 MoBL®, 16-Mbit (2M x 8) MoBL® Static RAM
Document Number: 38-05329
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
118409
Description of Change
09/30/02
02/05/03
GUG
DPM
New Data Sheet
*A
123693
Changed Advance Information to Preliminary
Added package diagram
*B
*C
*D
*E
126556
132869
272589
335864
04/24/03
01/15/04
See ECN
See ECN
DPM
XRJ
PCI
Minor change: Change sunset owner from DPM to HRT
Changed Preliminary to Final
Updated Final data sheet and added Pb-free package.
PCI
Removed redundant packages from Ordering Information Table
Added Address A20 to ball G2 in the Pin Configuration
*F
492895
See ECN
VKN
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 70 ns speed bin
Removed L power bin from product offering
Updated Ordering Information Table
Document #: 38-05329 Rev. *F
Page 9 of 9
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相关型号：
CY62168DV30LL-55BVXIT
Standard SRAM, 2MX8, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM PITCH, LEAD FREE, VFBGA-48
CYPRESS
CY62168DV30LL-70BVI
Standard SRAM, 2MX8, 70ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, VFBGA-48
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