CY29773AI [CYPRESS]
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer; 2.5V或3.3V ， 200兆赫， 12路输出零延迟缓冲器
| 型号： | CY29773AI |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29773
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Description
• Output frequency range: 8.33 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 125 MHz
• 2.5V or 3.3V operation
The CY29773 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29773 features one LVPECL and two LVCMOS
reference clock inputs and provides 12 outputs partitioned in
three banks of four outputs each. Each bank divides the VCO
output per SEL(A:C) settings (see Table 2. Function Table
(Configuration Controls)). These dividers allow output-to-input
ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4,
1:1, and 5:6. Each LVCMOS-compatible output can drive 50Ω
series- or parallel-terminated transmission lines. For
series-terminated transmission lines, each output can drive
one or two traces, giving the device an effective fanout of 1:24.
• Split 2.5V/3.3V outputs
• ±2% max Output duty cycle variation
• 12 Clock outputs: drive up to 24 clock lines
• One feedback output
• Three reference clock inputs: LVPECL or LVCMOS
• 300-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
The PLL is ensured stable, given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies, from 8 MHz to 200 MHz. For normal
operation, the external feedback input FB_IN is connected to
the feedback output FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see Table 1. Frequency Table).
• Pin-compatible with MPC9773 and MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin 1.0-mm TQFP package
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
Sync
D Q
QA0
Frz
0
1
Phase
Detector
VCO
TCLK0
TCLK1
0
1
QA1
QA2
QA3
52 51 50 49 48 47 46 45 44 43 42 41 40
39
LPF
TCLK_SEL
V SS
AV SS
MR#/OE
SCLK
1
2
FB_IN
QB0
38
37
36
35
34
33
32
31
30
29
28
27
Sync
Frz
V DDQB
QB1
3
D
QB0
QB1
Q
SDA TA
4
V SS
QB2
FB_SEL2
PLL_EN
5
QB2
QB3
6
FB_SEL2
V DDQB
QB3
REF_SEL
TCLK_SEL
TCLK0
7
CY29773
8
9
FB_IN
V SS
MR#/OE
TCLK1
10
11
12
13
Sync
Frz
D
Q
QC0
QC1
FB_OUT
V DD
Power-On
Reset
PECL_CLK
PECL_CLK#
AV DD
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
FB_SEL0
Sync
Frz
2
QC2
D Q
SELA(0,1)
14 15 16 17 18 19 20 21 22 23 24 25 26
QC3
2
2
SELB(0,1)
SELC(0,1)
0
1
Sync
Frz
FB_OUT
D
Q
/4, /6, /8, /10
Sync Pulse
/2
Sync
Frz
2
SYNC
D Q
FB_SEL(0,1)
Data Generator
SCLK
Output Disable
Circuitry
12
SDATA
INV_CLK
Cypress Semiconductor Corporation
Document #: 38-07573 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 27, 2003
CY29773
Pin Description [1]
Pin
Name
I/O
Type
Description
11
PECL_CLK I, PU
LVPECL LVPECL reference clock input.
LVPECL LVPECL reference clock input.
12
PECL_CLK#
TCLK0
I
9
I, PU LVCMOS LVCMOS/LVTTL reference clock input.
I, PU LVCMOS LVCMOS/LVTTL reference clock input.
10
TCLK1
44,46,48,50
32,34,36,38
16,18,21,23
29
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
FB_IN
O
O
O
O
LVCMOS Clock output bank A.
LVCMOS Clock output bank B.
LVCMOS Clock output bank C.
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
31
I, PU LVCMOS Feedback clockinput. Connect to FB_OUT fornormaloperation. This
input should be at the same voltage rail as input reference clock. See
Table 1. Frequency Table.
25
6
SYNC
O
LVCMOS Synchronous pulse output. This output is used for system synchro-
nization.
PLL_EN
MR#/OE
TCLK_SEL
REF_SEL
VCO_SEL
INV_CLK
I, PU LVCMOS PLL enable/bypass input. When Low, PLL is disabled/bypassed and
the input clock connects to the output dividers.
2
I, PU LVCMOS Master reset and Output enable/disable input. See Table 2.
Function Table (Configuration Controls).
8
I, PU LVCMOS LVCMOS Clock reference select input. See Table 2. Function Table
(Configuration Controls).
7
I, PU LVCMOS LVCMOS/LVPECL Reference select input. See Table 2. Function
Table (Configuration Controls).
52
14
I, PU LVCMOS VCO Operating frequency select input. See Table 2. Function Table
(Configuration Controls).
I, PU LVCMOS QC(2,3) Phase selection input. See Table 2. Function Table (Config-
uration Controls).
5,26,27
42,43
FB_SEL(2:0) I, PU LVCMOS Feedback divider select input. See Table 6.
SELA(1,0)
SELB(1,0)
SELC(1,0)
I, PU LVCMOS Frequency select input, Bank A. See Table 3. Function Table (Bank
A).
40,41
19,20
I, PU LVCMOS Frequency select input, Bank B. See Table 4. Function Table (Bank
B).
I, PU LVCMOS Frequency select input, Bank C. See Table 5. Function Table (Bank
C).
3
SCLK
I, PU LVCMOS Serial clock input.
4
SDATA
VDDQA
VDDQB
VDDQC
AVDD
I, PU LVCMOS Serial data input.
45,49
33,37
22,17
13
Supply
Supply
Supply
Supply
Supply
VDD
VDD
VDD
VDD
VDD
2.5V or 3.3V Power supply for bank A output clocks.[2,3]
2.5V or 3.3V Power supply for bank B output clocks.[2,3]
2.5V or 3.3V Power supply for bank C output clocks.[2,3]
2.5V or 3.3V Power supply for PLL.[2,3]
28
VDD
2.5V or 3.3V Power supply for core and inputs.[2,3]
1
AVSS
Supply Ground Analog Ground.
Supply Ground Common Ground.
15,24,30,35,39,47,51 VSS
Notes:
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
Document #: 38-07573 Rev. **
Page 2 of 12
CY29773
Table 1. Frequency Table
Feedback Output
Divider
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
VCO
÷4
Input Clock * 4
Input Clock * 6
Input Clock * 8
Input Clock * 10
Input Clock * 12
Input Clock * 16
Input Clock * 20
Input Clock * 24
Input Clock * 32
Input Clock * 40
50 MHz to 125 MHz
50 MHz to 95 MHz
÷6
33.3 MHz to 83.3 MHz
25 MHz to 62.5 MHz
20 MHz to 50 MHz
33.3 MHz to 63.3 MHz
25 MHz to 47.5 MHz
20 MHz to 38 MHz
÷8.
÷10
÷12
÷16
÷20
÷24
÷32
÷40
16.6 MHz to 41.6 MHz
12.5 MHz to 31.25 MHz
10 MHz to 25 MHz
16.6 MHz to 31.6 MHz
12.5 MHz to 23.75 MHz
10 MHz to19 MHz
8.3 MHz to 20.8 MHz
6.25 MHz to 15.625 MHz
5 MHz to 12.5 MHz
8.3 MHz to 15.8 MHz
6.25 MHz to 11.8 MHz
5 MHz to 9.5 MHz
Table 2. Function Table (Configuration Controls)
Control Default
0
1
PECL_CLK
REF_SEL
TCLK_SEL
VCO_SEL
PLL_EN
1
1
1
1
TCLK0, TCLK1
TCLK0
TCLK1
VCO÷2 (low input frequency range)
VCO÷1 (high input frequency range)
Bypass mode, PLL disabled. The input clock connects to the
output dividers
PLL enabled. The VCO output
connects to the output dividers
INV_CLK
MR#/OE
1
1
QC2 and QC3 are in phase with QC0 and QC1
QC2 and QC3 areinverted (180° phase
shift) with respect to QC0 and QC1
Outputs disabled (three-state) and reset of the device. During
reset/output disable the PLL feedback loop is open and the VCO
running at its minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during power-up.
Outputs enabled
Table 3. Function Table (Bank A)
Table 5. Function Table (Bank C)
VCO_SEL
SELA1
SELA0
QA(0:3)
÷8
VCO_SEL
SELC1
SELC0
QC(0:3)
÷4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷12
÷16
÷24
÷4
÷8
÷12
³16
÷2
÷6
÷4
÷8
÷6
÷12
÷8
Table 4. Function Table (Bank B)
Table 6. Function Table (FB_OUT)
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FB_OUT
VCO_SEL
SELB1
SELB0
QB(0:3)
÷8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
÷8
÷12
÷16
÷20
÷4
÷12
÷16
÷20
÷16
÷24
÷32
÷40
÷4
÷6
÷8
÷10
Document #: 38-07573 Rev. **
Page 3 of 12
CY29773
Table 6. Function Table (FB_OUT) (continued)
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷6
÷8
÷10
÷8
÷12
÷16
÷20
Document #: 38-07573 Rev. **
Page 4 of 12
CY29773
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
Description
DC Supply Voltage
Condition
Functional
Min.
–0.3
2.375
–0.3
–0.3
Max.
5.5
Unit
V
DC Operating Voltage
3.465
V
DC Input Voltage
Relative to VSS
Relative to VSS
VDD + 0.3
VDD + 0.3
V
V
VOUT
VTT
DC Output Voltage
Output termination Voltage
Latch-up Immunity
VDD ÷ 2
V
LU
Functional
200
–
mA
mVp-p
°C
RPS
TS
Power Supply Ripple
Ripple Frequency < 100 kHz
Non-functional
Functional
150
Temperature, Storage
–65
–40
+150
+85
+150
23
TA
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
°C
TJ
Functional
°C
ØJC
ØJA
ESDH
FIT
Functional
°C/W
°C/W
V
Functional
55
2000
Manufacturing test
10
ppm
DC Electrical Specifications (VDD = 2.5V ±5%, TA = –40°C to +85°C)
Parameter Description Condition
VIL Input Voltage, Low
Min.
–
Typ.
Max.
Unit
V
LVCMOS
LVCMOS
LVPECL
LVPECL
–
–
0.7
VIH
Input Voltage, High
1.7
250
1.0
–
VDD+0.3
V
VPP
VCMR
VOL
VOH
IIL
Peak-Peak Input Voltage
Common Mode Range[4]
Output Voltage, Low[5]
Output Voltage, High[5]
Input Current, Low[5]
Input Current, High[6]
PLL Supply Current
–
1000
mV
V
–
VDD – 0.6
IOL = 15 mA
–
0.6
–
V
IOH = –15 mA
1.8
–
–
V
VIL = VSS
–
–100
100
10
8
µA
µA
mA
mA
mA
pF
Ω
IIH
VIL = VDD
–
–
IDDA
IDDQ
IDD
AVDD only
–
5
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
All VDD pins except AVDD
Outputs loaded @ 100 MHz
–
–
–
135
4
–
CIN
–
–
ZOUT
14
18
22
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)
Parameter
VIL
Description
Input Voltage, Low
Condition
Min.
–
Typ.
–
Max.
0.8
Unit
V
LVCMOS
LVCMOS
LVPECL
LVPECL
VIH
Input Voltage, High
2.0
250
1.0
–
–
VDD+0.3
1000
VDD – 0.6
0.55
V
VPP
Peak-Peak Input Voltage
Common Mode Range[4]
Output Voltage, Low[5]
–
mV
V
VCMR
VOL
–
IOL = 24 mA
IOL = 12 mA
IOH = –24 mA
VIL = VSS
–
V
–
–
0.30
VOH
IIL
Output Voltage, High[5]
Input Current, Low[6
2.4
–
–
–
V
–
–100
µA
Notes:
4.
V
CMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input
swing is within the VPP (DC) specification.
5. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated
transmission lines.
6. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07573 Rev. **
Page 5 of 12
CY29773
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued)
Parameter
IIH
Description
Input Current, High[6]
PLL Supply Current
Condition
VIL = VDD
Min.
–
Typ.
–
Max.
Unit
µA
mA
mA
mA
pF
100
10
8
IDDA
AVDD only
–
5
IDDQ
IDD
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Impedance
All VDD pins except AVDD
Outputs loaded @ 100 MHz
–
–
–
225
4
–
CIN
–
–
ZOUT
12
15
18
Ω
AC Electrical Specifications (VDD = 2.5V ±5%, TA = –40°C to +85°C)[7]
Parameter Description Condition
fVCO VCO Frequency
Min.
200
50
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
380
95
Unit
MHz
MHz
fin
Input Frequency
÷4 Feedback
÷6 Feedback
33.3
25
63.3
47.5
38
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode (PLL_EN = 0)
20
16.6
12.5
10
31.6
23.75
19
8.3
6.25
5
15.8
11.8
9.5
0
200
75
frefDC
VPP
Input Duty Cycle
25
%
mV
V
Peak-Peak Input Voltage
Common Mode Range[8]
TCLK Input Rise/FallTime
Maximum Output Frequency
LVPECL
500
1.2
–
1000
VDD – 0.6
1.0
VCMR
tr , tf
LVPECL
0.7V to 1.7V
÷2 Output
÷4 Output
÷6 Output
÷8 Output
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
ns
fMAX
100
50
190
95
MHz
33.3
25
63.3
47.5
38
20
16.6
12.5
10
31.6
23.75
19
8.3
–
15.8
20
fSCLK
DC
Serial Clock Frequency
Output Duty Cycle
MHz
%
fMAX < 100 MHz
fMAX > 100 MHz
0.6V to 1.8V
47.5
45
52.5
55
tr , tf
t(φ)
Output Rise/Fall times
0.1
–125
–125
1.0
ns
ps
Propagation Delay (static phase
offset)
TCLK to FB_IN
PCLK to FB_IN
125
125
Notes:
7. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing
lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
Document #: 38-07573 Rev. **
Page 6 of 12
CY29773
AC Electrical Specifications (VDD = 2.5V ±5%, TA = –40°C to +85°C)[7]
Parameter
tsk(O)
Description
Condition
Skew within Bank A
Skew within Bank B
Skew within Bank C
Min.
–
Typ.
Max.
Unit
Output-to-Output Skew
–
75
100
150
400
10
10
–
ps
–
–
–
–
tsk(B)
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
–
–
ps
ns
tPLZ, HZ
tPZL, ZH
BW
–
–
–
–
ns
PLL Closed Loop Bandwidth (-3dB) ÷4 Feedback
÷6 Feedback
–
1.3 - 2.0
0.7 - 1.3
0.9 - 1.3
0.6 - 1.1
0.6 - 0.9
0.4 - 0.6
0.6 - 0.9
7
MHz
–
–
÷8 Feedback
–
–
÷10 Feedback
–
–
÷12 Feedback
–
–
÷16 Feedback
–
–
÷20 Feedback
–
–
tJIT(CC)
Cycle-to-Cycle Jitter
Period Jitter
Same frequency (125 MHz)
RMS (1σ)
–
30
ps
ps
Same frequency
Multiple frequencies
–
–
–
–
–
6
150
435
30
tJIT(PER)
Same frequency (125 MHz)
RMS (1σ)
Same frequency
–
–
–
–
45
–
75
235
150
1
Multiple frequencies
tJIT(φ)
tLOCK
I/O Phase Jitter
–
ps
Maximum PLL Lock Time
–
ms
AC Electrical Specifications (VDD = 3.3V ±5%, TA = –40°C to +85°C)[7]
Parameter Description Condition
fVCO VCO Frequency
Min.
200
50
Typ.
–
Max.
500
Unit
MHz
MHz
fin
Input Frequency
÷4 Feedback
–
125
÷6 Feedback
33.3
25
–
83.3
62.5
50
÷8 Feedback
–
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode (PLL_EN = 0)
20
–
16.6
12.5
10
–
41.6
31.25
25
–
–
8.3
6.25
5
–
20.8
15.625
12.5
200
–
–
0
–
frefDC
VPP
Input Duty Cycle
25
–
75
%
mV
V
Peak-Peak Input Voltage
Common Mode Range[8]
TCLK Input Rise/FallTime
LVPECL
500
1.2
–
–
1000
VDD–0.9
1.0
VCMR
tr , tf
LVPECL
–
0.8V to 2.0V
–
ns
Document #: 38-07573 Rev. **
Page 7 of 12
CY29773
AC Electrical Specifications (VDD = 3.3V ±5%, TA = –40°C to +85°C)[7]
Parameter
fMAX
Description
Condition
Min.
100
50
33.3
25
20
16.6
12.5
10
8.3
–
Typ.
Max.
Unit
Maximum Output Frequency
÷2 Output
÷4 Output
÷6 Output
÷8 Output
–
200
125
83.3
62.5
50
MHz
–
–
–
fMAX
Maximum Output Frequency
(continued)
÷10 Output
÷12 Output
÷16 Output
÷20 Output
÷24 Output
–
MHz
–
41.6
31.25
25
–
–
–
20.8
20
fSCLK
DC
Serial Clock Frequency
Output Duty Cycle
–
MHz
%
f
MAX < 100 MHz
48
45
0.1
–125
–125
–
–
52
fMAX > 100 MHz
–
55
tr , tf
t(φ)
Output Rise/Fall times
0.55V to 2.4V
–
1.0
125
125
75
ns
ps
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD
PCLK to FB_IN, same VDD
Skew within Bank A
Skew within Bank B
Skew within Bank C
–
–
tsk(O)
Output-to-Output Skew
–
ps
–
–
100
150
325
8
–
–
tsk(B)
tPLZ, HZ
tPZL, ZH
BW
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
–
–
ps
ns
–
–
–
–
8
ns
PLL Closed Loop Bandwidth
(–3 dB)
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
–
1.3–2.0
0.7–1.3
0.9–1.3
0.6–1.1
0.6–0.9
0.4–0.6
0.6–0.9
7
–
MHz
–
–
–
–
–
–
–
–
–
–
–
–
tJIT(CC)
Cycle-to-Cycle Jitter
Period Jitter
Same frequency (125 MHz)
RMS (1σ)
–
30
ps
ps
Same frequency
–
–
–
–
–
6
100
375
30
Multiple frequencies
tJIT(PER)
Same frequency (125 MHz)
RMS (1σ)
Same frequency
Multiple frequencies
I/O same VDD
––
–
45
–
75
225
150
1
tJIT(φ)
tLOCK
I/O Phase Jitter
–
–
ps
Maximum PLL Lock Time
–
–
ms
SYNC Output
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. The following
timing diagram illustrates various waveforms for the SYNC
output. Note that the SYNC output is defined for all possible
combinations of the QA and QC outputs even though under
some relationships the lower frequency clock could be used
as a synchronizing signal.
In situations where output frequency relationships are not
integer multiples of each other the SYNC output provides a
signal for system synchronization. The CY29773 monitors the
relationship between the QA and the QC output clocks. It
provides a low going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
Document #: 38-07573 Rev. **
Page 8 of 12
CY29773
VCO
1:1 Mode
2:1 Mode
QA
QC
SYNC
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
4:1 Mode
QA
QC
SYNC
QC
QA
SYNC
4:3 Mode
6:1 Mode
QA
QC
SYNC
QA
QC
SYNC
Figure 1.
Power Management
data. An output is frozen when a logic ‘0’ is programmed and
enabled when a logic ‘1’ is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
The individual output enable/freeze control of the CY29773
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
‘0’ state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
The serial input register is programmed through the SDATA
input by writing a logic ‘0’ start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
Document #: 38-07573 Rev. **
Page 9 of 12
CY29773
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Figure 2.
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
Zo = 50 ohm
Differential
Pulse
Zo = 50 ohm
Generator
Z = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
RT = 50 ohm
VTT
Figure 4. PECL_CLK AC Test Reference for VDD = 3.3V/2.5V
PECL_CLK
VCMR
PECL_CLK
VPP
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 5. LVPECL Propagation Delay t(φ), Static Phase Offset
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 6. LVCMOS Propagation Delay t(φ), Static Phase Offset
Document #: 38-07573 Rev. **
Page 10 of 12
CY29773
VDD
VDD/2
GND
tP
T0
DC = tP / T0 x 100%
Figure 7. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Figure 8. Output-to-Output Skew, tsk(O)
Ordering Information
Part Number
Package Type
Product Flow
CY29773AI
52-pin TQFP
52-pin TQFP – Tape and Reel
Industrial, –40°C to +85°C
Industrial, –40°C to 85°C
CY29773AIT
Package Drawing and Dimension
52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07573 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29773
Document History Page
Document Title:CY29773 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Document Number: 38-07573
Orig. of
REV.
ECN No. Issue Date
129007 09/02/03
Change
Description of Change
**
RGL
New Data Sheet
Document #: 38-07573 Rev. **
Page 12 of 12
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