CY292510ZCT [CYPRESS]
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 4.40 MM, TSSOP-24;
| 型号： | CY292510ZCT |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, 4.40 MM, TSSOP-24 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY292510
200-MHz, Ten-output Zero Delay Buffer/PLL
Features
Description
• Output frequency range: 25 MHz to 200 MHz
• 10 LVCMOS outputs
• One feedback output
• Output-to-output skew < 100 ps
• Cycle-to cycle jitter < 100 ps
The CY292510 is a 3.3V zero delay buffer designed to
distribute high-speed clocks in PC, workstation, datacom,
telecom, and other high-performance applications. It is ideal
for use in SDRAM memory applications, and conforms to the
JEDEC JC40/JC42.5 specification supporting SDRAM DIMM
applications.
• ± 125-ps static phase error: 66 MHz to 166 MHz
• Spread-Spectrum-compatible
• Integrated series damping resistors specifically
designed for registered SDRAM DIMM applications –
JEDEC-JC42.5-compliant
The CY292510 has one bank of outputs with output enable
control. Input-to-output skew can be adjusted by varying
load/delay on feedback path. When OE is low, clock outputs
are forced low. VDDA can be strapped low to force device into
test mode. See Table 4.
• Externally controllable output delay
• Output enable/disable control
• 24-pin TSSOP package
Table 1. Function Table[1]
OE
1Y(0:9) Outputs
LOW
FBOUT
REF
LOW
HIGH
REF
REF
Pin Configuration
Block Diagram
FBOUT
1Y0
VSSA
VDD
1Y0
1Y1
1Y2
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
REF
VDDA
VDD
1Y9
1Y8
VSS
1Y1
1Y2
1Y3
FBIN
REF
PLL
1
MUX
1Y4
VSS
VSS
0
1Y5
1Y6
1Y7
1Y8
1Y9
1Y3
1Y4
VDD
1Y7
1Y6
1Y5
VDD
VDDA
SEL
9
10
11
12
OE
FBOUT
FBIN
OE
Note:
1. See Table 4 for additional logic configurations. REF is fixed frequency input.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07472 Rev. **
Revised October 11, 2002
CY292510
Pin Description
Pin
Name
I/O
Description
24
12
13
REF
I
Input reference pin.
Feedback Output. Not affected by the OE pin.
FBOUT
FBIN
O
I
This pin is to be connected to the FBOUT pin. A timing delay may be inserted to change the
delay through the device.
11
OE
I
Output Enable clock (high active). OE low places CLK(0:9) into low state. See Block Diagram.
2, 10, 14, 22
23
VDD
VDDA
PWR 3.3V supply for core logic, inputs and outputs.
PWR Power for internal analog circuitry. This supply should have separate de coupling. For test
purposes, when VDDA is strapped to ground the internal PLL is shut off and bypassed and
REF is buffered directly to device outputs( see Table 4).
3, 4, 5, 8, 9, 15, 1Y(0:9)
16, 17, 20, 21
O
Low skew clock outputs. Outputs enabled by OE in high state.
6, 7, 18, 19
1
VSS
PWR Ground pins for the core logic and I/Os.
PWR Ground pin for analog circuitry.
VSSA
Table 2. Absolute Maximum Ratings[2]
Parameter
Description
Commercial
–0.5 to +4.6
–0.5 to VDD + 0.5
Unit
V
VDD, VDDA
Supply Voltage Range
Input Voltage Range
VI[3]
V
[3]
VO
IK (VI<0)
IOK (VO<0 or VO>VDD Terminal voltage with respect to VSS (inputs VIH2.5, VIL2.5 ±50
Voltage range applied to any output in the high or low state –0.5 to VDD+0.5
V
I
Input clamp current –50
mA
mA
mA
mA
W
IO (VO = 0 to VDD
)
Continuous Output Current
±50
V
DD or VSS
Continuous Current
±100
TA = 50°C (in still air)[4] Maximum power dissipation
0.7
TSTG
Storage Temperature Range
–65°C to +150°C
°C
Table 3. Capacitance[5]
Parameter
Description
Min.
Typ.
Max.
Unit
pF
CIN
CO
Input Capacitance VIN = VDD or VSS
Output Capacitance VO = VDD or VSS
–
–
5
6
–
–
pF
Table 4. Test Mode Table (VDDA = 0V)
INPUTS
OUTPUTS
OE
REF
LOW
HIGH
LOW
HIGH
1Y(0:9)
FBOUT
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
Notes:
2. Stresses beyond those listed under “ absolute maximum ratings” may cause permanent damage to the device. These are stresses rating only and functional
operation of the device at these or any other conditions beyond those indicated under “ recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
4. The maximum package power dissipation is calculated using a junction temperature or 150°C and board trace length of 750 mils.
5. Unused inputs must be held high or low to prevent them from floating.
Document #: 38-07472 Rev. **
Page 2 of 6
CY292510
Table 5. Recommended Operating Conditions
Parameter Description
Min.
3.0
3.0
0
Typ.
3.3
Max.
3.6
3.6
VDD
–12
12
Unit
V
VDD
VDDA
VIN
IOH
IOL
Supply voltage
Analog supply voltage
Voltage applied to input pins
High level output current
Low level output current
Operating free-air temperature
3.3
V
V
–
–
–
–
mA
mA
°C
–
TA
0
85
Table 6. DC Parameters (VDD = VDDA = 3.3V ±10%, TA = 0°C to +85°C)
Parameter
VIH
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
HIGH Level input voltage
LOW level input voltage
HIGH level output voltage
2.0
VIL
0.8
V
VOH
Min. to Max.
DD = 3V
IOH = –100 µA
VDD–0.2
2.1
V
IOH = –12 mA
IOH = -6 mA
IOL =100 µA
IOL = 12 mA
IOL= 6 mA
V
V
VDD = 3V
2.4
VOL
IOH
IOL
LOW level output voltage
HIGH level output current
LOW level output current
Clamp voltage
Min. to Max.
0.2
0.8
VDD = 3V
VDD = 3V
0.55
VDD = 3.135V
VO = 1V
–32
VDD = 3.3V
VO = 1.65V
VO = 3.135V
VO = 1.95V
VO = 1.65V
VO = 0.4V
–36
mA
mA
VDD = 3.465V
VDD = 3.135V
–12
34
VDD = 3.3V
40
VDD = 3.465V
VDD = 3V
14
–1.2
±5
VIK
IIN = –18 mA
VI = VDD or VSS
V
II
Input leakage current per pin VDD = 3.6V
µA
mA
mA
IDDA
IDDQ
∆IDDQ
PLL supply current
Min. to Max.
VDD = 3.6V
2.3
3.5
5
Quiescent supply current
IO = 0 VIN = VDD or VSS
Change in quiescent current VDD = 3.3 V to 3.6V One input at VDD – 0.6V,
other inputs at VDD or
VSS
500
µA
IDD
Dynamic supply current
VDD = 3.6V
Outputsloaded at133MHz
200
mA
[6, 7, 8, 9, 10]
Table 7. AC Parameters (VDD = VDDA = 3.3V ±10%, TA = 0°C to +85°C)
VDD = 3.3V ± 0.3V
Min. Typ. Max.
200
Parameter
From Input/Condition
Reference Clock
To Output
Unit
MHz
%
Fin
25
40
Duty Cycle
Fout
Reference Clock
60
Output Operating Frequency
30-pF load
25
185
200
125
MHz
25-pF load
FBIN
25
tPHASEerror[11],static REF = 66 to 166 MHz
offset (normalized)
–125
pS
%
Duty Cycle
Any clock out or FBOUT
45
55
Notes:
6. Parameters are guaranteed by design and characterization and are not 100% production tested.
7. The tSK(0) specification is only valid for equal loading of all outputs (30 pF//500Ω) for Fout < 185 MHz and (25 pF//500Ω) for Fout > 185 MHz.
8. The test load is 30 pF//500Ω for Fout < 185 MHz and 25 pF//500Ω for Fout > 185 MHz.
9. See Figure 2.
10. OE = VDD
.
11. Uses the averaging feature of the scope to remove the jitter component.
Document #: 38-07472 Rev. **
Page 3 of 6
CY292510
Table 7. AC Parameters (VDD = VDDA = 3.3V ±10%, TA = 0°C to +85°C) (continued)[6, 7, 8, 9, 10]
tsk(o)[6,7,9]
Skew, Output to Output
Any clock out
100
pS
pS
nS
nS
Jitter(cycle-to-cycle)
Any clock out or FBOUT
Any clock out or FBOUT
Any clock out or FBOUT
Any clock out or FBOUT
75
3
[13]
tR
0.5
0.5
2.2
2.2
[13]
tF
tPD (propagation delay REF
- bypass mode)
ns
[12]
TSTABIL
Stabilization time
FBOUT
1
mS
Parameter Measurement Information
From Output
Under Test
VOH
VOL
2 V
500 Ohm
30 pF
2 V
Output
50% VDD
tf
0.4 V
0.4 V
tr
Load Circuit for Outputs
25 pF load w hen Fout > 185 MHz
Output Rise/Fall Time
Figure 1. Load Circuit and Voltage Waveforms[14, 15, 16]
CLKIN
FBIN
tphase error
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Phase Error and Skew Calculations
Notes:
12. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency
fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given in
the switching characteristics table are not applicable.
13. tR/tF are measured at 0.4V to 2.0V.
14. CL includes probe and jig capacitance.
15. All input pulses are supplied by generators having the following characteristics: input frequency ≤ 100 MHz, Zo = 50Ω, tr ≤ 1.2 ns, tf < 1.2 ns.
16. The outputs are measured one at a time with one transition per measurement.
Document #: 38-07472 Rev. **
Page 4 of 6
CY292510
Ordering Information
Part Number
Package Type
Production Flow
Commercial, 0°C to +85°C
Commercial, 0°C to +85°C
CY292510ZC
24-pin TSSOP
CY292510ZCT
24-pin TSSOP–Tape and Reel
Package Drawing and Dimension
24-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24
51-85119-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07472 Rev. **
Page 5 of 6
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY292510
Document History Page
Document Title: CY292510 200-MHz, Ten-output Zero Delay Buffer/PLL
Document Number: 38-07472
Orig. of
Rev.
ECN No. Issue Date Change
Description of Change
**
118946
10/14/02
RGL
New Data Sheet
Document #: 38-07472 Rev. **
Page 6 of 6
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